diff --git a/Documentation/README.html b/Documentation/README.html index cbf33411f24..0083b251371 100644 --- a/Documentation/README.html +++ b/Documentation/README.html @@ -8,7 +8,7 @@

NuttX README Files

-

Last Updated: March 22, 2018

+

Last Updated: March 26, 2018

@@ -166,6 +166,8 @@ nuttx/ | | `- README.txt | |- ne64badge/ | | `- README.txt + | |- nrf52-pca10040/ + | | `- README.txt | |- ntosd-dm320/ | | |- doc/README.txt | | `- README.txt diff --git a/README.txt b/README.txt index 57b46522ccc..0f8958db95e 100644 --- a/README.txt +++ b/README.txt @@ -1735,6 +1735,8 @@ nuttx/ | | `- README.txt | |- ne63badge/ | | `- README.txt + | |- nrf52-pca10040/ + | | `- README.txt | |- ntosd-dm320/ | | |- doc/README.txt | | `- README.txt diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0d51ed92ab1..e3224d046f2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -189,6 +189,17 @@ config ARCH_CHIP_MOXART ---help--- MoxART family +config ARCH_CHIP_NRF52 + bool "Nordic NRF52" + select ARCH_CORTEXM4 + select ARCH_HAVE_CMNVECTOR + select ARMV7M_CMNVECTOR + #select ARCH_HAVE_MPU + #select ARM_HAVE_MPU_UNIFIED + select ARCH_HAVE_FPU + ---help--- + Nordic NRF52 architectures (ARM Cortex-M4). + config ARCH_CHIP_NUC1XX bool "Nuvoton NUC100/120" select ARCH_CORTEXM0 @@ -551,6 +562,7 @@ config ARCH_CHIP default "lpc43xx" if ARCH_CHIP_LPC43XX default "lpc54xx" if ARCH_CHIP_LPC54XX default "moxart" if ARCH_CHIP_MOXART + default "nrf52" if ARCH_CHIP_NRF52 default "nuc1xx" if ARCH_CHIP_NUC1XX default "sama5" if ARCH_CHIP_SAMA5 default "samdl" if ARCH_CHIP_SAMD || ARCH_CHIP_SAML @@ -797,6 +809,9 @@ endif if ARCH_CHIP_MOXART source arch/arm/src/moxart/Kconfig endif +if ARCH_CHIP_NRF52 +source arch/arm/src/nrf52/Kconfig +endif if ARCH_CHIP_NUC1XX source arch/arm/src/nuc1xx/Kconfig endif diff --git a/arch/arm/include/nrf52/chip.h b/arch/arm/include/nrf52/chip.h new file mode 100644 index 00000000000..9007d9557d3 --- /dev/null +++ b/arch/arm/include/nrf52/chip.h @@ -0,0 +1,122 @@ +/************************************************************************************ + * arch/arm/include/nrf52/chip.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_NRF52_CHIP_H +#define __ARCH_ARM_INCLUDE_NRF52_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + *********************************************************************************** + +/* NVIC priority levels *************************************************************/ +/* Each priority field holds a priority value, 0-31. The lower the value, the greater + * the priority of the corresponding interrupt. + * + * The Cortex-M4 core supports 8 programmable interrupt priority levels. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* All bits[7:5] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x20 /* Steps between priorities */ + +/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled + * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most + * interrupts will not have execution priority. SVCall must have execution + * priority in all cases. + * + * In the normal cases, interrupts are not nest-able and all interrupts run + * at an execution priority between NVIC_SYSH_PRIORITY_MIN and + * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). + * + * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special + * high priority interrupts are supported. These are not "nested" in the + * normal sense of the word. These high priority interrupts can interrupt + * normal processing but execute outside of OS (although they can "get back + * into the game" via a PendSV interrupt). + * + * In the normal course of things, interrupts must occasionally be disabled + * using the up_irq_save() inline function to prevent contention in use of + * resources that may be shared between interrupt level and non-interrupt + * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, + * do we disable all interrupts (except SVCall), or do we only disable the + * "normal" interrupts. Since the high priority interrupts cannot interact + * with the OS, you may want to permit the high priority interrupts even if + * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be + * used to select either behavior: + * + * ----------------------------+--------------+---------------------------- + * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES + * ----------------------------+--------------+--------------+------------- + * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO + * ----------------------------+--------------+--------------+------------- + * | | | SVCall + * | SVCall | SVCall | HIGH + * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL + * | | MAXNORMAL | + * ----------------------------+--------------+--------------+------------- + */ + +#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) +# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) +# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY +# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX +#else +# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) +# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX +# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY +# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_NRF52_CHIP_H */ diff --git a/arch/arm/include/nrf52/irq.h b/arch/arm/include/nrf52/irq.h new file mode 100644 index 00000000000..439721d0c99 --- /dev/null +++ b/arch/arm/include/nrf52/irq.h @@ -0,0 +1,111 @@ +/******************************************************************************************** + * arch/arm/include/nrf52xxx/irq.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +/* This file should never be included directed but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_NRF52_IRQ_H +#define __ARCH_ARM_INCLUDE_NRF52_IRQ_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +#endif + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to bits in + * the NVIC. This does, however, waste several words of memory in the IRQ to handle mapping + * tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define NRF52_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define NRF52_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define NRF52_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define NRF52_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define NRF52_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define NRF52_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define NRF52_IRQ_SIGNVALUE (7) /* Vector 7: Sign value */ +#define NRF52_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define NRF52_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define NRF52_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define NRF52_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define NRF52_IRQ_EXTINT (16) /* Vector 16: Vector number of the first external interrupt */ + +/* Cortex-M4 External interrupts (vectors >= 16) */ + +#if defined(CONFIG_ARCH_FAMILY_NRF52832) +# include +#else +# error "Unsupported NRF52XX MCU" +#endif + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +#ifndef __ASSEMBLY__ +typedef void (*vic_vector_t)(uint32_t *regs); + +/******************************************************************************************** + * Public Function Prototypes + ********************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_NRF52_IRQ_H */ diff --git a/arch/arm/include/nrf52/nrf52832_irq.h b/arch/arm/include/nrf52/nrf52832_irq.h new file mode 100644 index 00000000000..ca0e6c478fb --- /dev/null +++ b/arch/arm/include/nrf52/nrf52832_irq.h @@ -0,0 +1,96 @@ +/**************************************************************************************************** + * arch/arm/include/nrf52/nrf52_irq.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_NRF52_NRF52_IRQ_H +#define __ARCH_ARM_INCLUDE_NRF52_NRF52_IRQ_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Cortex-M4 External interrupts (vectors >= 16) */ + +#define NRF52_IRQ_POWER_CLOCK (NRF52_IRQ_EXTINT+0) /* VOD Windowed watchdog timer, Brownout detect */ +#define NRF52_IRQ_RADIO (NRF52_IRQ_EXTINT+1) /* DMA controller */ +#define NRF52_IRQ_UART0 (NRF52_IRQ_EXTINT+2) /* GPIO group 0 */ +#define NRF52_IRQ_SPI_TWI_0 (NRF52_IRQ_EXTINT+3) /* GPIO group 1 */ +#define NRF52_IRQ_SPI_TWI_1 (NRF52_IRQ_EXTINT+4) /* Pin interrupt 0 or pattern match engine slice 0 */ +#define NRF52_IRQ_NFCT (NRF52_IRQ_EXTINT+5) /* Pin interrupt 1 or pattern match engine slice 1 */ +#define NRF52_IRQ_GPIOTE (NRF52_IRQ_EXTINT+6) /* Pin interrupt 2 or pattern match engine slice 2 */ +#define NRF52_IRQ_SAADC (NRF52_IRQ_EXTINT+7) /* Pin interrupt 3 or pattern match engine slice 3 */ +#define NRF52_IRQ_TIMER0 (NRF52_IRQ_EXTINT+8) /* Micro-tick Timer */ +#define NRF52_IRQ_TIMER1 (NRF52_IRQ_EXTINT+9) /* Multi-rate timer */ +#define NRF52_IRQ_TIMER2 (NRF52_IRQ_EXTINT+10) /* Standard counter/timer CTIMER0 */ +#define NRF52_IRQ_RTC0 (NRF52_IRQ_EXTINT+11) /* Standard counter/timer CTIMER1 */ +#define NRF52_IRQ_TEMP (NRF52_IRQ_EXTINT+12) /* SCTimer/PWM0 */ +#define NRF52_IRQ_RNG (NRF52_IRQ_EXTINT+12) /* SCTimer/PWM0 */ +#define NRF52_IRQ_ECB (NRF52_IRQ_EXTINT+13) /* CTIMER3 Standard counter/timer CTIMER3 */ +#define NRF52_IRQ_CCM_AAR (NRF52_IRQ_EXTINT+14) /* Flexcomm Interface 0 (USART, SPI, I2C) */ +#define NRF52_IRQ_WDT (NRF52_IRQ_EXTINT+15) /* Flexcomm Interface 1 (USART, SPI, I2C) */ +#define NRF52_IRQ_RTC1 (NRF52_IRQ_EXTINT+16) /* Flexcomm Interface 2 (USART, SPI, I2C) */ +#define NRF52_IRQ_QDEC (NRF52_IRQ_EXTINT+17) /* Flexcomm Interface 3 (USART, SPI, I2C) */ +#define NRF52_IRQ_COMP_LPCOMP (NRF52_IRQ_EXTINT+18) /* Flexcomm Interface 4 (USART, SPI, I2C) */ +#define NRF52_IRQ_SWI0_EGU0 (NRF52_IRQ_EXTINT+19) /* Flexcomm Interface 5 (USART, SPI, I2C) */ +#define NRF52_IRQ_SWI1_EGU1 (NRF52_IRQ_EXTINT+20) /* Flexcomm Interface 6 (USART, SPI, I2C, I2S) */ +#define NRF52_IRQ_SWI2_EGU2 (NRF52_IRQ_EXTINT+21) /* Flexcomm Interface 7 (USART, SPI, I2C, I2S) */ +#define NRF52_IRQ_SWI3_EGU3 (NRF52_IRQ_EXTINT+22) /* ADC0 sequence A completion */ +#define NRF52_IRQ_SWI4_EGU4 (NRF52_IRQ_EXTINT+23) /* ADC0 sequence B completion */ +#define NRF52_IRQ_SWI5_EGU5 (NRF52_IRQ_EXTINT+24) /* ADC0 threshold compare and error */ +#define NRF52_IRQ_TIMER3 (NRF52_IRQ_EXTINT+25) /* Digital microphone and audio subsystem */ +#define NRF52_IRQ_TIMER4 (NRF52_IRQ_EXTINT+26) /* Hardware Voice Activity Detection */ +#define NRF52_IRQ_PWM0 (NRF52_IRQ_EXTINT+27) /* USB0 Activity Interrupt */ +#define NRF52_IRQ_PDM (NRF52_IRQ_EXTINT+28) /* USB0 host and device */ + /* 29-30 Reserved */ +#define NRF52_IRQ_MWU (NRF52_IRQ_EXTINT+31) /* Pin interrupt 4 or pattern match engine slice 4 */ +#define NRF52_IRQ_PWM1 (NRF52_IRQ_EXTINT+32) /* Pin interrupt 5 or pattern match engine slice 5 */ +#define NRF52_IRQ_PWM2 (NRF52_IRQ_EXTINT+33) /* Pin interrupt 6 or pattern match engine slice 6 */ +#define NRF52_IRQ_SPI2 (NRF52_IRQ_EXTINT+34) /* Pin interrupt 7 or pattern match engine slice 7 */ +#define NRF52_IRQ_RTC2 (NRF52_IRQ_EXTINT+35) /* Standard counter/timer CTIMER2 */ +#define NRF52_IRQ_I2S (NRF52_IRQ_EXTINT+36) /* Standard counter/timer CTIMER4 */ +#define NRF52_IRQ_FPU (NRF52_IRQ_EXTINT+37) /* Repetitive Interrupt Timer */ + +#define NRF52_IRQ_NEXTINT (38) +#define NRF52_IRQ_NIRQS (NRF52_IRQ_EXTINT+NRF52_IRQ_NEXTINT) + +/* Total number of IRQ numbers */ + +#define NR_VECTORS NRF52_IRQ_NIRQS +#define NR_IRQS NRF52_IRQ_NIRQS + +#endif /* __ARCH_ARM_INCLUDE_NRF52_NRF52_IRQ_H */ diff --git a/arch/arm/src/nrf52/Kconfig b/arch/arm/src/nrf52/Kconfig new file mode 100644 index 00000000000..2aef7c19c1a --- /dev/null +++ b/arch/arm/src/nrf52/Kconfig @@ -0,0 +1,74 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "NRF52 Configuration Options" + +choice + prompt "NRF52 Chip Selection" + default ARCH_CHIP_NRF52832 + depends on ARCH_CHIP_NRF52 + +config ARCH_CHIP_NRF52832 + bool "NRF52832" + select ARCH_FAMILY_NRF52 + select ARCH_FAMILY_NRF52832 + #select NRF52_HAVE_I2C_MASTER + #select NRF52_HAVE_UART + +endchoice # NRF52 Chip Selection + +# NRF52 Families + +config ARCH_FAMILY_NRF52 + bool + default n + +config ARCH_FAMILY_NRF52832 + bool + default n + +# Peripheral support + +# Peripheral Selection + +config NRF52_HAVE_I2C_MASTER + bool + default n + +config NRF52_HAVE_SPI_MASTER + bool + default n + +config NRF52_HAVE_UART + bool + default n + +menu "NRF52 Peripheral Selection" + +config NRF52_I2C0_MASTER + bool "I2C0 Master" + default n + select NRF52_HAVE_I2C_MASTER + +config NRF52_I2C1_MASTER + bool "I2C1 Master" + default n + select NRF52_HAVE_I2C_MASTER + +config NRF52_UART0 + bool "UART0" + default n + select UART0_SERIALDRIVER + select NRF52_HAVE_UART + +endmenu # NRF52 Peripheral Selection + +menu "GPIO Interrupt Configuration" + +config NRF52_GPIOIRQ + bool "Support GPIO Interrupts" + default n + +endmenu # GPIO Interrupt Configuration diff --git a/arch/arm/src/nrf52/Make.defs b/arch/arm/src/nrf52/Make.defs new file mode 100644 index 00000000000..29e517cca0b --- /dev/null +++ b/arch/arm/src/nrf52/Make.defs @@ -0,0 +1,102 @@ +############################################################################ +# arch/arm/src/nrf52/Make.defs +# +# Copyright (C) 2018 Gregory Nutt. All rights reserved. +# Author: Janne Rosberg +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +HEAD_ASRC = + +CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S +CMN_ASRCS += up_testset.S vfork.S + +CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c +CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c +CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c +CMN_CSRCS += up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c +CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c +CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_stackframe.c +CMN_CSRCS += up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c +CMN_CSRCS += up_svcall.c up_vfork.c + +ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) +CMN_ASRCS += up_lazyexception.S +else +CMN_ASRCS += up_exception.S +endif +CMN_CSRCS += up_vectors.c + +ifeq ($(CONFIG_ARCH_RAMVECTORS),y) +CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c +endif + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c +ifneq ($(CONFIG_DISABLE_SIGNALS),y) +CMN_CSRCS += up_signal_dispatch.c +CMN_UASRCS += up_signal_handler.S +endif +endif + +ifeq ($(CONFIG_STACK_COLORATION),y) +CMN_CSRCS += up_checkstack.c +endif + +ifeq ($(CONFIG_ARCH_FPU),y) +CMN_ASRCS += up_fpu.S +ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y) +CMN_CSRCS += up_copyarmstate.c +else ifeq ($(CONFIG_ARMV7M_LAZYFPU),y) +CMN_CSRCS += up_copyarmstate.c +endif +endif + +CHIP_ASRCS = +CHIP_CSRCS = nrf52_start.c nrf52_clockconfig.c nrf52_irq.c nrf52_clrpend.c +CHIP_CSRCS += nrf52_allocateheap.c nrf52_lowputc.c nrf52_gpio.c + +ifneq ($(CONFIG_SCHED_TICKLESS),y) +CHIP_CSRCS += nrf52_timerisr.c +else +CHIP_CSRCS += nrf52_tickless.c +endif + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += nrf52_userspace.c nrf52_mpuinit.c +endif + +ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CHIP_CSRCS += nrf52_idle.c +endif + +ifeq ($(CONFIG_NRF52_HAVE_UART),y) +CHIP_CSRCS += nrf52_serial.c +endif diff --git a/arch/arm/src/nrf52/chip.h b/arch/arm/src/nrf52/chip.h new file mode 100644 index 00000000000..c790efa77a0 --- /dev/null +++ b/arch/arm/src/nrf52/chip.h @@ -0,0 +1,77 @@ +/************************************************************************************ + * arch/arm/src/nrf52/chip.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF53_CHIP_H +#define __ARCH_ARM_SRC_NRF53_CHIP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/* Include the memory map and the chip definitions file. Other chip hardware files + * should then include this file for the proper setup. + */ + +#include +#include +#include "chip/nrf52_memorymap.h" + +/* If the common ARMv7-M vector handling logic is used, then it expects the + * following definition in this file that provides the number of supported external + * interrupts which, for this architecture, is provided in the arch/nrf52/chip.h + * header file. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS NRF52_IRQ_NEXTINT + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_NRF53_CHIP_H */ diff --git a/arch/arm/src/nrf52/chip/nrf52832_memorymap.h b/arch/arm/src/nrf52/chip/nrf52832_memorymap.h new file mode 100644 index 00000000000..0e433eb7af0 --- /dev/null +++ b/arch/arm/src/nrf52/chip/nrf52832_memorymap.h @@ -0,0 +1,126 @@ +/**************************************************************************** + * arch/arm/src/nrf52/chip/nrf52832_memorymap.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_CHIP_NRF52832_MEMORYMAP_H +#define __ARCH_ARM_SRC_NRF52_CHIP_NRF52832_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Memory Map */ + +#define NRF52_FLASH_BASE 0x00000000 /* Flash memory (512 KB) */ +#define NRF52_SRAM_BASE 0x20000000 /* SRAM bank (64 KB) */ +#define NRF52_FICR_BASE 0x10000000 /* FICR */ +#define NRF52_UICR_BASE 0x10001000 /* UICR */ +#define NRF52_APB0_BASE 0x40000000 /* APB */ + +#define NRF52_CORTEXM4_BASE 0xe0000000 /* Cortex-M4 Private Peripheral Bus */ + +/* APB Peripherals */ + +#define NRF52_CLOCK_BASE 0x40000000 +#define NRF52_POWER_BASE 0x40000000 +#define NRF52_BPROT_BASE 0x40000000 +#define NRF52_RADIO_BASE 0x40001000 +#define NRF52_UARTE0_BASE 0x40002000 +#define NRF52_UART0_BASE 0x40002000 +#define NRF52_SPIM0_BASE 0x40003000 +#define NRF52_SPIS0_BASE 0x40003000 +#define NRF52_TWIM0_BASE 0x40003000 +#define NRF52_TWI0_BASE 0x40003000 +#define NRF52_SPI0_BASE 0x40003000 +#define NRF52_TWIS0_BASE 0x40003000 +#define NRF52_SPIM1_BASE 0x40004000 +#define NRF52_TWI1_BASE 0x40004000 +#define NRF52_SPIS1_BASE 0x40004000 +#define NRF52_TWIS1_BASE 0x40004000 +#define NRF52_TWIM1_BASE 0x40004000 +#define NRF52_SPI1_BASE 0x40004000 +#define NRF52_NFCT_BASE 0x40005000 +#define NRF52_GPIOTE_BASE 0x40006000 +#define NRF52_SAADC_BASE 0x40007000 +#define NRF52_TIMER0_BASE 0x40008000 +#define NRF52_TIMER1_BASE 0x40009000 +#define NRF52_TIMER2_BASE 0x4000A000 +#define NRF52_RTC0_BASE 0x4000B000 +#define NRF52_TEMP_BASE 0x4000C000 +#define NRF52_RNG_BASE 0x4000D000 +#define NRF52_ECB_BASE 0x4000E000 +#define NRF52_CCM_BASE 0x4000F000 +#define NRF52_AAR_BASE 0x4000F000 +#define NRF52_WDT_BASE 0x40010000 +#define NRF52_RTC1_BASE 0x40011000 +#define NRF52_QDEC_BASE 0x40012000 +#define NRF52_LPCOMP_BASE 0x40013000 +#define NRF52_COMP_BASE 0x40013000 +#define NRF52_SWI0_BASE 0x40014000 +#define NRF52_EGU0_BASE 0x40014000 +#define NRF52_EGU1_BASE 0x40015000 +#define NRF52_SWI1_BASE 0x40015000 +#define NRF52_SWI2_BASE 0x40016000 +#define NRF52_EGU2_BASE 0x40016000 +#define NRF52_SWI3_BASE 0x40017000 +#define NRF52_EGU3_BASE 0x40017000 +#define NRF52_EGU4_BASE 0x40018000 +#define NRF52_SWI4_BASE 0x40018000 +#define NRF52_SWI5_BASE 0x40019000 +#define NRF52_EGU5_BASE 0x40019000 +#define NRF52_TIMER3_BASE 0x4001A000 +#define NRF52_TIMER4_BASE 0x4001B000 +#define NRF52_PWM0_BASE 0x4001C000 +#define NRF52_PDM_BASE 0x4001D000 +#define NRF52_NVMC_BASE 0x4001E000 +#define NRF52_PPI_BASE 0x4001F000 +#define NRF52_MWU_BASE 0x40020000 +#define NRF52_PWM1_BASE 0x40021000 +#define NRF52_PWM2_BASE 0x40022000 +#define NRF52_SPI2_BASE 0x40023000 +#define NRF52_SPIS2_BASE 0x40023000 +#define NRF52_SPIM2_BASE 0x40023000 +#define NRF52_RTC2_BASE 0x40024000 +#define NRF52_I2S_BASE 0x40025000 +#define NRF52_FPU_BASE 0x40026000 + +#define NRF52_GPIO_P0_BASE 0x50000000 + +#endif /* __ARCH_ARM_SRC_NRF52_CHIP_NRF52832_MEMORYMAP_H */ diff --git a/arch/arm/src/nrf52/chip/nrf52_clock.h b/arch/arm/src/nrf52/chip/nrf52_clock.h new file mode 100644 index 00000000000..41ba551a527 --- /dev/null +++ b/arch/arm/src/nrf52/chip/nrf52_clock.h @@ -0,0 +1,100 @@ +/************************************************************************************************ + * arch/arm/src/nrf52/chip/nrf52_clock.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_CHIP_NRF52_CLOCK_H +#define __ARCH_ARM_SRC_NRF52_CHIP_NRF52_CLOCK_H + +/************************************************************************************************ + * Included Files + ************************************************************************************************/ + +#include +#include "chip/nrf52_memorymap.h" + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ + +/* Register offsets *****************************************************************************/ + +#define NRF52_CLOCK_TASKS_HFCLKSTART_OFFSET 0x0000 /* Start HFCLK crystal oscillator */ +#define NRF52_CLOCK_TASKS_HFCLKSTOP_OFFSET 0x0004 /* Stop HFCLK crystal oscillator */ +#define NRF52_CLOCK_TASKS_LFCLKSTART_OFFSET 0x0008 /* Start LFCLK source */ +#define NRF52_CLOCK_TASKS_LFCLKSTOP_OFFSET 0x000c /* Stop LFCLK source */ +#define NRF52_CLOCK_TASKS_CAL_OFFSET 0x0010 /* Start calibration of LFRC oscillator */ +#define NRF52_CLOCK_TASKS_CTSTART_OFFSET 0x0014 /* Start calibration timer */ +#define NRF52_CLOCK_TASKS_CTSTOP_OFFSET 0x0018 /* Stop calibration timer */ +#define NRF52_CLOCK_EVENTS_HFCLKSTARTED_OFFSET 0x0100 /* HFCLK oscillator started */ +#define NRF52_CLOCK_EVENTS_LFCLKSTARTED_OFFSET 0x0104 /* LFCLK started */ +#define NRF52_CLOCK_EVENTS_DONE_OFFSET 0x010c /* Calibration of LFCLK RC oscillator complete event */ +#define NRF52_CLOCK_EVENTS_CTTO_OFFSET 0x0110 /* Calibration timer timeout */ +#define NRF52_CLOCK_INTENSET_OFFSET 0x0304 /* Enable interrupt */ +#define NRF52_CLOCK_INTENCLR_OFFSET 0x0308 /* Disable interrupt */ +#define NRF52_CLOCK_HFCLKRUN_OFFSET 0x0408 /* Status indicating that HFCLKSTART task has been triggered */ +#define NRF52_CLOCK_HFCLKSTAT_OFFSET 0x040c /* HFCLK status */ +#define NRF52_CLOCK_LFCLKRUN_OFFSET 0x0414 /* Status indicating that LFCLKSTART task has been triggered */ +#define NRF52_CLOCK_LFCLKSTAT_OFFSET 0x0418 /* LFCLK status */ +#define NRF52_CLOCK_LFCLKSRCCOPY_OFFSET 0x041c /* Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ +#define NRF52_CLOCK_LFCLKSRC_OFFSET 0x0518 /* Clock source for the LFCLK */ +#define NRF52_CLOCK_CTIV_OFFSET 0x0538 /* Calibration timer interval */ +#define NRF52_CLOCK_TRACECONFIG_OFFSET 0x055c /* Clocking options for the Trace Port debug interface */ + +/* Register Addresses ***************************************************************************/ + +#define NRF52_CLOCK_TASKS_HFCLKSTART (NRF52_CLOCK_BASE + NRF52_CLOCK_TASKS_HFCLKSTART_OFFSET) +#define NRF52_CLOCK_TASKS_HFCLKSTOP (NRF52_CLOCK_BASE + NRF52_CLOCK_TASKS_HFCLKSTOP_OFFSET) +#define NRF52_CLOCK_TASKS_LFCLKSTART (NRF52_CLOCK_BASE + NRF52_CLOCK_TASKS_LFCLKSTART_OFFSET) +#define NRF52_CLOCK_TASKS_LFCLKSTOP (NRF52_CLOCK_BASE + NRF52_CLOCK_TASKS_LFCLKSTOP_OFFSET) +#define NRF52_CLOCK_TASKS_CAL (NRF52_CLOCK_BASE + NRF52_CLOCK_TASKS_CAL_OFFSET) +#define NRF52_CLOCK_TASKS_CTSTART (NRF52_CLOCK_BASE + NRF52_CLOCK_TASKS_CTSTART_OFFSET) +#define NRF52_CLOCK_TASKS_CTSTOP (NRF52_CLOCK_BASE + NRF52_CLOCK_TASKS_CTSTOP_OFFSET) +#define NRF52_CLOCK_EVENTS_HFCLKSTARTED (NRF52_CLOCK_BASE + NRF52_CLOCK_EVENTS_HFCLKSTARTED_OFFSET) +#define NRF52_CLOCK_EVENTS_LFCLKSTARTED (NRF52_CLOCK_BASE + NRF52_CLOCK_EVENTS_LFCLKSTARTED_OFFSET) +#define NRF52_CLOCK_EVENTS_DONE (NRF52_CLOCK_BASE + NRF52_CLOCK_EVENTS_DONE_OFFSET) +#define NRF52_CLOCK_EVENTS_CTTO (NRF52_CLOCK_BASE + NRF52_CLOCK_EVENTS_CTTO_OFFSET) +#define NRF52_CLOCK_INTENSET (NRF52_CLOCK_BASE + NRF52_CLOCK_INTENSET_OFFSET) +#define NRF52_CLOCK_INTENCLR (NRF52_CLOCK_BASE + NRF52_CLOCK_INTENCLR_OFFSET) +#define NRF52_CLOCK_HFCLKRUN (NRF52_CLOCK_BASE + NRF52_CLOCK_HFCLKRUN_OFFSET) +#define NRF52_CLOCK_HFCLKSTAT (NRF52_CLOCK_BASE + NRF52_CLOCK_HFCLKSTAT_OFFSET) +#define NRF52_CLOCK_LFCLKRUN (NRF52_CLOCK_BASE + NRF52_CLOCK_LFCLKRUN_OFFSET) +#define NRF52_CLOCK_LFCLKSTAT (NRF52_CLOCK_BASE + NRF52_CLOCK_LFCLKSTAT_OFFSET) +#define NRF52_CLOCK_LFCLKSRCCOPY (NRF52_CLOCK_BASE + NRF52_CLOCK_LFCLKSRCCOPY_OFFSET) +#define NRF52_CLOCK_LFCLKSRC (NRF52_CLOCK_BASE + NRF52_CLOCK_LFCLKSRC_OFFSET ) +#define NRF52_CLOCK_CTIV (NRF52_CLOCK_BASE + NRF52_CLOCK_CTIV_OFFSET) +#define NRF52_CLOCK_TRACECONFIG (NRF52_CLOCK_BASE + NRF52_CLOCK_TRACECONFIG_OFFSET) + +/* Register Bitfield Definitions ****************************************************************/ + +#endif /* __ARCH_ARM_SRC_NRF52_CHIP_NRF52_LCD_H */ diff --git a/arch/arm/src/nrf52/chip/nrf52_gpio.h b/arch/arm/src/nrf52/chip/nrf52_gpio.h new file mode 100644 index 00000000000..1caf627e5cc --- /dev/null +++ b/arch/arm/src/nrf52/chip/nrf52_gpio.h @@ -0,0 +1,80 @@ +/************************************************************************************ + * arch/arm/src/nrf52/chip/nrf52_gpio.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_CHIP_NRF52_GPIO_H +#define __ARCH_ARM_SRC_NRF52_CHIP_NRF52_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include +#include "chip/nrf52_memorymap.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#define NRF52_GPIO_PORT0 0 +#define NRF52_GPIO_NPORTS 1 + +/* Register offsets *****************************************************************/ + +#define NRF52_GPIO_OUT_OFFSET 0x0504 /* Write GPIO port */ +#define NRF52_GPIO_OUTSET_OFFSET 0x0508 /* Set individual bits in GPIO port */ +#define NRF52_GPIO_OUTCLR_OFFSET 0x050c /* Clear individual bits in GPIO port */ +#define NRF52_GPIO_IN_OFFSET 0x0510 /* Read GPIO port */ +#define NRF52_GPIO_DIR_OFFSET 0x0514 /* Direction of GPIO pins */ +#define NRF52_GPIO_DIRSET_OFFSET 0x0518 /* DIR set register */ +#define NRF52_GPIO_DIRCLR_OFFSET 0x051c /* DIR clear register */ +#define NRF52_GPIO_LATCH_OFFSET 0x0520 /* Latch register */ +#define NRF52_GPIO_DETECTMODE_OFFSET 0x0524 /* Select between default DETECT signal behaviour and LDETECT mode */ + +#define NRF52_GPIO_PIN_CNF_OFFSET(n) (0x0700 + (n << 2)) + +/* Register addresses ***************************************************************/ + +#define NRF52_GPIO0_OUT (NRF52_GPIO_P0_BASE + NRF52_GPIO_OUT_OFFSET) +#define NRF52_GPIO0_OUTSET (NRF52_GPIO_P0_BASE + NRF52_GPIO_OUTSET_OFFSET) +#define NRF52_GPIO0_OUTCLR (NRF52_GPIO_P0_BASE + NRF52_GPIO_OUTCLR_OFFSET) +#define NRF52_GPIO0_IN (NRF52_GPIO_P0_BASE + NRF52_GPIO_IN_OFFSET) +#define NRF52_GPIO0_DIR (NRF52_GPIO_P0_BASE + NRF52_GPIO_DIR_OFFSET) +#define NRF52_GPIO0_DIRSET (NRF52_GPIO_P0_BASE + NRF52_GPIO_DIRSET_OFFSET) +#define NRF52_GPIO0_DIRCLR (NRF52_GPIO_P0_BASE + NRF52_GPIO_DIRCLR_OFFSET) + +/* Register bit definitions *********************************************************/ + +#endif /* __ARCH_ARM_SRC_NRF52_CHIP_NRF52_GPIO_H */ diff --git a/arch/arm/src/nrf52/chip/nrf52_memorymap.h b/arch/arm/src/nrf52/chip/nrf52_memorymap.h new file mode 100644 index 00000000000..9974507a367 --- /dev/null +++ b/arch/arm/src/nrf52/chip/nrf52_memorymap.h @@ -0,0 +1,52 @@ +/************************************************************************************ + * arch/arm/src/nrf52/chip/nrf52_memorymap.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_CHIP_NRF52_MEMORYMAP_H +#define __ARCH_ARM_SRC_NRF52_CHIP_NRF52_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_FAMILY_NRF52832) +# include "chip/nrf52832_memorymap.h" +#else +# error "Unsupported NRF52 family" +#endif + +#endif /* __ARCH_ARM_SRC_NRF52_CHIP_NRF52_MEMORYMAP_H */ + diff --git a/arch/arm/src/nrf52/chip/nrf52_uarte.h b/arch/arm/src/nrf52/chip/nrf52_uarte.h new file mode 100644 index 00000000000..b87de7d5a3c --- /dev/null +++ b/arch/arm/src/nrf52/chip/nrf52_uarte.h @@ -0,0 +1,188 @@ +/***************************************************************************************************** + * arch/arm/src/nrf52/chip/nrf52_uarte.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_CHIP_NRF52_UARTE_H +#define __ARCH_ARM_SRC_NRF52_CHIP_NRF52_UARTE_H + +/***************************************************************************************************** + * Included Files + *****************************************************************************************************/ + +#include +#include "chip/nrf52_memorymap.h" + +/***************************************************************************************************** + * Pre-processor Definitions + *****************************************************************************************************/ + +/* UARTE Register Offsets ****************************************************************************/ + +/* Registers for the UARTE function: */ + +#define NRF52_UARTE_TASKS_STARTRX_OFFSET 0x0000 /* Start UART receiver */ +#define NRF52_UARTE_TASKS_STOPRX_OFFSET 0x0004 /* Stop UART receiver */ +#define NRF52_UARTE_TASKS_STARTTX_OFFSET 0x0008 /* Start UART transmitter */ +#define NRF52_UARTE_TASKS_STOPTX_OFFSET 0x000c /* Stop UART transmitter */ +#define NRF52_UARTE_TASKS_FLUSHRX_OFFSET 0x002c /* Flush RX FIFO into RX buffer */ +#define NRF52_UARTE_EVENTS_CTS_OFFSET 0x0100 /* CTS is activated (set low). Clear To Send. */ +#define NRF52_UARTE_EVENTS_NCTS_OFFSET 0x0104 /* CTS is deactivated (set high). Not Clear To Send. */ +#define NRF52_UARTE_EVENTS_RXDRDY_OFFSET 0x0108 /* Data received in RXD (but potentially not yet transferred to Data RAM) */ +#define NRF52_UARTE_EVENTS_ENDRX_OFFSET 0x0110 /* Receive buffer is filled up */ +#define NRF52_UARTE_EVENTS_TXDRDY_OFFSET 0x011c /* Data sent from TXD */ +#define NRF52_UARTE_EVENTS_ENDTX_OFFSET 0x0120 /* Last TX byte transmitted */ +#define NRF52_UARTE_EVENTS_ERROR_OFFSET 0x0124 /* Error detected */ +#define NRF52_UARTE_EVENTS_RXTO_OFFSET 0x0144 /* Receiver timeout */ +#define NRF52_UARTE_EVENTS_RXSTARTED_OFFSET 0x014c /* UART receiver has started */ +#define NRF52_UARTE_EVENTS_TXSTARTED_OFFSET 0x0150 /* UART transmitter has started */ +#define NRF52_UARTE_EVENTS_TXSTOPPED_OFFSET 0x0158 /* Transmitter stopped */ +#define NRF52_UARTE_SHORTS_OFFSET 0x0200 /* Shortcut register */ +#define NRF52_UARTE_INTEN_OFFSET 0x0300 /* Enable or disable interrupt */ +#define NRF52_UARTE_INTENSET_OFFSET 0x0304 /* Enable interrupt */ +#define NRF52_UARTE_INTENCLR_OFFSET 0x0308 /* Disable interrupt */ +#define NRF52_UARTE_ERRORSRC_OFFSET 0x0480 /* Error source */ +#define NRF52_UARTE_ENABLE_OFFSET 0x0500 /* Enable UART */ +#define NRF52_UARTE_PSEL_RTS_OFFSET 0x0508 /* Pin select for RTS signal */ +#define NRF52_UARTE_PSEL_TXD_OFFSET 0x050c /* Pin select for TXD signal */ +#define NRF52_UARTE_PSEL_CTS_OFFSET 0x0510 /* Pin select for CTS signal */ +#define NRF52_UARTE_PSEL_RXD_OFFSET 0x0514 /* Pin select for RXD signal */ +#define NRF52_UARTE_BAUDRATE_OFFSET 0x0524 /* Baud rate. Accuracy depends on the HFCLK source selected. */ +#define NRF52_UARTE_RXD_PTR_OFFSET 0x0534 /* Data pointer */ +#define NRF52_UARTE_RXD_MAXCNT_OFFSET 0x0538 /* Maximum number of bytes in receive buffer */ +#define NRF52_UARTE_RXD_AMOUNT_OFFSET 0x053c /* Number of bytes transferred in the last transaction */ +#define NRF52_UARTE_TXD_PTR_OFFSET 0x0544 /* Data pointer */ +#define NRF52_UARTE_TXD_MAXCNT_OFFSET 0x0548 /* Maximum number of bytes in transmit buffer */ +#define NRF52_UARTE_TXD_AMOUNT_OFFSET 0x054c /* Number of bytes transferred in the last transaction */ +#define NRF52_UARTE_CONFIG_OFFSET 0x056c /* Configuration of parity and hardware flow control */ + + +#define NRF52_UARTE_TASKS_STARTRX (NRF52_UARTE0_BASE + NRF52_UARTE_TASKS_STARTRX_OFFSET) +#define NRF52_UARTE_TASKS_STOPRX (NRF52_UARTE0_BASE + NRF52_UARTE_TASKS_STOPRX_OFFSET) +#define NRF52_UARTE_TASKS_STARTTX (NRF52_UARTE0_BASE + NRF52_UARTE_TASKS_STARTTX_OFFSET) +#define NRF52_UARTE_TASKS_STOPTX (NRF52_UARTE0_BASE + NRF52_UARTE_TASKS_STOPTX_OFFSET) +#define NRF52_UARTE_TASKS_FLUSHRX (NRF52_UARTE0_BASE + NRF52_UARTE_TASKS_FLUSHRX_OFFSET) +#define NRF52_UARTE_EVENTS_CTS (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_CTS_OFFSET) +#define NRF52_UARTE_EVENTS_NCTS (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_NCTS_OFFSET) +#define NRF52_UARTE_EVENTS_RXDRDY (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_RXDRDY_OFFSET) +#define NRF52_UARTE_EVENTS_ENDRX (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_ENDRX_OFFSET) +#define NRF52_UARTE_EVENTS_TXDRDY (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_TXDRDY_OFFSET) +#define NRF52_UARTE_EVENTS_ENDTX (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_ENDTX_OFFSET) +#define NRF52_UARTE_EVENTS_ERROR (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_ERROR_OFFSET) +#define NRF52_UARTE_EVENTS_RXTO (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_RXTO_OFFSET) +#define NRF52_UARTE_EVENTS_RXSTARTED (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_RXSTARTED_OFFSET) +#define NRF52_UARTE_EVENTS_TXSTARTED (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_TXSTARTED_OFFSET) +#define NRF52_UARTE_EVENTS_TXSTOPPED (NRF52_UARTE0_BASE + NRF52_UARTE_EVENTS_TXSTOPPED_OFFSET) +#define NRF52_UARTE_SHORTS (NRF52_UARTE0_BASE + NRF52_UARTE_SHORTS_OFFSET) +#define NRF52_UARTE_INTEN (NRF52_UARTE0_BASE + NRF52_UARTE_INTEN_OFFSET) +#define NRF52_UARTE_INTENSET (NRF52_UARTE0_BASE + NRF52_UARTE_INTENSET_OFFSET) +#define NRF52_UARTE_INTENCLR (NRF52_UARTE0_BASE + NRF52_UARTE_INTENCLR_OFFSET) +#define NRF52_UARTE_ERRORSRC (NRF52_UARTE0_BASE + NRF52_UARTE_ERRORSRC_OFFSET) +#define NRF52_UARTE_ENABLE (NRF52_UARTE0_BASE + NRF52_UARTE_ENABLE_OFFSET) +#define NRF52_UARTE_PSEL_RTS (NRF52_UARTE0_BASE + NRF52_UARTE_PSEL_RTS_OFFSET) +#define NRF52_UARTE_PSEL_TXD (NRF52_UARTE0_BASE + NRF52_UARTE_PSEL_TXD_OFFSET) +#define NRF52_UARTE_PSEL_CTS (NRF52_UARTE0_BASE + NRF52_UARTE_PSEL_CTS_OFFSET) +#define NRF52_UARTE_PSEL_RXD (NRF52_UARTE0_BASE + NRF52_UARTE_PSEL_RXD_OFFSET) +#define NRF52_UARTE_BAUDRATE (NRF52_UARTE0_BASE + NRF52_UARTE_BAUDRATE_OFFSET) +#define NRF52_UARTE_RXD_PTR (NRF52_UARTE0_BASE + NRF52_UARTE_RXD_PTR_OFFSET) +#define NRF52_UARTE_RXD_MAXCNT (NRF52_UARTE0_BASE + NRF52_UARTE_RXD_MAXCNT_OFFSET) +#define NRF52_UARTE_RXD_AMOUNT (NRF52_UARTE0_BASE + NRF52_UARTE_RXD_AMOUNT_OFFSET) +#define NRF52_UARTE_TXD_PTR (NRF52_UARTE0_BASE + NRF52_UARTE_TXD_PTR_OFFSET) +#define NRF52_UARTE_TXD_MAXCNT (NRF52_UARTE0_BASE + NRF52_UARTE_TXD_MAXCNT_OFFSET) +#define NRF52_UARTE_TXD_AMOUNT (NRF52_UARTE0_BASE + NRF52_UARTE_TXD_AMOUNT_OFFSET) +#define NRF52_UARTE_CONFIG (NRF52_UARTE0_BASE + NRF52_UARTE_CONFIG_OFFSET) + +#define NRF52_UART_TASKS_STARTRX_OFFSET 0x0000 /* Start UART receiver */ +#define NRF52_UART_TASKS_STOPRX_OFFSET 0x0004 /* Stop UART receiver */ +#define NRF52_UART_TASKS_STARTTX_OFFSET 0x0008 /* Start UART transmitter */ +#define NRF52_UART_TASKS_STOPTX_OFFSET 0x000c /* Stop UART transmitter */ +#define NRF52_UART_TASKS_SUSPEND_OFFSET 0x001c /* Suspend UART */ +#define NRF52_UART_EVENTS_CTS_OFFSET 0x0100 /* CTS is activated (set low). Clear To Send. */ +#define NRF52_UART_EVENTS_NCTS_OFFSET 0x0104 /* CTS is deactivated (set high). Not Clear To Send. */ +#define NRF52_UART_EVENTS_RXDRDY_OFFSET 0x0108 /* Data received in RXD */ +#define NRF52_UART_EVENTS_TXDRDY_OFFSET 0x011c /* Data sent from TXD */ +#define NRF52_UART_EVENTS_ERROR_OFFSET 0x0124 /* Error detected */ +#define NRF52_UART_EVENTS_RXTO_OFFSET 0x0144 /* Receiver timeout */ +#define NRF52_UART_SHORTS_OFFSET 0x0200 /* Shortcut register */ +#define NRF52_UART_INTENSET_OFFSET 0x0304 /* Enable interrupt */ +#define NRF52_UART_INTENCLR_OFFSET 0x0308 /* Disable interrupt */ +#define NRF52_UART_ERRORSRC_OFFSET 0x0480 /* Error source */ +#define NRF52_UART_ENABLE_OFFSET 0x0500 /* Enable UART */ +#define NRF52_UART_PSELRTS_OFFSET 0x0508 /* Pin select for RTS */ +#define NRF52_UART_PSELTXD_OFFSET 0x050c /* Pin select for TXD */ +#define NRF52_UART_PSELCTS_OFFSET 0x0510 /* Pin select for CTS */ +#define NRF52_UART_PSELRXD_OFFSET 0x0514 /* Pin select for RXD */ +#define NRF52_UART_RXD_OFFSET 0x0518 /* RXD register */ +#define NRF52_UART_TXD_OFFSET 0x051c /* TXD register */ +#define NRF52_UART_BAUDRATE_OFFSET 0x0524 /* Baud rate */ +#define NRF52_UART_CONFIG_OFFSET 0x056c /* Configuration of parity and hardware flow control */ + +#define NRF52_UART_TASKS_STARTRX (NRF52_UART0_BASE + NRF52_UART_TASKS_STARTRX_OFFSET) +#define NRF52_UART_TASKS_STOPRX (NRF52_UART0_BASE + NRF52_UART_TASKS_STOPRX_OFFSET) +#define NRF52_UART_TASKS_STARTTX (NRF52_UART0_BASE + NRF52_UART_TASKS_STARTTX_OFFSET) +#define NRF52_UART_TASKS_STOPTX (NRF52_UART0_BASE + NRF52_UART_TASKS_STOPTX_OFFSET) +#define NRF52_UART_TASKS_SUSPEND (NRF52_UART0_BASE + NRF52_UART_TASKS_SUSPEND_OFFSET) +#define NRF52_UART_EVENTS_CTS (NRF52_UART0_BASE + NRF52_UART_EVENTS_CTS_OFFSET) +#define NRF52_UART_EVENTS_NCTS (NRF52_UART0_BASE + NRF52_UART_EVENTS_NCTS_OFFSET) +#define NRF52_UART_EVENTS_RXDRDY (NRF52_UART0_BASE + NRF52_UART_EVENTS_RXDRDY_OFFSET) +#define NRF52_UART_EVENTS_TXDRDY (NRF52_UART0_BASE + NRF52_UART_EVENTS_TXDRDY_OFFSET) +#define NRF52_UART_EVENTS_ERROR (NRF52_UART0_BASE + NRF52_UART_EVENTS_ERROR_OFFSET) +#define NRF52_UART_EVENTS_RXTO (NRF52_UART0_BASE + NRF52_UART_EVENTS_RXTO_OFFSET) +#define NRF52_UART_SHORTS (NRF52_UART0_BASE + NRF52_UART_SHORTS_OFFSET) +#define NRF52_UART_INTENSET (NRF52_UART0_BASE + NRF52_UART_INTENSET_OFFSET) +#define NRF52_UART_INTENCLR (NRF52_UART0_BASE + NRF52_UART_INTENCLR_OFFSET) +#define NRF52_UART_ERRORSRC (NRF52_UART0_BASE + NRF52_UART_ERRORSRC_OFFSET) +#define NRF52_UART_ENABLE (NRF52_UART0_BASE + NRF52_UART_ENABLE_OFFSET) +#define NRF52_UART_PSELRTS (NRF52_UART0_BASE + NRF52_UART_PSELRTS_OFFSET) +#define NRF52_UART_PSELTXD (NRF52_UART0_BASE + NRF52_UART_PSELTXD_OFFSET) +#define NRF52_UART_PSELCTS (NRF52_UART0_BASE + NRF52_UART_PSELCTS_OFFSET) +#define NRF52_UART_PSELRXD (NRF52_UART0_BASE + NRF52_UART_PSELRXD_OFFSET) +#define NRF52_UART_RXD (NRF52_UART0_BASE + NRF52_UART_RXD_OFFSET) +#define NRF52_UART_TXD (NRF52_UART0_BASE + NRF52_UART_TXD_OFFSET) +#define NRF52_UART_BAUDRATE (NRF52_UART0_BASE + NRF52_UART_BAUDRATE_OFFSET) +#define NRF52_UART_CONFIG (NRF52_UART0_BASE + NRF52_UART_CONFIG_OFFSET) + +/* UARTE Register Addresses **************************************************************************/ + +/* UART Register Bitfield Definitions ****************************************************************/ + +/* ENABLE Register */ + +#define NRF52_UART_ENABLE_DISABLE (0) +#define NRF52_UART_ENABLE_ENABLE (4) + +/* INTENSET Register */ + +#define NRF52_UART_INTENSET_RXDRDY (1 << 2) + +#endif /* __ARCH_ARM_SRC_NRF52_CHIP_NRF52_UARTE_H */ diff --git a/arch/arm/src/nrf52/nrf52_allocateheap.c b/arch/arm/src/nrf52/nrf52_allocateheap.c new file mode 100644 index 00000000000..4ec0d0287fb --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_allocateheap.c @@ -0,0 +1,218 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_allocateheap.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "chip/nrf52_memorymap.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ +/* Terminology. In the flat build (CONFIG_BUILD_FLAT=y), there is only a + * single heap access with the standard allocations (malloc/free). This + * heap is referred to as the user heap. In the protected build + * (CONFIG_BUILD_PROTECTED=y) where an MPU is used to protect a region of + * otherwise flat memory, there will be two allocators: One that allocates + * protected (kernel) memory and one that allocates unprotected (user) + * memory. These are referred to as the kernel and user heaps, + * respectively. + * + * The ARMv7 has no MPU but does have an MMU. With this MMU, it can support + * the kernel build (CONFIG_BUILD_KERNEL=y). In this configuration, there + * is one kernel heap but multiple user heaps: One per task group. However, + * in this case, we need only be concerned about initializing the single + * kernel heap here. + */ + +/* .bss and .data is always positioned in internal SRAM. The remaining SRAM + * after the static .bss, .data, and IDLE stack allocations are always added + * to the heap. + */ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* _sbss is the start of the BSS region (see the linker script) _ebss is the + * end of the BSS region (see the linker script). The idle task stack starts + * at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE + * thread is the thread that the system boots on and, eventually, becomes the + * idle, do nothing task that runs only when there is nothing else to run. + * The heap continues from there until the configured end of memory. + * g_idle_topstack is the beginning of this heap region (not necessarily + * aligned). + */ + +const uint32_t g_idle_topstack = (uint32_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap/up_allocate_kheap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * - For the normal "flat" build, this function returns the size of the + * single heap. + * - For the protected build (CONFIG_BUILD_PROTECTED=y) with both kernel- + * and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function + * provides the size of the unprotected, user-space heap. + * - For the kernel build (CONFIG_BUILD_KERNEL=y), this function provides + * the size of the protected, kernel-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated by an analogous up_allocate_kheap(). A custom version of this + * file is needed if memory protection of the kernel heap is required. + * + * The following memory map is assumed for the flat build: + * + * .data region. Size determined at link time. + * .bss region Size determined at link time. + * IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Heap. Extends to the end of SRAM. + * + * The following memory map is assumed for the kernel build: + * + * Kernel .data region. Size determined at link time. + * Kernel .bss region Size determined at link time. + * Kernel IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE. + * Padding for alignment + * User .data region. Size determined at link time. + * User .bss region Size determined at link time. + * Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE. + * User heap. Extends to the end of SRAM. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_KERNEL +void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) +#else +void up_allocate_heap(FAR void **heap_start, size_t *heap_size) +#endif +{ +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + size_t usize = CONFIG_RAM_END - ubase; + + DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END); + + /* Return the user-space heap settings */ + + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (FAR void *)ubase; + *heap_size = usize; +#else + + /* Return the heap settings */ + + board_autoled_on(LED_HEAPALLOCATE); + *heap_start = (FAR void *)g_idle_topstack; + *heap_size = CONFIG_RAM_END - g_idle_topstack; +#endif +} + +/**************************************************************************** + * Name: up_allocate_kheap + * + * Description: + * For the kernel build (CONFIG_BUILD_PROTECTED/KERNEL=y) with both kernel- + * and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates + * the kernel-space heap. A custom version of this function is needed if + * memory protection of the kernel heap is required. + * + ****************************************************************************/ + +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) +void up_allocate_kheap(FAR void **heap_start, size_t *heap_size) +{ + /* Get the unaligned size and position of the user-space heap. + * This heap begins after the user-space .bss section at an offset + * of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment). + */ + + uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE; + DEBUGASSERT(ubase < (uintptr_t)CONFIG_RAM_END); + + /* Return the kernel heap settings (i.e., the part of the heap region + * that was not dedicated to the user heap). + */ + + *heap_start = (FAR void *)USERSPACE->us_bssend; + *heap_size = ubase - (uintptr_t)USERSPACE->us_bssend; +} +#endif + +/**************************************************************************** + * Name: up_addregion + * + * Description: + * Memory may be added in non-contiguous chunks. Additional chunks are + * added by calling this function. + * + ****************************************************************************/ + +#if CONFIG_MM_REGIONS > 1 +void up_addregion(void) +{ +} +#endif /* CONFIG_MM_REGIONS > 1 */ diff --git a/arch/arm/src/nrf52/nrf52_clockconfig.c b/arch/arm/src/nrf52/nrf52_clockconfig.c new file mode 100644 index 00000000000..e7aa6144a05 --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_clockconfig.c @@ -0,0 +1,70 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_clockconfig.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "nrf52_clockconfig.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_clockconfig + * + * Description: + * Called to initialize the NRF52xxx. This does whatever setup is needed + * to put the MCU in a usable state. This includes the initialization of + * clocking using the settings in board.h. This function also performs + * other low-level chip as necessary. + * + *****************************************************************************/ + +void nrf52_clockconfig() +{ +} diff --git a/arch/arm/src/nrf52/nrf52_clockconfig.h b/arch/arm/src/nrf52/nrf52_clockconfig.h new file mode 100644 index 00000000000..7fb21c52f21 --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_clockconfig.h @@ -0,0 +1,100 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_clockconfig.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_NRF52_CLOCKCONFIG_H +#define __ARCH_ARM_SRC_NRF52_NRF52_CLOCKCONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Frequencies of internal clocks */ + +#define NRF52_SYSTEM_CLOCK 64000000 /* Default System clock value */ +#define NRF52_RTC_CLOCK 32768 /* RTC oscillator 32 kHz output (32k_clk )*/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_clockconfig + * + * Description: + * Called to initialize the NRF52xxx. This does whatever setup is needed + * to put the MCU in a usable state. This includes the initialization of + * clocking using the settings in board.h. This function also performs + * other low-level chip as necessary. + * + *****************************************************************************/ + +void nrf52_clockconfig(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_NRF52_NRF52_CLOCKCONFIG_H */ diff --git a/arch/arm/src/nrf52/nrf52_clrpend.c b/arch/arm/src/nrf52/nrf52_clrpend.c new file mode 100644 index 00000000000..018b4b475d7 --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_clrpend.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_clrpend.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "nvic.h" +#include "up_arch.h" + +#include "nrf52_irq.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_clrpend + * + * Description: + * Clear a pending interrupt at the NVIC. This does not seem to be required + * for most interrupts. + * + * This function is logically a part of nrf52_irq.c, but I will keep it in + * a separate file so that it will not increase the footprint on NRF52 + * platforms that do not need this function. + * + ****************************************************************************/ + +void nrf52_clrpend(int irq) +{ + /* Check for external interrupt */ + + if (irq >= NRF52_IRQ_EXTINT) + { + if (irq < (NRF52_IRQ_EXTINT + 32)) + { + putreg32(1 << (irq - NRF52_IRQ_EXTINT), NVIC_IRQ0_31_CLRPEND); + } + else if (irq < NRF52_IRQ_NIRQS) + { + putreg32(1 << (irq - NRF52_IRQ_EXTINT - 32), NVIC_IRQ32_63_CLRPEND); + } + } +} diff --git a/arch/arm/src/nrf52/nrf52_config.h b/arch/arm/src/nrf52/nrf52_config.h new file mode 100644 index 00000000000..75eda666bd1 --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_config.h @@ -0,0 +1,87 @@ +/************************************************************************************ + * arch/arm/src/nrf52/nrf52_config.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_NRF52_CONFIG_H +#define __ARCH_ARM_SRC_NRF52_NRF52_CONFIG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Configuration *********************************************************************/ +/* Make sure that no unsupported UART, I2C master, or SPI master peripherals are + * enabled. + */ + +/* Map logical UART names (Just for simplicity of naming) */ + +#undef HAVE_UART0 + +#ifdef CONFIG_NRF52_UART0 +# define HAVE_UART0 1 +#endif + +/* Check if we have a UART device */ + +#undef CONFIG_NRF52_HAVE_UART +#undef HAVE_UART_DEVICE + +#if defined(HAVE_UART0) +# define HAVE_UART_DEVICE 1 +#endif + +/* Is there a serial console? There should be at most one defined. */ + +#undef HAVE_UART_CONSOLE + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(HAVE_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_NRF52_NRF52_CONFIG_H */ diff --git a/arch/arm/src/nrf52/nrf52_gpio.c b/arch/arm/src/nrf52/nrf52_gpio.c new file mode 100644 index 00000000000..22f0d2a8d27 --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_gpio.c @@ -0,0 +1,197 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_gpio.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include "up_arch.h" +#include "chip/nrf52_gpio.h" +#include "nrf52_gpio.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_gpio_input + * + * Description: + * Configure a GPIO input pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +static inline void nrf52_gpio_input(unsigned int port, unsigned int pin) +{ + /* Set as input */ + + if (port == 0) + { + putreg32(1 << pin, NRF52_GPIO0_DIRCLR); + } +} + +/**************************************************************************** + * Name: nrf52_gpio_output + * + * Description: + * Configure a GPIO output pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +static inline void nrf52_gpio_output(nrf52_pinset_t cfgset, + unsigned int port, unsigned int pin) +{ + nrf52_gpio_write(cfgset, ((cfgset & GPIO_VALUE) != GPIO_VALUE_ZERO)); + + /* Configure the pin as an output */ + + if (port == 0) + { + putreg32(1 << pin, NRF52_GPIO0_DIRSET); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_gpio_config + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int nrf52_gpio_config(nrf52_pinset_t cfgset) +{ + unsigned int port; + unsigned int pin; + + /* Verify that this hardware supports the select GPIO port */ + + port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + if (port < NRF52_GPIO_NPORTS) + { + /* Get the pin number and select the port configuration register for + * that pin. + */ + + pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* First, configure the port as a generic input so that we have a + * known starting point and consistent behavior during the re- + * configuration. + */ + + nrf52_gpio_input(port, pin); + + /* Set the mode bits */ + + //nrf52_gpio_iocon(cfgset, port, pin); + + /* Handle according to pin function */ + + switch (cfgset & GPIO_FUNC_MASK) + { + case GPIO_INPUT: /* GPIO input pin */ + break; /* Already configured */ + +#ifdef CONFIG_NRF52_GPIOIRQ + case GPIO_INTFE: /* GPIO interrupt falling edge */ + case GPIO_INTRE: /* GPIO interrupt rising edge */ + case GPIO_INTBOTH: /* GPIO interrupt both edges */ + case GPIO_INTLOW: /* GPIO interrupt low level */ + case GPIO_INTHIGH: /* GPIO interrupt high level */ + nrf52_gpio_interrupt(cfgset); + break; +#endif + + case GPIO_OUTPUT: /* GPIO outpout pin */ + nrf52_gpio_output(cfgset, port, pin); + break; + + default: + return -EINVAL; + } + } + + return OK; +} + +/**************************************************************************** + * Name: nrf52_gpio_write + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void nrf52_gpio_write(nrf52_pinset_t pinset, bool value) +{ + unsigned int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + if (value) + { + putreg32(1 << pin, NRF52_GPIO0_OUTSET); + } + else + { + putreg32(1 << pin, NRF52_GPIO0_OUTCLR); + } +} + +/**************************************************************************** + * Name: nrf52_gpio_read + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool nrf52_gpio_read(nrf52_pinset_t pinset) +{ +} diff --git a/arch/arm/src/nrf52/nrf52_gpio.h b/arch/arm/src/nrf52/nrf52_gpio.h new file mode 100644 index 00000000000..7c1d1f822b2 --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_gpio.h @@ -0,0 +1,307 @@ +/************************************************************************************ + * arch/arm/src/nrf52/nrf52_gpio.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_NRF52_GPIO_H +#define __ARCH_ARM_SRC_NRF52_NRF52_GPIO_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +#include +#include "chip/nrf52_gpio.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Bit-encoded input to nrf52_gpio_config() *****************************************/ + +/* 32-Bit Encoding: .... .... .... .... FFSS DDDM MVPN NNNN + * + * Pin Function: FF + * Pin Sense: SS + * Pin Drive: DDD + * Pin Mode bits: MM + * Initial value: V (output pins) + * Port number: P (0-1) + * Pin number: NNNNN (0-31) + */ + +/* Pin Function bits: + * Only meaningful when the GPIO function is GPIO_PIN + * + * .... .... .... .... FF.. .... .... .... + */ + +#define GPIO_FUNC_SHIFT (14) /* Bits 14-15: GPIO mode */ +#define GPIO_FUNC_MASK (0x03 << GPIO_FUNC_SHIFT) +# define GPIO_INPUT (0x00 << GPIO_FUNC_SHIFT) /* 00000 GPIO input pin */ +# define GPIO_OUTPUT (0x01 << GPIO_FUNC_SHIFT) /* 00001 GPIO output pin */ + +/* Pin Sense bits: + * + * .... .... .... .... ..SS .... .... .... + */ + +#define GPIO_SENSE_SHIFT (12) /* Bits 12-13: Pin Sense mode */ +#define GPIO_SENSE_MASK (0x3 << GPIO_SENSE_SHIFT) +# define GPIO_SENSE_NONE (0 << GPIO_SENSE_SHIFT) +# define GPIO_SENSE_HIGH (2 << GPIO_SENSE_SHIFT) +# define GPIO_SENSE_LOW (3 << GPIO_SENSE_SHIFT) + +/* Pin Drive bits: + * + * .... .... .... .... .... DDD. .... .... + */ + +#define GPIO_DRIVE_SHIFT (9) /* Bits 9-11: Pin pull-up mode */ +#define GPIO_DRIVE_MASK (0x3 << GPIO_DRIVE_SHIFT) +# define GPIO_DRIVE_S0S1 (0 << GPIO_DRIVE_SHIFT) /* Standard '0', standard '1' */ +# define GPIO_DRIVE_H0S1 (1 << GPIO_DRIVE_SHIFT) /* High drive '0', standard '1' */ +# define GPIO_DRIVE_S0H1 (2 << GPIO_DRIVE_SHIFT) /* */ +# define GPIO_DRIVE_H0H1 (3 << GPIO_DRIVE_SHIFT) /* */ +# define GPIO_DRIVE_D0S1 (4 << GPIO_DRIVE_SHIFT) /* */ +# define GPIO_DRIVE_D0H1 (5 << GPIO_DRIVE_SHIFT) /* */ +# define GPIO_DRIVE_S0D1 (6 << GPIO_DRIVE_SHIFT) /* */ +# define GPIO_DRIVE_H0D1 (7 << GPIO_DRIVE_SHIFT) /* */ + +/* Pin Mode: MM + * + * .... .... .... .... .... ...M M... .... + */ + +#define GPIO_MODE_SHIFT (7) /* Bits 7-8: Pin pull-up mode */ +#define GPIO_MODE_MASK (0x3 << GPIO_MODE_SHIFT) +# define GPIO_FLOAT (GPIO_MODE_FLOAT << GPIO_MODE_SHIFT) /* Neither pull-up nor -down */ +# define GPIO_PULLDOWN (GPIO_MODE_PULLDOWN << GPIO_MODE_SHIFT) /* Pull-down resistor enabled */ +# define GPIO_PULLUP (GPIO_MODE_PULLUP << GPIO_MODE_SHIFT) /* Pull-up resistor enabled */ + +/* Initial value: V + * + * .... .... .... .... .... .... .V.. .... + */ + +#define GPIO_VALUE (1 << 6) /* Bit 6: Initial GPIO output value */ +# define GPIO_VALUE_ONE GPIO_VALUE +# define GPIO_VALUE_ZERO (0) + +/* Port number: PPP (0-5) + * + * .... .... .... .... .... .... ..P. .... + */ + +#define GPIO_PORT_SHIFT (5) /* Bit 5: Port number */ +#define GPIO_PORT_MASK (0x1 << GPIO_PORT_SHIFT) +# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT) +# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT) + +/* Pin number: NNNNN (0-31) + * + * .... .... .... .... .... .... ...N NNNN + */ + +#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */ +#define GPIO_PIN_MASK (0x1f << GPIO_PIN_SHIFT) +# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) +# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) +# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) +# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) +# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) +# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) +# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) +# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) +# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) +# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) +# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) +# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) +# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) +# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) +# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) +# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) +# define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) +# define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) +# define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) +# define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) +# define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) +# define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) +# define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) +# define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) +# define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) +# define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) +# define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) +# define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) +# define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) +# define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) +# define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) +# define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +typedef uint32_t nrf52_pinset_t; + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: nrf52_gpio_irqinitialize + * + * Description: + * Initialize logic to support interrupting GPIO pins. This function is called by + * the OS inialization logic and is not a user interface. + * + ************************************************************************************/ + +#ifdef CONFIG_NRF52_GPIOIRQ +void nrf52_gpio_irqinitialize(void); +#else +# define nrf52_gpio_irqinitialize() +#endif + +/************************************************************************************ + * Name: nrf52_gpio_config + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ************************************************************************************/ + +int nrf52_gpio_config(nrf52_pinset_t cfgset); + +/************************************************************************************ + * Name: nrf52_gpio_interrupt + * + * Description: + * Configure a GPIO interrupt pin based on bit-encoded description of the pin. + * This function is called by nrf52_gpio_config to setup interrupting pins. It is + * not a user interface. + * + ************************************************************************************/ + +#ifdef CONFIG_NRF52_GPIOIRQ +int nrf52_gpio_interrupt(nrf52_pinset_t pinset); +#endif + +/************************************************************************************ + * Name: nrf52_gpio_irqno + * + * Description: + * Returns the IRQ number that was associated with an interrupt pin after it was + * configured. + * + ************************************************************************************/ + +#ifdef CONFIG_NRF52_GPIOIRQ +int nrf52_gpio_irqno(nrf52_pinset_t pinset); +#endif + +/************************************************************************************ + * Name: nrf52_gpio_ackedge + * + * Description: + * Acknowledge edge interrupts by clearing the associated bits in the rising and + * falling registers. This acknowledgemment is, of course, not needed for level + * interupts. + * + ************************************************************************************/ + +#ifdef CONFIG_NRF52_GPIOIRQ +int nrf52_gpio_ackedge(int irq); +#endif + +/************************************************************************************ + * Name: rnf52_gpio_write + * + * Description: + * Write one or zero to the selected GPIO pin + * + ************************************************************************************/ + +void nrf52_gpio_write(nrf52_pinset_t pinset, bool value); + +/************************************************************************************ + * Name: nrf52_gpio_read + * + * Description: + * Read one or zero from the selected GPIO pin + * + ************************************************************************************/ + +bool nrf52_gpio_read(nrf52_pinset_t pinset); + +/************************************************************************************ + * Function: nf52_gpio_dump + * + * Description: + * Dump all GPIO registers associated with the base address of the provided pinset. + * + ************************************************************************************/ + +#ifdef CONFIG_DEBUG_GPIO_INFO +int nrf52_gpio_dump(nrf52_pinset_t pinset, const char *msg); +#else +# define nrf52_gpio_dump(p,m) +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_NRF52_NRF52_GPIO_H */ diff --git a/arch/arm/src/nrf52/nrf52_idle.c b/arch/arm/src/nrf52/nrf52_idle.c new file mode 100644 index 00000000000..ece1372c39e --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_idle.c @@ -0,0 +1,185 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_idle.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include + +#include "up_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE) +# define BEGIN_IDLE() board_autoled_on(LED_IDLE) +# define END_IDLE() board_autoled_off(LED_IDLE) +#else +# define BEGIN_IDLE() +# define END_IDLE() +#endif + +#define PM_IDLE_DOMAIN 0 /* Revisit */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idlepm + * + * Description: + * Perform IDLE state power management. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void up_idlepm(void) +{ + static enum pm_state_e oldstate = PM_NORMAL; + enum pm_state_e newstate; + irqstate_t flags; + int ret; + + /* Decide, which power saving level can be obtained */ + + newstate = pm_checkstate(PM_IDLE_DOMAIN); + + /* Check for state changes */ + + if (newstate != oldstate) + { + flags = enter_critical_section(); + + /* Perform board-specific, state-dependent logic here */ + + _info("newstate= %d oldstate=%d\n", newstate, oldstate); + + /* Then force the global state change */ + + ret = pm_changestate(PM_IDLE_DOMAIN, newstate); + if (ret < 0) + { + /* The new state change failed, revert to the preceding state */ + + (void)pm_changestate(PM_IDLE_DOMAIN, oldstate); + } + else + { + /* Save the new state */ + + oldstate = newstate; + } + + /* MCU-specific power management logic */ + + switch (newstate) + { + case PM_NORMAL: + break; + + case PM_IDLE: + break; + + case PM_STANDBY: + nrf52_pmstandby(true); + break; + + case PM_SLEEP: + (void)nrf52_pmsleep(); + break; + + default: + break; + } + + leave_critical_section(flags); + } +} +#else +# define up_idlepm() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when their is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + sched_process_timer(); +#else + + /* Perform IDLE mode power management */ + + up_idlepm(); + + /* Sleep until an interrupt occurs to save power */ + + BEGIN_IDLE(); + asm("WFI"); + END_IDLE(); +#endif +} diff --git a/arch/arm/src/nrf52/nrf52_irq.c b/arch/arm/src/nrf52/nrf52_irq.c new file mode 100644 index 00000000000..7452d689078 --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_irq.c @@ -0,0 +1,562 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_irq.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "nvic.h" +#include "ram_vectors.h" +#include "up_arch.h" +#include "up_internal.h" + +#include "nrf52_gpio.h" +#include "nrf52_irq.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Get a 32-bit version of the default priority */ + +#define DEFPRIORITY32 \ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT) + +/* Given the address of a NVIC ENABLE register, this is the offset to + * the corresponding CLEAR ENABLE register. + */ + +#define NVIC_ENA_OFFSET (0) +#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_current_regs[] holds a references to the current interrupt level + * register storage structure. If is non-NULL only during interrupt + * processing. Access to g_current_regs[] must be through the macro + * CURRENT_REGS for portability. + */ + +volatile uint32_t *g_current_regs[1]; + +/* This is the address of the exception vector table (determined by the + * linker script). + */ + +extern uint32_t _vectors[]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_dumpnvic + * + * Description: + * Dump some interesting NVIC registers + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_IRQ_INFO) +static void nrf52_dumpnvic(const char *msg, int irq) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + irqinfo("NVIC (%s, irq=%d):\n", msg, irq); + irqinfo(" INTCTRL: %08x VECTAB: %08x\n", + getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB)); +#if 0 + irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n", + getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA), + getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE)); +#endif + irqinfo(" IRQ ENABLE: %08x %08x\n", + getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE)); + irqinfo(" SYSH_PRIO: %08x %08x %08x\n", + getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY), + getreg32(NVIC_SYSH12_15_PRIORITY)); + irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY), + getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY), + getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY)); + irqinfo(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY), + getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY)); + irqinfo(" %08x %08x %08x\n", + getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY), + getreg32(NVIC_IRQ56_59_PRIORITY)); + + leave_critical_section(flags); +} +#else +# define nrf52_dumpnvic(msg, irq) +#endif + +/**************************************************************************** + * Name: nrf52_nmi, nrf52_busfault, nrf52_usagefault, nrf52_pendsv, + * nrf52_dbgmonitor, nrf52_pendsv, nrf52_reserved + * + * Description: + * Handlers for various exceptions. None are handled and all are fatal + * error conditions. The only advantage these provided over the default + * unexpected interrupt handler is that they provide a diagnostic output. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +static int nrf52_nmi(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! NMI received\n"); + PANIC(); + return 0; +} + +static int nrf52_busfault(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! Bus fault recived\n"); + PANIC(); + return 0; +} + +static int nrf52_usagefault(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! Usage fault received\n"); + PANIC(); + return 0; +} + +static int nrf52_pendsv(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! PendSV received\n"); + PANIC(); + return 0; +} + +static int nrf52_dbgmonitor(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! Debug Monitor received\n"); + PANIC(); + return 0; +} + +static int nrf52_reserved(int irq, FAR void *context, FAR void *arg) +{ + (void)up_irq_save(); + _err("PANIC!!! Reserved interrupt\n"); + PANIC(); + return 0; +} +#endif + +/**************************************************************************** + * Name: nrf52_prioritize_syscall + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV7M_USEBASEPRI +static inline void nrf52_prioritize_syscall(int priority) +{ + uint32_t regval; + + /* SVCALL is system handler 11 */ + + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); +} +#endif + +/**************************************************************************** + * Name: nrf52_irqinfo + * + * Description: + * Given an IRQ number, provide the register and bit setting to enable or + * disable the irq. + * + ****************************************************************************/ + +static int nrf52_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, + uintptr_t offset) +{ + int n; + + DEBUGASSERT(irq >= NRF52_IRQ_NMI && irq < NR_IRQS); + + /* Check for external interrupt */ + + if (irq >= NRF52_IRQ_EXTINT) + { + n = irq - NRF52_IRQ_EXTINT; + *regaddr = NVIC_IRQ_ENABLE(n) + offset; + *bit = (uint32_t)1 << (n & 0x1f); + } + + /* Handle processor exceptions. Only a few can be disabled */ + + else + { + *regaddr = NVIC_SYSHCON; + if (irq == NRF52_IRQ_MEMFAULT) + { + *bit = NVIC_SYSHCON_MEMFAULTENA; + } + else if (irq == NRF52_IRQ_BUSFAULT) + { + *bit = NVIC_SYSHCON_BUSFAULTENA; + } + else if (irq == NRF52_IRQ_USAGEFAULT) + { + *bit = NVIC_SYSHCON_USGFAULTENA; + } + else if (irq == NRF52_IRQ_SYSTICK) + { + *regaddr = NVIC_SYSTICK_CTRL; + *bit = NVIC_SYSTICK_CTRL_ENABLE; + } + else + { + return ERROR; /* Invalid or unsupported exception */ + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + * + * Description: + * Complete initialization of the interrupt system and enable normal, + * interrupt processing. + * + ****************************************************************************/ + +void up_irqinitialize(void) +{ + uint32_t regaddr; +#ifdef CONFIG_DEBUG_FEATURES + uint32_t regval; +#endif + int num_priority_registers; + int i; + + /* Disable all interrupts */ + + for (i = 0; i < NRF52_IRQ_NEXTINT; i += 32) + { + putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); + } + + /* Make sure that we are using the correct vector table. The default + * vector address is 0x0000:0000 but if we are executing code that is + * positioned in SRAM or in external FLASH, then we may need to reset + * the interrupt vector so that it refers to the table in SRAM or in + * external FLASH. + */ + + putreg32((uint32_t)_vectors, NVIC_VECTAB); + +#ifdef CONFIG_ARCH_RAMVECTORS + /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based + * vector table that requires special initialization. + */ + + up_ramvec_initialize(); +#endif + + /* Set all interrupts (and exceptions) to the default priority */ + + putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); + + /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt + * lines that the NVIC supports: + * + * 0 -> 32 interrupt lines, 8 priority registers + * 1 -> 64 " " " ", 16 priority registers + * 2 -> 96 " " " ", 32 priority registers + * ... + */ + + num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8; + + /* Now set all of the interrupt lines to the default priority */ + + regaddr = NVIC_IRQ0_3_PRIORITY; + while (num_priority_registers--) + { + putreg32(DEFPRIORITY32, regaddr); + regaddr += 4; + } + + /* currents_regs is non-NULL only while processing an interrupt */ + + CURRENT_REGS = NULL; + + /* Attach the SVCall and Hard Fault exception handlers. The SVCall + * exception is used for performing context switches; The Hard Fault + * must also be caught because a SVCall may show up as a Hard Fault + * under certain conditions. + */ + + irq_attach(NRF52_IRQ_SVCALL, up_svcall, NULL); + irq_attach(NRF52_IRQ_HARDFAULT, up_hardfault, NULL); + + /* Set the priority of the SVCall interrupt */ + +#ifdef CONFIG_ARCH_IRQPRIO + /* up_prioritize_irq(NRF52_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ +#endif + +#ifdef CONFIG_ARMV7M_USEBASEPRI + nrf52_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); +#endif + +#ifdef CONFIG_ARM_MPU + /* If the MPU is enabled, then attach and enable the Memory Management + * Fault handler. + */ + + irq_attach(NRF52_IRQ_MEMFAULT, up_memfault, NULL); + up_enable_irq(NRF52_IRQ_MEMFAULT); +#endif + + /* Attach all other processor exceptions (except reset and sys tick) */ + +#ifdef CONFIG_DEBUG_FEATURES + irq_attach(NRF52_IRQ_NMI, nrf52_nmi, NULL); +#ifndef CONFIG_ARM_MPU + irq_attach(NRF52_IRQ_MEMFAULT, up_memfault, NULL); +#endif + irq_attach(NRF52_IRQ_BUSFAULT, nrf52_busfault, NULL); + irq_attach(NRF52_IRQ_USAGEFAULT, nrf52_usagefault, NULL); + irq_attach(NRF52_IRQ_PENDSV, nrf52_pendsv, NULL); + irq_attach(NRF52_IRQ_DBGMONITOR, nrf52_dbgmonitor, NULL); + irq_attach(NRF52_IRQ_RESERVED, nrf52_reserved, NULL); +#endif + + nrf52_dumpnvic("initial", NRF52_IRQ_NIRQS); + +#if defined(CONFIG_DEBUG_FEATURES) && !defined(CONFIG_ARMV7M_USEBASEPRI) + /* If a debugger is connected, try to prevent it from catching hardfaults. + * If CONFIG_ARMV7M_USEBASEPRI, no hardfaults are expected in normal + * operation. + */ + + regval = getreg32(NVIC_DEMCR); + regval &= ~NVIC_DEMCR_VCHARDERR; + putreg32(regval, NVIC_DEMCR); +#endif + +#ifdef CONFIG_NRF52_GPIOIRQ + /* Initialize GPIO interrupts */ + + nrf52_gpio_irqinitialize(); +#endif + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + /* And finally, enable interrupts */ + + up_irq_enable(); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (nrf52_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to disable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Clear Enable register. For other exceptions, we need to + * clear the bit in the System Handler Control and State Register. + */ + + if (irq >= NRF52_IRQ_EXTINT) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval &= ~bit; + putreg32(regval, regaddr); + } + } + + nrf52_dumpnvic("disable", irq); +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (nrf52_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to enable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Set Enable register. For other exceptions, we need to + * set the bit in the System Handler Control and State Register. + */ + + if (irq >= NRF52_IRQ_EXTINT) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } + } + + nrf52_dumpnvic("enable", irq); +} + +/**************************************************************************** + * Name: up_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void up_ack_irq(int irq) +{ + nrf52_clrpend(irq); +} + +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int irq, int priority) +{ + uint32_t regaddr; + uint32_t regval; + int shift; + + DEBUGASSERT(irq >= NRF52_IRQ_MEMFAULT && irq < NR_IRQS && + (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); + + if (irq < NRF52_IRQ_EXTINT) + { + /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority + * registers (0-3 are invalid) + */ + + regaddr = NVIC_SYSH_PRIORITY(irq); + irq -= 4; + } + else + { + /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ + + irq -= NRF52_IRQ_EXTINT; + regaddr = NVIC_IRQ_PRIORITY(irq); + } + + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + nrf52_dumpnvic("prioritize", irq); + return OK; +} +#endif diff --git a/arch/arm/src/nrf52/nrf52_irq.h b/arch/arm/src/nrf52/nrf52_irq.h new file mode 100644 index 00000000000..6cbfe781b31 --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_irq.h @@ -0,0 +1,60 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_irq.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_NRF52_IRQ_H +#define __ARCH_ARM_SRC_NRF52_NRF52_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_clrpend + * + * Description: + * Clear a pending interrupt at the NVIC. This does not seem to be + * required for most interrupts. + * + ****************************************************************************/ + +void nrf52_clrpend(int irq); + +#endif /* __ARCH_ARM_SRC_NRF52_NRF52_IRQ_H */ diff --git a/arch/arm/src/nrf52/nrf52_lowputc.c b/arch/arm/src/nrf52/nrf52_lowputc.c new file mode 100644 index 00000000000..a6f8f3de068 --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_lowputc.c @@ -0,0 +1,225 @@ +/**************************************************************************** + * arch/arm/src/rnf52/nrf52_lowputc.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "chip/nrf52_memorymap.h" +#include "chip/nrf52_uarte.h" + +#include "nrf52_config.h" +#include "nrf52_clockconfig.h" +#include "nrf52_gpio.h" +#include "nrf52_lowputc.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef HAVE_UART_CONSOLE + +#define CONSOLE_BASE NRF52_UART0_BASE +#define CONSOLE_BAUD CONFIG_UART0_BAUD +#define CONSOLE_BITS CONFIG_UART0_BITS +#define CONSOLE_PARITY CONFIG_UART0_PARITY +#define CONSOLE_2STOP CONFIG_UART0_2STOP + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* UART console configuration */ + +static const struct uart_config_s g_console_config= +{ + .baud = CONSOLE_BAUD, + .parity = CONSOLE_PARITY, + .bits = CONSOLE_BITS, + .stopbits2 = CONSOLE_2STOP, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .iflow = CONSOLE_IFLOW, +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + .oflow = CONSOLE_OFLOW, +#endif + .txpin = BOARD_UART0_TX_PIN, + .rxpin = BOARD_UART0_RX_PIN, +}; +#endif /* HAVE_UART_CONSOLE */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_setbaud + * + * Description: + * Configure the UART BAUD. + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +static void nrf52_setbaud(uintptr_t base, const struct uart_config_s *config) +{ + uint32_t br = 0x01D7E000; /* 268.444444 */ + + if (config->baud == 115200) + { + br = 0x01D7E000; + } + + putreg32(br, base + NRF52_UART_BAUDRATE_OFFSET); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level initialization + * including setup of the console UART. This UART initialization is done + * early so that the serial console is available for debugging very early in + * the boot sequence. + * + ****************************************************************************/ + +void nrf52_lowsetup(void) +{ +#ifdef HAVE_UART_DEVICE +#ifdef HAVE_UART_CONSOLE + /* Configure the console UART (if any) */ + + nrf52_usart_configure(CONSOLE_BASE, &g_console_config); + +#endif /* HAVE_UART_CONSOLE */ +#endif /* HAVE_UART_DEVICE */ +} + +/**************************************************************************** + * Name: nrf52_usart_configure + * + * Description: + * Configure a UART for non-interrupt driven operation + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +void nrf52_usart_configure(uintptr_t base, const struct uart_config_s *config) +{ + uint32_t pin; + + putreg32(1, base + NRF52_UART_TASKS_STOPRX_OFFSET); + putreg32(1, base + NRF52_UART_TASKS_STOPTX_OFFSET); + putreg32(NRF52_UART_ENABLE_DISABLE, base + NRF52_UART_ENABLE_OFFSET); + + /* Configure baud */ + + nrf52_setbaud(base, config); + + /* Config and select pins for uart */ + + nrf52_gpio_config(config->txpin); + nrf52_gpio_config(config->rxpin); + + pin = (config->txpin & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + putreg32(pin, base + NRF52_UART_PSELTXD_OFFSET); + pin = (config->rxpin & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + putreg32(pin, base + NRF52_UART_PSELRXD_OFFSET); + + /* Enable */ + + putreg32(NRF52_UART_ENABLE_ENABLE, base + NRF52_UART_ENABLE_OFFSET); + putreg32(1, base + NRF52_UART_TASKS_STARTTX_OFFSET); + putreg32(1, base + NRF52_UART_TASKS_STARTRX_OFFSET); +} +#endif + +/**************************************************************************** + * Name: nrf52_usart_disable + * + * Description: + * Disable a UART. it will be necessary to again call + * nrf52_usart_configure() in order to use this UART channel again. + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +void nrf52_usart_disable(uintptr_t base) +{ + /* Disable interrupts */ + /* Disable the UART */ + + putreg32(1, base + NRF52_UART_TASKS_STOPRX_OFFSET); + putreg32(1, base + NRF52_UART_TASKS_STOPTX_OFFSET); + putreg32(NRF52_UART_ENABLE_DISABLE, base + NRF52_UART_ENABLE_OFFSET); + + putreg32(0xFFFFFFFF, base + NRF52_UART_PSELTXD_OFFSET); + putreg32(0xFFFFFFFF, base + NRF52_UART_PSELRXD_OFFSET); +} +#endif + +/**************************************************************************** + * Name: up_lowputc + * + * Description: + * Output one byte on the serial console + * + ****************************************************************************/ + +void up_lowputc(char ch) +{ +#ifdef HAVE_UART_CONSOLE + putreg32(0, CONSOLE_BASE + NRF52_UART_EVENTS_TXDRDY_OFFSET); + putreg32(ch, CONSOLE_BASE + NRF52_UART_TXD_OFFSET); + while (getreg32(CONSOLE_BASE + NRF52_UART_EVENTS_TXDRDY_OFFSET) == 0 ) + { + } +#endif +} diff --git a/arch/arm/src/nrf52/nrf52_lowputc.h b/arch/arm/src/nrf52/nrf52_lowputc.h new file mode 100644 index 00000000000..dd0a57ce244 --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_lowputc.h @@ -0,0 +1,115 @@ +/************************************************************************************ + * arch/arm/src/nrf52/nrf52_lowputc.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_NRF52_LOWPUTC_H +#define __ARCH_ARM_SRC_NRF52_NRF52_LOWPUTC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#ifdef HAVE_UART_DEVICE +/* This structure describes the configuration of an UART */ + +struct uart_config_s +{ + uint32_t baud; /* Configured baud */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (5-9) */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + bool iflow; /* true: Input flow control supported */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + bool oflow; /* true: Output flow control supported. */ +#endif + nrf52_pinset_t txpin; /* TX pin */ + nrf52_pinset_t rxpin; /* RX pin */ +}; +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: nrf52_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level initialization + * including setup of the console UART. This UART initialization is done + * early so that the serial console is available for debugging very early in + * the boot sequence. + * + ************************************************************************************/ + +void nrf52_lowsetup(void); + +/************************************************************************************ + * Name: nrf52_usart_configure + * + * Description: + * Configure a UART for non-interrupt driven operation + * + ************************************************************************************/ + +#ifdef HAVE_UART_DEVICE +void nrf52_usart_configure(uintptr_t base, FAR const struct uart_config_s *config); +#endif + +/**************************************************************************** + * Name: nrf52_usart_disable + * + * Description: + * Disable a UART. it will be necessary to again call + * nrf52_usart_configure() in order to use this UART channel again. + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +void nrf52_usart_disable(uintptr_t base); +#endif + +#endif /* __ARCH_ARM_SRC_NRF52_NRF52_LOWPUTC_H */ diff --git a/arch/arm/src/nrf52/nrf52_serial.c b/arch/arm/src/nrf52/nrf52_serial.c new file mode 100644 index 00000000000..10f4f90ed88 --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_serial.c @@ -0,0 +1,621 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_serial.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "chip.h" +#include "nrf52_config.h" +#include "chip/nrf52_uarte.h" +#include "nrf52_clockconfig.h" +#include "nrf52_lowputc.h" +#include "nrf52_serial.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Some sanity checks *******************************************************/ +/* Is there at least one UART enabled and configured as a RS-232 device? */ + +#ifndef HAVE_UART_DEVICE +# warning "No UARTs enabled" +#endif + +/* If we are not using the serial driver for the console, then we still must + * provide some minimal implementation of up_putc. + */ + +#if defined(HAVE_UART_DEVICE) && defined(USE_SERIALDRIVER) + +/* Which UART with be tty0/console and which tty1-4? The console will + * always be ttyS0. If there is no console then will use the lowest + * numbered UART. + */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure provides the state of one UART device */ + +struct nrf52_dev_s +{ + uintptr_t uartbase; /* Base address of UART registers */ + uint8_t irq; /* IRQ associated with this UART */ + bool rx_available; /* rx byte available */ + + /* UART configuration */ + + struct uart_config_s config; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int nrf52_setup(struct uart_dev_s *dev); +static void nrf52_shutdown(struct uart_dev_s *dev); +static int nrf52_attach(struct uart_dev_s *dev); +static void nrf52_detach(struct uart_dev_s *dev); +static int nrf52_interrupt(int irq, void *context, FAR void *arg); +static int nrf52_ioctl(struct file *filep, int cmd, unsigned long arg); +static int nrf52_receive(struct uart_dev_s *dev, uint32_t *status); +static void nrf52_rxint(struct uart_dev_s *dev, bool enable); +static bool nrf52_rxavailable(struct uart_dev_s *dev); +static void nrf52_send(struct uart_dev_s *dev, int ch); +static void nrf52_txint(struct uart_dev_s *dev, bool enable); +static bool nrf52_txready(struct uart_dev_s *dev); +static bool nrf52_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = nrf52_setup, + .shutdown = nrf52_shutdown, + .attach = nrf52_attach, + .detach = nrf52_detach, + .ioctl = nrf52_ioctl, + .receive = nrf52_receive, + .rxint = nrf52_rxint, + .rxavailable = nrf52_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = nrf52_send, + .txint = nrf52_txint, + .txready = nrf52_txready, + .txempty = nrf52_txempty, +}; + +/* I/O buffers */ + +#ifdef HAVE_UART0 +static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; +#endif + +/* This describes the state of the NRF52 UART0 port. */ + +#ifdef HAVE_UART0 +static struct nrf52_dev_s g_uart0priv = +{ + .uartbase = NRF52_UART0_BASE, + .irq = NRF52_IRQ_UART0, + .rx_available = false, + .config = + { + .baud = CONFIG_UART0_BAUD, + .parity = CONFIG_UART0_PARITY, + .bits = CONFIG_UART0_BITS, + .stopbits2 = CONFIG_UART0_2STOP, +#ifdef CONFIG_UART0_IFLOWCONTROL + .iflow = true, +#endif +#ifdef CONFIG_UART0_OFLOWCONTROL + .oflow = true, +#endif + } +}; + +static uart_dev_t g_uart0port = +{ + .recv = + { + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart0priv, +}; +#endif + +#define CONSOLE_DEV g_uart0port /* UART0 is console */ +#define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_setup + * + * Description: + * Configure the UART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int nrf52_setup(struct uart_dev_s *dev) +{ +#ifndef CONFIG_SUPPRESS_UART_CONFIG + struct nrf52_dev_s *priv = (struct nrf52_dev_s *)dev->priv; + + /* Configure the UART as an RS-232 UART */ + + nrf52_usart_configure(priv->uartbase, &priv->config); +#endif + + return OK; +} + +/**************************************************************************** + * Name: nrf52_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void nrf52_shutdown(struct uart_dev_s *dev) +{ + struct nrf52_dev_s *priv = (struct nrf52_dev_s *)dev->priv; + + /* Disable interrupts */ + /* Reset hardware and disable Rx and Tx */ + + nrf52_usart_disable(priv->uartbase); +} + +/**************************************************************************** + * Name: nrf52_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless the + * hardware supports multiple levels of interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() methods are called. + * + ****************************************************************************/ + +static int nrf52_attach(struct uart_dev_s *dev) +{ + struct nrf52_dev_s *priv = (struct nrf52_dev_s *)dev->priv; + int ret; + + /* Attach and enable the IRQ(s). The interrupts are (probably) still + * disabled in the C2 register. + */ + + ret = irq_attach(priv->irq, nrf52_interrupt, dev); + if (ret == OK) + { + up_enable_irq(priv->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: nrf52_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception + * is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void nrf52_detach(struct uart_dev_s *dev) +{ + struct nrf52_dev_s *priv = (struct nrf52_dev_s *)dev->priv; + + /* Disable interrupts */ + + up_disable_irq(priv->irq); + + /* Detach from the interrupt(s) */ + + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: nrf52_interrupt + * + * Description: + * This is the UART status interrupt handler. It will be invoked when an + * interrupt received on the 'irq' It should call uart_transmitchars or + * uart_receivechar to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'irq' number into the + * approprite uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int nrf52_interrupt(int irq, void *context, FAR void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct nrf52_dev_s *priv; + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = (struct nrf52_dev_s *)dev->priv; + + /* Clear RX event */ + putreg32(0 , priv->uartbase + NRF52_UART_EVENTS_RXDRDY_OFFSET); + priv->rx_available = true; + + uart_recvchars(dev); + + //uart_xmitchars(dev); + + return OK; +} + +/**************************************************************************** + * Name: nrf52_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int nrf52_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + return -ENOTTY; +} + +/**************************************************************************** + * Name: nrf52_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int nrf52_receive(struct uart_dev_s *dev, uint32_t *status) +{ + struct nrf52_dev_s *priv = (struct nrf52_dev_s *)dev->priv; + uint32_t data; + + /* Get input data along with receiver control information */ + + data = getreg32(priv->uartbase + NRF52_UART_RXD_OFFSET); + priv->rx_available = false; + + /* Return receiver control information */ + + if (status) + { + *status = 0x00; + } + + /* Then return the actual received data. */ + + return data; +} + +/**************************************************************************** + * Name: nrf52_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void nrf52_rxint(struct uart_dev_s *dev, bool enable) +{ + struct nrf52_dev_s *priv = (struct nrf52_dev_s *)dev->priv; + + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + /* Receive an interrupt when their is anything in the Rx data register (or an Rx + * timeout occurs). + */ + + putreg32(NRF52_UART_INTENSET_RXDRDY, + priv->uartbase + NRF52_UART_INTENSET_OFFSET); + +#endif + } + else + { + putreg32(NRF52_UART_INTENSET_RXDRDY, + priv->uartbase + NRF52_UART_INTENCLR_OFFSET); + } +} + +/**************************************************************************** + * Name: nrf52_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +static bool nrf52_rxavailable(struct uart_dev_s *dev) +{ + struct nrf52_dev_s *priv = (struct nrf52_dev_s *)dev->priv; + + /* Return true if the receive buffer/fifo is not "empty." */ + + return priv->rx_available; +} + +/**************************************************************************** + * Name: nrf52_send + * + * Description: + * This method will send one byte on the UART. + * + ****************************************************************************/ + +static void nrf52_send(struct uart_dev_s *dev, int ch) +{ + struct nrf52_dev_s *priv = (struct nrf52_dev_s *)dev->priv; + + putreg32(0, priv->uartbase + NRF52_UART_EVENTS_TXDRDY_OFFSET); + putreg32(ch, priv->uartbase + NRF52_UART_TXD_OFFSET); + while (getreg32(priv->uartbase + NRF52_UART_EVENTS_TXDRDY_OFFSET) == 0 ) + { + } +} + +/**************************************************************************** + * Name: nrf52_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void nrf52_txint(struct uart_dev_s *dev, bool enable) +{ + /* struct nrf52_dev_s *priv = (struct nrf52_dev_s *)dev->priv; */ + + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + irqstate_t flags; + + /* Enable the TX interrupt */ + + flags = enter_critical_section(); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); + leave_critical_section(flags); +#endif + } + else + { + /* Disable the TX interrupt */ + } +} + +/**************************************************************************** + * Name: nrf52_txready + * + * Description: + * Return true if the tranmsit data register is empty + * + ****************************************************************************/ + +static bool nrf52_txready(struct uart_dev_s *dev) +{ + /* struct nrf52_dev_s *priv = (struct nrf52_dev_s *)dev->priv; */ + + /* Return true if the transmit FIFO is "not full." */ + + return true; +} + +/**************************************************************************** + * Name: nrf52_txempty + * + * Description: + * Return true if the transmit data register is empty + * + ****************************************************************************/ + +static bool nrf52_txempty(struct uart_dev_s *dev) +{ + /* struct nrf52_dev_s *priv = (struct nrf52_dev_s *)dev->priv; */ + + /* Return true if the transmit FIFO is "empty." */ + + return true; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before nrf52_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in nrf52_lowsetup() and main clock iniialization + * performed in nrf_clock_configure(). + * + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT +void nrf52_earlyserialinit(void) +{ + /* Configuration whichever one is the console */ + +#ifdef HAVE_UART_CONSOLE + CONSOLE_DEV.isconsole = true; + nrf52_setup(&CONSOLE_DEV); +#endif +} +#endif + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that nrf52_earlyserialinit was called previously. + * + * Input Parameters: + * None + * + * Returns Value: + * None + * + ****************************************************************************/ + +void up_serialinit(void) +{ +#ifdef HAVE_UART_CONSOLE + /* Register the serial console */ + + (void)uart_register("/dev/console", &CONSOLE_DEV); +#endif + + (void)uart_register("/dev/ttyS0", &TTYS0_DEV); +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_UART_CONSOLE + /* struct nrf52_dev_s *priv = (struct nrf52_dev_s *)CONSOLE_DEV.priv; */ + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); +#endif + + return ch; +} + +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_UART_CONSOLE + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); + return ch; +#endif +} + +#endif /* HAVE_UART_DEVICE && USE_SERIALDRIVER */ diff --git a/arch/arm/src/nrf52/nrf52_serial.h b/arch/arm/src/nrf52/nrf52_serial.h new file mode 100644 index 00000000000..90d83c31afc --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_serial.h @@ -0,0 +1,66 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_serial.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_NRF52_SERIAL_H +#define __ARCH_ARM_SRC_NRF52_NRF52_SERIAL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "nrf52_config.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before nrf52_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in xmc_lowsetup() and main clock initialization + * performed in xmc_clock_configure(). + * + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT +void nrf52_earlyserialinit(void); +#endif + +#endif /* __ARCH_ARM_SRC_NRF52_NRF52_SERIAL_H */ diff --git a/arch/arm/src/nrf52/nrf52_start.c b/arch/arm/src/nrf52/nrf52_start.c new file mode 100644 index 00000000000..7ca37b95467 --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_start.c @@ -0,0 +1,257 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_start.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "up_arch.h" +#include "up_internal.h" +#include "nvic.h" + +#include "nrf52_clockconfig.h" +//#include "nrf52_userspace.h" +#include "nrf52_lowputc.h" +//#include "nrf52_serial.h" +#include "nrf52_start.h" +#include "nrf52_gpio.h" +#include "nrf52_serial.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: showprogress + * + * Description: + * Print a character on the UART to show boot status. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +# define showprogress(c) up_lowputc(c) +#else +# define showprogress(c) +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_fpuconfig + * + * Description: + * Configure the FPU. Relative bit settings: + * + * CPACR: Enables access to CP10 and CP11 + * CONTROL.FPCA: Determines whether the FP extension is active in the + * current context: + * FPCCR.ASPEN: Enables automatic FP state preservation, then the + * processor sets this bit to 1 on successful completion of any FP + * instruction. + * FPCCR.LSPEN: Enables lazy context save of FP state. When this is + * done, the processor reserves space on the stack for the FP state, + * but does not save that state information to the stack. + * + * Software must not change the value of the ASPEN bit or LSPEN bit while either: + * - the CPACR permits access to CP10 and CP11, that give access to the FP + * extension, or + * - the CONTROL.FPCA bit is set to 1 + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_FPU +#if defined(CONFIG_ARMV7M_CMNVECTOR) && !defined(CONFIG_ARMV7M_LAZYFPU) +static inline void nrf52_fpuconfig(void) +{ + uint32_t regval; + + /* Set CONTROL.FPCA so that we always get the extended context frame + * with the volatile FP registers stacked above the basic context. + */ + + regval = getcontrol(); + regval |= (1 << 2); + setcontrol(regval); + + /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend + * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we + * are going to turn on CONTROL.FPCA for all contexts. + */ + + regval = getreg32(NVIC_FPCCR); + regval &= ~((1 << 31) | (1 << 30)); + putreg32(regval, NVIC_FPCCR); + + /* Enable full access to CP10 and CP11 */ + + regval = getreg32(NVIC_CPACR); + regval |= ((3 << (2 * 10)) | (3 << (2 * 11))); + putreg32(regval, NVIC_CPACR); +} +#else +static inline void nrf52_fpuconfig(void) +{ + uint32_t regval; + + /* Clear CONTROL.FPCA so that we do not get the extended context frame + * with the volatile FP registers stacked in the saved context. + */ + + regval = getcontrol(); + regval &= ~(1 << 2); + setcontrol(regval); + + /* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend + * with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we + * are going to keep CONTROL.FPCA off for all contexts. + */ + + regval = getreg32(NVIC_FPCCR); + regval &= ~((1 << 31) | (1 << 30)); + putreg32(regval, NVIC_FPCCR); + + /* Enable full access to CP10 and CP11 */ + + regval = getreg32(NVIC_CPACR); + regval |= ((3 << (2 * 10)) | (3 << (2 * 11))); + putreg32(regval, NVIC_CPACR); +} +#endif + +#else +# define nrf52_fpuconfig() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _start + * + * Description: + * This is the reset entry point. + * + ****************************************************************************/ + +void __start(void) +{ + const uint32_t *src; + uint32_t *dest; + + /* Make sure that interrupts are disabled */ + + __asm__ __volatile__ ("\tcpsid i\n"); + + /* Configure the clocking and the console uart so that we can get debug + * output as soon as possible. NOTE: That this logic must not assume that + * .bss or .data have beeninitialized. + */ + + nrf52_clockconfig(); + nrf52_lowsetup(); + showprogress('A'); + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = &_sbss; dest < &_ebss; ) + { + *dest++ = 0; + } + + showprogress('B'); + + /* Move the initialized data section from his temporary holding spot in + * FLASH into the correct place in SRAM. The correct place in SRAM is + * give by _sdata and _edata. The temporary location is in FLASH at the + * end of all of the other read-only data (.text, .rodata) at _eronly. + */ + + for (src = &_eronly, dest = &_sdata; dest < &_edata; ) + { + *dest++ = *src++; + } + + showprogress('C'); + + /* Initialize the FPU (if configured) */ + + nrf52_fpuconfig(); + showprogress('D'); + + /* Perform early serial initialization */ + +#ifdef USE_EARLYSERIALINIT + nrf52_earlyserialinit(); +#endif + showprogress('E'); + + /* For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + */ + +#ifdef CONFIG_BUILD_PROTECTED + nrf52_userspace(); + showprogress('F'); +#endif + + /* Initialize onboard resources */ + + nrf52_board_initialize(); + showprogress('G'); + + /* Then start NuttX */ + + showprogress('\r'); + showprogress('\n'); + os_start(); + + /* Shouldn't get here */ + + for (; ; ); +} diff --git a/arch/arm/src/nrf52/nrf52_start.h b/arch/arm/src/nrf52/nrf52_start.h new file mode 100644 index 00000000000..e7639789716 --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_start.h @@ -0,0 +1,88 @@ +/************************************************************************************ + * arch/arm/src/nrf52/nrf52_start.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_NRF52_START_H +#define __ARCH_ARM_SRC_NRF52_NRF52_START_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include +#include +#include + +#include "up_internal.h" +#include "chip.h" + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* g_idle_topstack: _sbss is the start of the BSS region as defined by the linker + * script. _ebss lies at the end of the BSS region. The idle task stack starts at + * the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE thread is + * the thread that the system boots on and, eventually, becomes the IDLE, do + * nothing task that runs only when there is nothing else to run. The heap + * continues from there until the end of memory. g_idle_topstack is a read-only + * variable the provides this computed address. + */ + +extern const uintptr_t g_idle_topstack; + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/************************************************************************************ + * Name: nrf52_board_initialize + * + * Description: + * All NRF52xxx architectures must provide the following entry point. This entry + * point is called early in the initialization -- after clocking and memory have + * been configured but before caches have been enabled and before any devices have + * been initialized. + * + ************************************************************************************/ + +void nrf52_board_initialize(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_NRF52_NRF52_START_H */ diff --git a/arch/arm/src/nrf52/nrf52_timerisr.c b/arch/arm/src/nrf52/nrf52_timerisr.c new file mode 100644 index 00000000000..d15f65e8efd --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_timerisr.c @@ -0,0 +1,148 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_timerisr.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "nvic.h" +#include "clock/clock.h" +#include "up_internal.h" +#include "up_arch.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The SysTick clock may be clocked internally either by the by the system + * clock (CLKSOURCE==1) or by the SysTick function clock (CLKSOURCE==0). + * The SysTick Function clock is equal to: + * + * Fsystick = Fmainclk / SYSTICKCLKDIV + * + * Both the divider value (BOARD_SYSTICKCLKDIV) and the resulting SysTick + * function clock frequency (Fsystick, BOARD_SYSTICK_CLOCK) + * + * The desired timer interrupt frequency is provided by the definition + * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of + * system clock ticks per second. That value is a user configurable setting + * that defaults to 100 (100 ticks per second = 10 MS interval). + * + * reload = (Fsystick / CLK_TICK) - 1 + * + * Tips for selecting BOARD_SYSTICKCLKDIV: The resulting reload value + * should be as large as possible, but must be less than 2^24: + * + * SYSTICKDIV > Fmainclk / CLK_TCK / 2^24 + */ + +#define SYSTICK_RELOAD ((BOARD_SYSTICK_CLOCK / CLK_TCK) - 1) + +/* The size of the reload field is 24 bits. Verify that the reload value + * will fit in the reload register. + */ + +#if SYSTICK_RELOAD > 0x00ffffff +# error SYSTICK_RELOAD exceeds the range of the RELOAD register +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: nrf52_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +static int nrf52_timerisr(int irq, uint32_t *regs, void *arg) +{ + /* Process timer interrupt */ + + sched_process_timer(); + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: arm_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void arm_timer_initialize(void) +{ + uint32_t regval; + + regval = getreg32(NVIC_SYSTICK_CTRL); + regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; + putreg32(regval, NVIC_SYSTICK_CTRL); + + /* Configure SysTick to interrupt at the requested rate */ + + putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); + + /* Attach the timer interrupt vector */ + + (void)irq_attach(NRF52_IRQ_SYSTICK, (xcpt_t)nrf52_timerisr, NULL); + + /* Enable SysTick interrupts */ + + putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT | + NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); + + /* And enable the timer interrupt */ + + up_enable_irq(NRF52_IRQ_SYSTICK); +} diff --git a/configs/Kconfig b/configs/Kconfig index 6a5ec5c394b..3a567d65b18 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -492,6 +492,14 @@ config ARCH_BOARD_NTOSD_DM320 STATUS: This port is code complete, verified, and included in the NuttX 0.2.1 release. +config ARCH_BOARD_NRF52_PCA10040 + bool "NRF52 PCA10040 eval board" + depends on ARCH_CHIP_NRF52 + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + ---help--- + PCA10040 Evaluation board + config ARCH_BOARD_LPC1766STK bool "Olimex LPC1766-STK board" depends on ARCH_CHIP_LPC1766 @@ -1664,6 +1672,7 @@ config ARCH_BOARD default "mirtoo" if ARCH_BOARD_MIRTOO default "moteino-mega" if ARCH_BOARD_MOTEINO_MEGA default "ne64badge" if ARCH_BOARD_NE64BADGE + default "nrf52-pca10040" if ARCH_BOARD_NRF52_PCA10040 default "ntosd-dm320" if ARCH_BOARD_NTOSD_DM320 default "nucleo-144" if ARCH_BOARD_NUCLEO_144 default "nucleo-f072rb" if ARCH_BOARD_NUCLEO_F072RB @@ -1955,6 +1964,9 @@ endif if ARCH_BOARD_NE64BADGE source "configs/ne64badge/Kconfig" endif +if ARCH_BOARD_NRF52_PCA10040 +source "configs/nrf52-pca10040/Kconfig" +endif if ARCH_BOARD_NTOSD_DM320 source "configs/ntosd-dm320/Kconfig" endif diff --git a/configs/README.txt b/configs/README.txt index e9ace0cf9bc..ec53cde7fa9 100644 --- a/configs/README.txt +++ b/configs/README.txt @@ -402,6 +402,10 @@ configs/ne64badge STATUS: Under development. The port is code-complete but has not yet been fully tested. +configs/nrf52-pca10040 + NuttX port to the NRF PCA10040 board from Nordic Semiconductor + featuring the NRF52832 MCU. + configs/ntosd-dm320 This port uses the Neuros OSD v1.0 Dev Board with a GNU arm-nuttx-elf toolchain*: see diff --git a/configs/nrf52-pca10040/Kconfig b/configs/nrf52-pca10040/Kconfig new file mode 100644 index 00000000000..6ad461321a3 --- /dev/null +++ b/configs/nrf52-pca10040/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_NRF52_PCA10040 + +endif diff --git a/configs/nrf52-pca10040/README.txt b/configs/nrf52-pca10040/README.txt new file mode 100644 index 00000000000..97cc24b2ffd --- /dev/null +++ b/configs/nrf52-pca10040/README.txt @@ -0,0 +1,112 @@ +README +====== + +README for NuttX port to the NRF PCA10040 board from Nordic Semiconductor +featuring the NRF52832 MCU. + +Contents +======== + + - PCA10040 development board + - Status + - LED and Pushbuttons + - Serial Console + - Configurations + - STATUS + +PCA10040 board +============== + + Memory Map + ---------- + + Block Start Length + Name Address + --------------------- ---------- ------ + FLASH 0x00000000 512K + RAM 0x20000000 64K + + Console + ------- + + The PCA10040 default console is the UART0. + +Status +====== + + This is the current status of the NRF52 port: + + - The basic OS test configuration and the basic NSH configurations + are present and fully verified. This includes: SYSTICK system time, + pin and GPIO configuration, and serial console support. + +LED and Pushbuttons +=================== + + LEDS + ---- + The PCA10040 has 4 user-controllable LEDs + + LED MCU + LED1 PIN-17 + LED2 PIN-18 + LED3 PIN-19 + LED4 PIN-20 + + A low output illuminates the LED. + + If CONFIG_ARCH_LEDS is defined, the LED will be controlled as follows + for NuttX debug functionality (where NC means "No Change"). + + TBD! + + If CONFIG_ARCH_LEDS is not defined, then the LEDs are completely under + control of the application. The following interfaces are then available + for application control of the LEDs: + + void board_userled_initialize(void); + void board_userled(int led, bool ledon); + void board_userled_all(uint8_t ledset); + + Pushbuttons + ----------- + To be provided + +Serial Console +============== + +The PCA10040 does not have RS-232 drivers or serial connectors on board. +UART0, is available on P4 as follows: + + -------- ----- + Signal PIN + -------- ----- + UART0-TX P0.24 + UART0-RX P0.23 + +Configurations +============== + +Each PCA10040 configuration is maintained in a sub-directory and can be selected +as follow: + + cd tools + ./configure.sh nrf52-pca10040/ + cd - + +Where is one of the following: + + nsh: + ---- + This configuration is the NuttShell (NSH) example at examples/nsh/. + + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configurations using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository. + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. diff --git a/configs/nrf52-pca10040/include/board.h b/configs/nrf52-pca10040/include/board.h new file mode 100644 index 00000000000..e82fdfc0788 --- /dev/null +++ b/configs/nrf52-pca10040/include/board.h @@ -0,0 +1,112 @@ +/**************************************************************************** + * configs/nrf52-pca10040/include/board.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef _CONFIGS_NRF52_PCA10040_INCLUDE_BOARD_H +#define _CONFIGS_NRF52_PCA10040_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#if defined(CONFIG_ARCH_IRQBUTTONS) && defined(CONFIG_NRF52_GPIO_IRQ) +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking ****************************************************************/ + +#define BOARD_SYSTICK_CLOCK (64000000) + +/* LED definitions *********************************************************/ +/* + * A low output illuminates the LED. + * + * LED index values for use with board_userled() + */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* If CONFIG_ARCH_LEDS is defined, the LED will be controlled as follows + * for NuttX debug functionality (where NC means "No Change"). + */ + /* LED */ +#define LED_STARTED 0 /* OFF */ +#define LED_HEAPALLOCATE 0 /* OFF */ +#define LED_IRQSENABLED 0 /* OFF */ +#define LED_STACKCREATED 1 /* ON */ +#define LED_INIRQ 2 /* NC */ +#define LED_SIGNAL 2 /* NC */ +#define LED_ASSERTION 2 /* NC */ +#define LED_PANIC 3 /* Flashing */ + +/* If CONFIG_ARCH_LEDS is not defined, then the LEDs are completely under + * control of the application. The following interfaces are then available + * for application control of the LEDs: + * + * void board_userled_initialize(void); + * void board_userled(int led, bool ledon); + * void board_userled_all(uint8_t ledset); + */ + +/* Button definitions *******************************************************/ +/* To be provided */ + +/* UART Pins ****************************************************************/ +/* + * The following definitions must be provided so that the NRF52 serial + * driver can set up the UART for the serial console properly. + */ + +#define BOARD_UART0_RX_PIN (GPIO_INPUT | GPIO_PIN23) +#define BOARD_UART0_TX_PIN (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PIN24) + +#endif /* _CONFIGS_NRF52_PCA10040_INCLUDE_BOARD_H */ diff --git a/configs/nrf52-pca10040/nsh/defconfig b/configs/nrf52-pca10040/nsh/defconfig new file mode 100644 index 00000000000..aaeea6ea734 --- /dev/null +++ b/configs/nrf52-pca10040/nsh/defconfig @@ -0,0 +1,42 @@ +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH_BOARD_NRF52_PCA10040=y +CONFIG_ARCH_BOARD="nrf52-pca10040" +CONFIG_ARCH_CHIP_NRF52=y +CONFIG_ARCH_CHIP_NRF52832=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_STDARG_H=y +CONFIG_ARCH="arm" +CONFIG_BOARD_LOOPSPERMSEC=5500 +CONFIG_EXAMPLES_NSH=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_MAX_TASKS=16 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_MM_REGIONS=2 +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NRF52_UART0=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_RAM_SIZE=65535 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_START_DAY=26 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2018 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_WDOG_INTRESERVE=0 diff --git a/configs/nrf52-pca10040/scripts/Make.defs b/configs/nrf52-pca10040/scripts/Make.defs new file mode 100644 index 00000000000..e9a5b047636 --- /dev/null +++ b/configs/nrf52-pca10040/scripts/Make.defs @@ -0,0 +1,116 @@ +############################################################################ +# configs/nrf52-pca10040/scripts/Make.defs +# +# Copyright (C) 2014, 2017, 2018 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = flash_config.ld + +# Setup for Windows vs Linux/Cygwin/OSX environments + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +STRIP = $(CROSSDEV)strip --strip-unneeded +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/nrf52-pca10040/scripts/flash_config.ld b/configs/nrf52-pca10040/scripts/flash_config.ld new file mode 100644 index 00000000000..288e3e417ad --- /dev/null +++ b/configs/nrf52-pca10040/scripts/flash_config.ld @@ -0,0 +1,119 @@ +/**************************************************************************** + * configs/nrf52-pca10040/scripts/flash_config.ld + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +MEMORY +{ + progmem (rx) : ORIGIN = 0x00000000, LENGTH = 512K + datamem (rwx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +OUTPUT_ARCH(arm) +ENTRY(__start) /* Treat __start as the anchor for dead code stripping */ +EXTERN(_vectors) /* Force the vectors to be included in the output */ +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > progmem + + .init_section : + { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > progmem + + .ARM.extab : + { + *(.ARM.extab*) + } > progmem + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : + { + *(.ARM.exidx*) + } > progmem + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > datamem AT > progmem + + /* BSS */ + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > datamem + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/nrf52-pca10040/src/.gitignore b/configs/nrf52-pca10040/src/.gitignore new file mode 100644 index 00000000000..726d936e1e3 --- /dev/null +++ b/configs/nrf52-pca10040/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/configs/nrf52-pca10040/src/Makefile b/configs/nrf52-pca10040/src/Makefile new file mode 100644 index 00000000000..16ac0283b36 --- /dev/null +++ b/configs/nrf52-pca10040/src/Makefile @@ -0,0 +1,51 @@ +############################################################################ +# configs/nrf52-pca10040/src/Makefile +# +# Copyright (C) 2018 Gregory Nutt. All rights reserved. +# Author: Janne Rosberg +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = nrf52_boot.c nrf52_bringup.c + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += nrf52_appinit.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += nrf52_autoleds.c +else +CSRCS += nrf52_userleds.c +endif + +include $(TOPDIR)/configs/Board.mk diff --git a/configs/nrf52-pca10040/src/nrf52-pca10040.h b/configs/nrf52-pca10040/src/nrf52-pca10040.h new file mode 100644 index 00000000000..61fccc69152 --- /dev/null +++ b/configs/nrf52-pca10040/src/nrf52-pca10040.h @@ -0,0 +1,109 @@ +/**************************************************************************** + * configs/nrf52-pca10040/src/lpc4357-evb.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef _CONFIGS_NRF52PCA10040_SRC_NRF52PCA10040_H +#define _CONFIGS_NRF52PCA10040_SRC_NRF52PCA10040_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "nrf52_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LED definitions **********************************************************/ +/* The PCA10040 has 4 user-controllable LEDs + * + * ---- ------- ------------- + * LED SIGNAL MCU + * ---- ------- ------------- + * LED1 GPIO 17 + * LED2 GPIO 18 + * LED3 GPIO 19 + * LED4 GPIO 20 + * ---- ------- ------------- + * + * A low output illuminates the LED. + * + */ + +/* Definitions to configure LED GPIO as outputs */ + +#define GPIO_LED1 (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PIN17) +#define GPIO_LED2 (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PIN18) +#define GPIO_LED3 (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PIN19) +#define GPIO_LED4 (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PIN20) + +/* Button definitions *******************************************************/ +/* to be provided */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int nrf52_bringup(void); + +#endif /* __ASSEMBLY__ */ +#endif /* _CONFIGS_NRF52PCA10040_SRC_NRF52PCA10040_H */ diff --git a/configs/nrf52-pca10040/src/nrf52_appinit.c b/configs/nrf52-pca10040/src/nrf52_appinit.c new file mode 100644 index 00000000000..503040655d0 --- /dev/null +++ b/configs/nrf52-pca10040/src/nrf52_appinit.c @@ -0,0 +1,89 @@ +/**************************************************************************** + * config/nrf52-pca10040/src/nrf52_appinit.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "nrf52-pca10040.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform architecture specific initialization + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_INITIALIZE + /* Board initialization already performed by board_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return nrf52_bringup(); +#endif +} diff --git a/configs/nrf52-pca10040/src/nrf52_autoleds.c b/configs/nrf52-pca10040/src/nrf52_autoleds.c new file mode 100644 index 00000000000..3ad096d41ab --- /dev/null +++ b/configs/nrf52-pca10040/src/nrf52_autoleds.c @@ -0,0 +1,162 @@ +/**************************************************************************** + * configs/nrf52-pca10040/src/lpc43_autoleds.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The PCA10040 has 4 user-controllable LEDs: + * + * LED MCU + * LED1 PIN-17 + * LED2 PIN-18 + * LED3 PIN-19 + * LED4 PIN-20 + * + * A low output illuminates the LED. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" + +#include "nrf52-pca10040.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_dumppins + ****************************************************************************/ + +#ifdef LED_VERBOSE +static void led_dumppins(FAR const char *msg) +{ + nrf52_pin_dump(PINCONFIG_LED, msg); + nrf52_gpio_dump(GPIO_LED, msg); +} +#else +# define led_dumppins(m) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED pin as a GPIO outputs */ + + led_dumppins("board_autoled_initialize() Entry)"); + + nrf52_gpio_config(GPIO_LED1); + nrf52_gpio_config(GPIO_LED2); + nrf52_gpio_config(GPIO_LED3); + nrf52_gpio_config(GPIO_LED4); + + led_dumppins("board_autoled_initialize() Exit"); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + default: + case 0: + nrf52_gpio_write(GPIO_LED1, 0); + break; + + case 1: + nrf52_gpio_write(GPIO_LED2, 0); + break; + + case 2: + nrf52_gpio_write(GPIO_LED3, 0); + break; + + case 3: + nrf52_gpio_write(GPIO_LED4, 0); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + default: + case 0: + nrf52_gpio_write(GPIO_LED1, 1); + break; + + case 1: + nrf52_gpio_write(GPIO_LED2, 1); + break; + + case 2: + nrf52_gpio_write(GPIO_LED3, 1); + break; + + case 3: + nrf52_gpio_write(GPIO_LED4, 1); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/nrf52-pca10040/src/nrf52_boot.c b/configs/nrf52-pca10040/src/nrf52_boot.c new file mode 100644 index 00000000000..b6cd58b22d6 --- /dev/null +++ b/configs/nrf52-pca10040/src/nrf52_boot.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * configs/nrf52-pca10040/src/lpc43_boot.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" + +#include "nrf52-pca10040.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_board_initialize + * + * Description: + * All NRF52xxx architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void nrf52_board_initialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_initialize + * + * Description: + * If CONFIG_BOARD_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_initialize(). board_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_INITIALIZE +void board_initialize(void) +{ + /* Perform board-specific initialization */ + + (void)nrf52_bringup(); +} +#endif diff --git a/configs/nrf52-pca10040/src/nrf52_bringup.c b/configs/nrf52-pca10040/src/nrf52_bringup.c new file mode 100644 index 00000000000..9e6fadcef57 --- /dev/null +++ b/configs/nrf52-pca10040/src/nrf52_bringup.c @@ -0,0 +1,64 @@ +/**************************************************************************** + * config/nrf52-pca10040/src/nrf53_bringup.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_INITIALIZE=y : + * Called from board_initialize(). + * + * CONFIG_BOARD_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int nrf52_bringup(void) +{ + return OK; +} diff --git a/configs/nrf52-pca10040/src/nrf52_userleds.c b/configs/nrf52-pca10040/src/nrf52_userleds.c new file mode 100644 index 00000000000..6ac5db8f3f3 --- /dev/null +++ b/configs/nrf52-pca10040/src/nrf52_userleds.c @@ -0,0 +1,136 @@ +/**************************************************************************** + * configs/nrf52-pca10040/src/nrf52_userleds.c + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Janne Rosberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" + +#include "nrf52-pca10040.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* LED definitions **********************************************************/ +/* + * If CONFIG_ARCH_LEDS is not defined, then the LEDs are completely under + * control of the application. The following interfaces are then available + * for application control of the LEDs: + * + * void board_userled_initialize(void); + * void board_userled(int led, bool ledon); + * void board_userled_all(uint8_t ledset); + */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_dumppins + ****************************************************************************/ + +#ifdef LED_VERBOSE +static void led_dumppins(FAR const char *msg) +{ + nrf52_pin_dump(PINCONFIG_LED, msg); + nrf52_gpio_dump(GPIO_LED, msg); +} +#else +# define led_dumppins(m) +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ + /* Configure LED pin as a GPIO outputs */ + + led_dumppins("board_userled_initialize() Entry)"); + + /* Configure GPIO as an outputs */ + + nrf52_gpio_config(GPIO_LED1); + nrf52_gpio_config(GPIO_LED2); + nrf52_gpio_config(GPIO_LED3); + nrf52_gpio_config(GPIO_LED4); + + led_dumppins("board_userled_initialize() Exit"); +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if (led == BOARD_LED1) + { + nrf52_gpio_write(GPIO_LED1, !ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ + nrf52_gpio_write(GPIO_LED1, (ledset & BOARD_LED1_BIT) == 0); + nrf52_gpio_write(GPIO_LED2, (ledset & BOARD_LED2_BIT) == 0); + nrf52_gpio_write(GPIO_LED3, (ledset & BOARD_LED3_BIT) == 0); + nrf52_gpio_write(GPIO_LED4, (ledset & BOARD_LED4_BIT) == 0); +} + +#endif /* !CONFIG_ARCH_LEDS */