diff --git a/arch/mips/src/mips32/cp0.h b/arch/mips/src/mips32/cp0.h deleted file mode 100755 index 177f3a84592..00000000000 --- a/arch/mips/src/mips32/cp0.h +++ /dev/null @@ -1,219 +0,0 @@ -/**************************************************************************** - * arch/mips/src/mips32/cp0.h - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_MIPS_SRC_MIPS32_CP0_H -#define __ARCH_MIPS_SRC_MIPS32_CP0_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-Processor Definitions - ****************************************************************************/ -/* CP0 Registers ************************************************************/ - -/* Register Number: 0 Sel: 0 Name: Index - * Function: Index into the TLB array - */ - -/* Register Number: 1 Sel: 0 Name: Random - * Function: Randomly generated index into the TLB array - */ - -/* Register Number: 2 Sel: 0 Name: EntryLo0 - * Function: Low-order portion of the TLB entry foreven-numbered virtual - * pages - */ - -/* Register Number: 3 Sel: 0 Name: EntryLo1 - * Function: Low-order portion of the TLB entry forodd-numbered virtual - * pages - */ - -/* Register Number: 4 Sel: 0 Name: Context - * Function: Pointer to page table entry in memory - */ - -/* Register Number: 5 Sel: 0 Name: PageMask - * Function: Control for variable page size in TLB entries - */ - -/* Register Number: 6 Sel: 0 Name: Wired - * Function: Controls the number of fixed (“wired”) TLB entries - */ - -/* Register Number: 7 Sel: all (Reserved for future extensions) -/* Register Number: 8 Sel: 0 Name: BadVAddr - * Function: Reports the address for the most recent address-related - * exception - */ - -/* Register Number: 9 Sel: 0 Name: Count - * Function: Processor cycle count - */ - -/* Register Number: 9 Sel: 6-7 (Available for implementation dependent user) */ - -/* Register Number: 10 Sel: 0 Name: EntryHi - * Function: High-order portion of the TLB entry - */ - -/* Register Number: 11 Sel: 0 Name: Compare - * Function: Timer interrupt control - */ - -/* Register Number: 11 Sel: 6-7 (Available for implementation dependent user) */ - -/* Register Number: 12 Sel: 0 Name: Status - * Function: Processor status and control - */ - -/* Register Number: 13 Sel: 0 Name: Cause - * Function: Cause of last general exception - */ - -/* Register Number: 14 Sel: 0 Name: EPC - * Function: Program counter at last exception - */ - -/* Register Number: 15 Sel: 0 Name: PRId - * Function: Processor identification and revision - */ - -/* Register Number: 16 Sel: 0 Name: Config - * Function: Configuration register - */ - -/* Register Number: 16 Sel: 1 Name: Config1 - * Function: Configuration register 1 - */ - -/* Register Number: 16 Sel: 2 Name: Config2 - * Function: Configuration register 2 - */ - -/* Register Number: 16 Sel: 3 Name: Config3 - * Function: Configuration register 3 - */ - -/* Register Number: 16 Sel: 6-7 (Available for implementation dependent use) */ - -/* Register Number: 17 Sel: 0 Name: LLAddr - * Function: Load linked address - */ - -/* Register Number: 18 Sel: 0-n Name: WatchLo - * Function: Watchpoint addr - */ - -/* Register Number: 19 Sel: 0-n Name: WatchHi - * Function: Watchpoint control - */ - -/* Register Number: 20 Sel: 0 Name: XContext - * Function: in 64-bit implementations - */ - -/* Register Number: 21 Sel: all (Reserved for future extensions) */ - -/* Register Number: 22 Sel: all Available for implementation dependent use) */ - -/* Register Number: 23 Sel: 0 Name: Debug - * Function: EJTAG Debug register - */ - -/* Register Number: 24 Sel: 0 Name: DEPC - * Function: Program counter at last EJTAG debug exception - */ - -/* Register Number: 25 Sel: 0-n Name: PerfCnt - * Function: Performance counter interface - */ - -/* Register Number: 26 Sel: 0 Name: ErrCtl - * Function: Parity/ECC error control and status - */ - -/* Register Number: 27 Sel: 0-3 Name: CacheErr - * Function: Cache parity error control and status - */ - -/* Register Number: 28 Sel: 0 Name: TagLo - * Function: Low-order portion of cache tag interface - */ - -/* Register Number: 29 Sel: 0 Name: TagHi - * Function: High-order portion of cache tag interface - */ - -/* Register Number: 30 Sel: 0 Name: ErrorEPC - * Function: Program counter at last error - */ - -/* Register Number: 31 Sel: 0 Name: DESAVE - * Function: EJTAG debug exception save register - */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_MIPS_SRC_MIPS32_CP0_H */ diff --git a/arch/mips/src/mips32/mips32-cp0.h b/arch/mips/src/mips32/mips32-cp0.h new file mode 100755 index 00000000000..1cf844b886b --- /dev/null +++ b/arch/mips/src/mips32/mips32-cp0.h @@ -0,0 +1,535 @@ +/******************************************************************************************** + * arch/mips/src/mips32/mips32-cp0.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_MIPS32_MIPS32_CP0_H +#define __ARCH_MIPS_SRC_MIPS32_MIPS32_CP0_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +/******************************************************************************************** + * Pre-Processor Definitions + ********************************************************************************************/ +/* CP0 Registers ****************************************************************************/ + +/* Register Number: 0 Sel: 0 Name: Index + * Function: Index into the TLB array + * Compliance Level: Required for TLB-based MMUs; Optional otherwise. + */ + +#define CP0_INDEX_SHIFT (0) /* Bits 0-(n-1): TLB Index */ +#define CP0_INDEX_MASK (0x7fffffff) +#define CP0_INDEX_P (1 << 31) /* Bit 31: Probe failure */ + +/* Register Number: 1 Sel: 0 Name: Random + * Function: Randomly generated index into the TLB array + * Compliance Level: Required for TLB-based MMUs; Optional otherwise. + * + * This is a 32-bit register containing a random TLB index. The valid width is some fixed + * number, 'n', but the upper bits are padded so that no fields need be defined for this + * register. + */ + +/* Register Number: 2 Sel: 0 Name: EntryLo0 + * Function: Low-order portion of the TLB entry for even-numbered virtual pages + * Compliance Level: EntryLo0 is Required for a TLB-based MMU; Optional + * otherwise. + * + * Register Number: 3 Sel: 0 Name: EntryLo1 + * Function: Low-order portion of the TLB entry for odd-numbered virtual pages + * Compliance Level: EntryLo1 is Required for a TLB-based MMU; Optional otherwise. + */ + +#define CP0_ENTRYLO_G (1 << 0) /* Bit 0: Global bit */ +#define CP0_ENTRYLO_V (1 << 1) /* Bit 1: Valild bit */ +#define CP0_ENTRYLO_D (1 << 2) /* Bit 2: Dirty bit */ +#define CP0_ENTRYLO_C_SHIFT (3) /* Bits 3-5: Coherency attribute */ +#define CP0_ENTRYLO_C_MASK (7 << CP0_ENTRYLO_CSHIFT) +# define CP0_ENTRYLO_UNCACHED (2 << CP0_ENTRYLO_CSHIFT) +# define CP0_ENTRYLO_CACHEABLE (3 << CP0_ENTRYLO_CSHIFT) +#define CP0_ENTRYLO_PFN_SHIFT (6) /* Bits 6-29: Page frame number */ +#define CP0_ENTRYLO_PFN_MASK (0x00ffffff << CP0_ENTRYLO_CSHIFT) + +/* Register Number: 4 Sel: 0 Name: Context + * Function: Pointer to page table entry in memory + * Compliance Level: Required for TLB-based MMUs; Optional otherwise. + */ + +#define CP0_CONTEXT_BADVPN2_SHIFT (4) /* Bits 4-22: Virtual address that cause an excpetion */ +#define CP0_CONTEXT_BADVPN2_MASK (0x0007ffff << CP0_CONTEXT_BADVPN2_SHIFT) +#define CP0_CONTEXT_PTEBASE_SHIFT (23) /* Bits 23-31: Page table base address */ +#define CP0_CONTEXT_PTEBASE_MASK (0x000001ff << CP0_CONTEXT_PTEBASE_SHIFT) + +/* Register Number: 5 Sel: 0 Name: PageMask + * Function: Control for variable page size in TLB entries. + * Compliance Level: Required for TLB-based MMUs; Optional otherwise. + */ + +#define CP0_PAGEMASK_SHIFT (13) /* Bits 13-28: Page mask */ +#define CP0_PAGEMASK_MASK (0xffff << CP0_PAGEMASK_SHIFT) +# define CP0_PAGEMASK_4KB (0x0000 << CP0_PAGEMASK_SHIFT) +# define CP0_PAGEMASK_16KB (0x0003 << CP0_PAGEMASK_SHIFT) +# define CP0_PAGEMASK_64KB (0x000f << CP0_PAGEMASK_SHIFT) +# define CP0_PAGEMASK_256KB (0x003f << CP0_PAGEMASK_SHIFT) +# define CP0_PAGEMASK_1MB (0x00ff << CP0_PAGEMASK_SHIFT) +# define CP0_PAGEMASK_4MB (0x03ff << CP0_PAGEMASK_SHIFT) +# define CP0_PAGEMASK_16MB (0x0fff << CP0_PAGEMASK_SHIFT) +# define CP0_PAGEMASK_64MB (0x3fff << CP0_PAGEMASK_SHIFT) +# define CP0_PAGEMASK_256MB (0xffff << CP0_PAGEMASK_SHIFT) + +/* Register Number: 6 Sel: 0 Name: Wired + * Function: Controls the number of fixed (“wired”) TLB entries + * Compliance Level: Required for TLB-based MMUs; Optional otherwise. + * + * This is a 32-bit register containing the TLB wired boundary. The valid width is some + * fixed number, 'n', but the upper bits are padded so that no fields need be defined for + * this register. + * + * Register Number: 7 Sel: all (Reserved for future extensions) + * + * Register Number: 8 Sel: 0 Name: BadVAddr + * Function: Reports the address for the most recent address-related exception + * Compliance Level: Required. + * + * This register contains a 32-bit address value; No fields need be defined for this + * register. + * + * Register Number: 9 Sel: 0 Name: Count + * Function: Processor cycle count + * Compliance Level: Required. + * + * This register contains a 32-bit count value; No fields need be defined for this + * register. + * + * Register Number: 9 Sel: 6-7 (Available for implementation dependent user) + */ + +/* Register Number: 10 Sel: 0 Name: EntryHi + * Function: High-order portion of the TLB entry + * Compliance Level: Required for TLB-based MMU; Optional otherwise. + */ + +#define CP0_ENTRYHI_ASID_SHIFT (0) /* Bits 0-7: Address space identifier */ +#define CP0_ENTRYHI_ASID_MASK (0xff << CP0_ENTRYHI_ASID_SHIFT) +#define CP0_ENTRYHI_VPN2_SHIFT (13) /* Bits 13-31: Virtual address */ +#define CP0_ENTRYHI_VPN2_MASK (0x0007ffff << CP0_ENTRYHI_VPN2_SHIFT) + +/* Register Number: 11 Sel: 0 Name: Compare + * Function: Timer interrupt control + * Compliance Level: Required. + * + * This register contains a 32-bit compare value; No fields need be defined for this + * register. + * + * Register Number: 11 Sel: 6-7 (Available for implementation dependent user) + */ + +/* Register Number: 12 Sel: 0 Name: Status + * Function: Processor status and control + * Compliance Level: Required. + */ + +#define CP0_STATUS_IE (1 << 0) /* Bit 0: Interrupt Enable */ +#define CP0_STATUS_EXL (1 << 1) /* Bit 1: Exception Level */ +#define CP0_STATUS_ERL (1 << 2) /* Bit 2: Error Level */ +#define CP0_STATUS_KSU_SHIFT (3) /* Bits 3-4: Operating mode (with supervisor mode) */ +#define CP0_STATUS_KSU_MASK (3 << CP0_STATUS_KSU_SHIFT) +# define CP0_STATUS_KSU_KERNEL (0 << CP0_STATUS_KSU_SHIFT) +# define CP0_STATUS_KSU_SUPER (1 << CP0_STATUS_KSU_SHIFT) +# define CP0_STATUS_KSU_USER (2 << CP0_STATUS_KSU_SHIFT) +#define CP0_STATUS_UM (1 << 4) /* Bit 4: Operating mode == USER (No supervisor mode) */ +#define CP0_STATUS_UX (1 << 5) /* Bit 5: Enables 64-bit user address space (Not MIPS32) */ +#define CP0_STATUS_SX (1 << 6) /* Bit 6: Enables 64-bit supervisor address space (Not MIPS32) */ +#define CP0_STATUS_KX (1 << 7) /* Bit 7: Enables 64-bit kernel address space (Not MIPS32) */ +#define CP0_STATUS_IM_SHIFT (8) /* Bits 8-15: Interrupt Mask */ +#define CP0_STATUS_IM_MASK (0xff << CP0_STATUS_IM_SHIFT) +# define CP0_STATUS_IM0 (0x01 << CP0_STATUS_IM_SHIFT) +# define CP0_STATUS_IM1 (0x02 << CP0_STATUS_IM_SHIFT) +# define CP0_STATUS_IM2 (0x04 << CP0_STATUS_IM_SHIFT) +# define CP0_STATUS_IM3 (0x08 << CP0_STATUS_IM_SHIFT) +# define CP0_STATUS_IM4 (0x10 << CP0_STATUS_IM_SHIFT) +# define CP0_STATUS_IM5 (0x20 << CP0_STATUS_IM_SHIFT) +# define CP0_STATUS_IM6 (0x40 << CP0_STATUS_IM_SHIFT) +# define CP0_STATUS_IM7 (0x80 << CP0_STATUS_IM_SHIFT) +#define CP0_STATUS_IMPL_SHIFT (16) /* Bits 16-17: Interrupt Mask */ +#define CP0_STATUS_IMPL_MASK (3 << CP0_STATUS_IMPL_SHIFT) +#define CP0_STATUS_NMI (1 << 19) /* Bit 19: Reset exception due to an NMI */ +#define CP0_STATUS_SR (1 << 20) /* Bit 20: Reset exception due to a Soft Reset */ +#define CP0_STATUS_TS (1 << 21) /* Bit 21: TLB detected match on multiple entries */ +#define CP0_STATUS_BEV (1 << 22) /* Bit 22: Location of exception vectors 1->Bootstrap */ +#define CP0_STATUS_PX (1 << 23) /* Bit 23: Enables 64-bit operations (Not MIPS32) */ +#define CP0_STATUS_MX (1 << 24) /* Bit 24: Enables MDMX™ (Not MIPS32) */ +#define CP0_STATUS_RE (1 << 25) /* Bit 25: Enable reverse-endian memory in user mode */ +#define CP0_STATUS_FR (1 << 26) /* Bit 26: Controls the floating point register mode (Not MIPS32) */ +#define CP0_STATUS_RP (1 << 27) /* Bit 27: Enables reduced power mode */ +#define CP0_STATUS_CU0 (1 << 28) /* Bit 28: Controls access to coprocessor 0 */ +#define CP0_STATUS_CU1 (1 << 29) /* Bit 29: Controls access to coprocessor 1 */ +#define CP0_STATUS_CU2 (1 << 30) /* Bit 30: Controls access to coprocessor 2 */ +#define CP0_STATUS_CU3 (1 << 31) /* Bit 31: Controls access to coprocessor 3 */ + +/* Register Number: 13 Sel: 0 Name: Cause + * Function: Cause of last general exception + * Compliance Level: Required. + */ + +#define CP0_CAUSE_EXCCODE_SHIFT (2) /* Bits 2-6: Exception code */ +#define CP0_CAUSE_EXCCODE_MASK (31 << CP0_CAUSE_EXCCODE_SHIFT) +# define CP0_CAUSE_EXCCODE_INT (0 << CP0_CAUSE_EXCCODE_SHIFT) /* Interrupt */ +# define CP0_CAUSE_EXCCODE_TLBL (2 << CP0_CAUSE_EXCCODE_SHIFT) /* TLB exception (load or instruction fetch) */ +# define CP0_CAUSE_EXCCODE_TLBS (3 << CP0_CAUSE_EXCCODE_SHIFT) /* TLB exception (store) */ +# define CP0_CAUSE_EXCCODE_ADEL (4 << CP0_CAUSE_EXCCODE_SHIFT) /* Address error exception (load or instruction fetch) */ +# define CP0_CAUSE_EXCCODE_ADES (5 << CP0_CAUSE_EXCCODE_SHIFT) /* Address error exception (store) */ +# define CP0_CAUSE_EXCCODE_IBE (6 << CP0_CAUSE_EXCCODE_SHIFT) /* Bus error exception (instruction fetch) */ +# define CP0_CAUSE_EXCCODE_DBE (7 << CP0_CAUSE_EXCCODE_SHIFT) /* Bus error exception (data reference: load or store) */ +# define CP0_CAUSE_EXCCODE_SYS (8 << CP0_CAUSE_EXCCODE_SHIFT) /* Syscall exception */ +# define CP0_CAUSE_EXCCODE_BP (9 << CP0_CAUSE_EXCCODE_SHIFT) /* Breakpoint exception */ +# define CP0_CAUSE_EXCCODE_RI (10 << CP0_CAUSE_EXCCODE_SHIFT) /* Reserved instruction exception */ +# define CP0_CAUSE_EXCCODE_CPU (11 << CP0_CAUSE_EXCCODE_SHIFT) /* Coprocessor Unusable exception */ +# define CP0_CAUSE_EXCCODE_OV (12 << CP0_CAUSE_EXCCODE_SHIFT) /* Arithmetic Overflow exception */ +# define CP0_CAUSE_EXCCODE_TR (13 << CP0_CAUSE_EXCCODE_SHIFT) /* Trap exception */ +# define CP0_CAUSE_EXCCODE_FPE (15 << CP0_CAUSE_EXCCODE_SHIFT) /* Floating point exception */ +# define CP0_CAUSE_EXCCODE_C2E (18 << CP0_CAUSE_EXCCODE_SHIFT) /* Precise Coprocessor 2 exceptions */ +# define CP0_CAUSE_EXCCODE_MDMX (22 << CP0_CAUSE_EXCCODE_SHIFT) /* MDMX Unusable (MIPS64) */ +# define CP0_CAUSE_EXCCODE_WATCH (23 << CP0_CAUSE_EXCCODE_SHIFT) /* WatchHi/WatchLo address */ +# define CP0_CAUSE_EXCCODE_MCHECK (24 << CP0_CAUSE_EXCCODE_SHIFT) /* Machine check */ +# define CP0_CAUSE_EXCCODE_CACHEERR (30 << CP0_CAUSE_EXCCODE_SHIFT) /* Cache error */ +#define CP0_CAUSE_IP0 (1 << 8) /* Bit 8: Controls request for software interrupt 0 */ +#define CP0_CAUSE_IP1 (1 << 9) /* Bit 9: Controls request for software interrupt 1 */ +#define CP0_CAUSE_IP_SHIFT (10) /* Bits 10-15: Pending external interrupts */ +#define CP0_CAUSE_IP_MASK (0x3f << CP0_CAUSE_IP_SHIFT) +# define CP0_CAUSE_IP2 (0x10 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 0 */ +# define CP0_CAUSE_IP3 (0x11 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 1 */ +# define CP0_CAUSE_IP4 (0x12 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 2 */ +# define CP0_CAUSE_IP5 (0x13 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 3 */ +# define CP0_CAUSE_IP6 (0x14 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 4 */ +# define CP0_CAUSE_IP7 (0x15 << CP0_CAUSE_IP_SHIFT) /* Hardware interrupt 5, timer or performance counter interrupt */ +#define CP0_CAUSE_WP (1 << 22 Watch exception was deferred +#define CP0_CAUSE_IV (1 << 23) /* Bit 23: Interrupt exception uses special interrupt vector */ +#define CP0_CAUSE_CE_SHIFT (28) /* Bits 28-29: Coprocessor unit number fo Coprocessor Unusable exception */ +#define CP0_CAUSE_CE_MASK (3 << CP0_CAUSE_CE_SHIFT) +#define CP0_CAUSE_BD (1 << 31) /* Bit 31: Last exception occurred in a branch delay slot */ + +/* Register Number: 14 Sel: 0 Name: EPC + * Function: Program counter at last exception + * Compliance Level: Required. + * + * This register contains a 32-bit address value; No fields need be defined for this + * register. + */ + +/* Register Number: 15 Sel: 0 Name: PRId + * Function: Processor identification and revision + * Compliance Level: Required. + */ + +#define CP0_PRID_REV_SHIFT (0) /* Bits 0-7: Revision number of the processor */ +#define CP0_PRID_REV_MASK (0xff << CP0_PRID_REV_SHIFT) +#define CP0_PRID_PROCID_SHIFT (8) /* Bits 8-15: Type of processor */ +#define CP0_PRID_PROCID_MASK (0xff << CP0_PRID_PROCID_SHIFT) +#define CP0_PRID_COMPANY_SHIFT (16) /* Bits 16-23: Company ID */ +#define CP0_PRID_COMPANY_MASK (0xff << CP0_PRID_COMPANY_SHIFT) +#define CP0_PRID_OPTIONS_SHIFT (24) /* Bits 24-31: Company-dependent options */ +#define CP0_PRID_OPTIONS_MASK (0xff << CP0_PRID_OPTIONS_SHIFT) + +/* Register Number: 16 Sel: 0 Name: Config + * Function: Configuration register + * Compliance Level: Required. + */ + +#define CP0_CONFIG_K0_SHIFT (0) /* Bits 0-2: KSEG0 coherency algorithm */ +#define CP0_CONFIG_K0_MASK (7 << CP0_CONFIG_K0_SHIFT) +# define CP0_CONFIG_K0_UNCACHED (2 << CP0_CONFIG_K0_SHIFT) +# define CP0_CONFIG_K0_CACHEABLE (3 << CP0_CONFIG_K0_SHIFT) +#define CP0_CONFIG_MT_SHIFT (7) /* Bits 7-9: MMU Type */ +#define CP0_CONFIG_MT_MASK (7 << CP0_CONFIG_MT_SHIFT) +# define CP0_CONFIG_MT_NONE (0 << CP0_CONFIG_MT_SHIFT) /* None */ +# define CP0_CONFIG_MT_TLB (1 << CP0_CONFIG_MT_SHIFT) /* Standard TLB */ +# define CP0_CONFIG_MT_BAT (2 << CP0_CONFIG_MT_SHIFT) /* Standard BAT */ +# define CP0_CONFIG_MT_FIXED (3 << CP0_CONFIG_MT_SHIFT) /* Standard fixed mapping */ +#define CP0_CONFIG_AR_SHIFT (10) /* Bits 10-12: Architecture revision level */ +#define CP0_CONFIG_AR_MASK (7 << CP0_CONFIG_AR_SHIFT) +# define CP0_CONFIG_AR_REV1 (0 << CP0_CONFIG_AR_SHIFT) +# define CP0_CONFIG_AR_REV2 (1 << CP0_CONFIG_AR_SHIFT) +#define CP0_CONFIG_AT_SHIFT (13) /* Bits 13-14: Architecture type implemented by the processor */ +#define CP0_CONFIG_AT_MASK (3 << CP0_CONFIG_AT_SHIFT) +# define CP0_CONFIG_AT_MIPS32 (0 << CP0_CONFIG_AT_SHIFT) /* MIPS32 */ +# define CP0_CONFIG_AT_MIPS64CMP (0 << CP0_CONFIG_AT_SHIFT) /* MIPS64 with 32-bit compatibility segments */ +# define CP0_CONFIG_AT_MIPS64 (1 << CP0_CONFIG_AT_SHIFT) /* MIPS64 with access to all address segments */ +#define CP0_CONFIG_BE (1 << 15) /* Bit 15: Processor is running in big-endian mode */ +#define CP0_CONFIG_IMPL_SHIFT (16) /* Bits 16-30: Implementation dependent */ +#define CP0_CONFIG_IMPL_MASK (0x7fff << CP0_CONFIG_IMPL_SHIFT) +#define CP0_CONFIG_M (1 << 31) /* Bit 31: Config1 register is implemented at select=1 */ + +/* Register Number: 16 Sel: 1 Name: Config1 + * Function: Configuration register 1 + * Compliance Level: Required. + */ + +#define CP0_CONFIG1_FP (1 << 0 FPU implemented +#define CP0_CONFIG1_EP (1 << 1 EJTAG implemented +#define CP0_CONFIG1_CA (1 << 2 Code compression (MIPS16) implemented +#define CP0_CONFIG1_WR (1 << 3 Watch registers implemented +#define CP0_CONFIG1_PC (1 << 4 Performance Counter registers implemented +#define CP0_CONFIG1_MD (1 << 5 MDMX ASE implemented (MIPS64) +#define CP0_CONFIG1_C2 (1 << 6 Coprocessor 2 implemented +#define CP0_CONFIG1_DA_SHIFT (7) /* Bits 7-9: Dcache associativity */ +#define CP0_CONFIG1_DA_MASK (7 << CP0_CONFIG1_DA_SHIFT) +# define CP0_CONFIG1_DA_DIRECT (0 << CP0_CONFIG1_DA_SHIFT) /* Direct mapped */ +# define CP0_CONFIG1_DA_2WAY (1 << CP0_CONFIG1_DA_SHIFT) /* 2-way */ +# define CP0_CONFIG1_DA_3WAY (2 << CP0_CONFIG1_DA_SHIFT) /* 3-way */ +# define CP0_CONFIG1_DA_4WAY (3 << CP0_CONFIG1_DA_SHIFT) /* 4-way */ +# define CP0_CONFIG1_DA_5WAY (4 << CP0_CONFIG1_DA_SHIFT) /* 5-way */ +# define CP0_CONFIG1_DA_6WAY (5 << CP0_CONFIG1_DA_SHIFT) /* 6-way */ +# define CP0_CONFIG1_DA_7WAY (6 << CP0_CONFIG1_DA_SHIFT) /* 7-way */ +# define CP0_CONFIG1_DA_8WAY (7 << CP0_CONFIG1_DA_SHIFT) /* 8-way */ +#define CP0_CONFIG1_DL_SHIFT (10) /* Bits 10-12: Dcache line size */ +#define CP0_CONFIG1_DL_MASK (7 << CP0_CONFIG1_DL_SHIFT) +# define CP0_CONFIG1_DL_NONE (0 << CP0_CONFIG1_DL_SHIFT) /* No Dcache present */ +# define CP0_CONFIG1_DL_4BYTES (1 << CP0_CONFIG1_DL_SHIFT) /* 4 bytes */ +# define CP0_CONFIG1_DL_8BYTES (2 << CP0_CONFIG1_DL_SHIFT) /* 8 bytes */ +# define CP0_CONFIG1_DL_16BYTES (3 << CP0_CONFIG1_DL_SHIFT) /* 16 bytes */ +# define CP0_CONFIG1_DL_32BYTES (4 << CP0_CONFIG1_DL_SHIFT) /* 32 bytes */ +# define CP0_CONFIG1_DL_64BYTES (5 << CP0_CONFIG1_DL_SHIFT) /* 64 bytes */ +# define CP0_CONFIG1_DL_128BYTES (6 << CP0_CONFIG1_DL_SHIFT) /* 128 bytes */ +#define CP0_CONFIG1_DS_SHIFT (13) /* Bits 13-15: Dcache sets per way */ +#define CP0_CONFIG1_DS_MASK (7 << CP0_CONFIG1_DS_SHIFT) +# define CP0_CONFIG1_DS_64SETS (0 << CP0_CONFIG1_DS_SHIFT) +# define CP0_CONFIG1_DS_128SETS (1 << CP0_CONFIG1_DS_SHIFT) +# define CP0_CONFIG1_DS_256SETS (2 << CP0_CONFIG1_DS_SHIFT) +# define CP0_CONFIG1_DS_512SETS (3 << CP0_CONFIG1_DS_SHIFT) +# define CP0_CONFIG1_DS_1024SETS (4 << CP0_CONFIG1_DS_SHIFT) +# define CP0_CONFIG1_DS_2048SETS (5 << CP0_CONFIG1_DS_SHIFT) +# define CP0_CONFIG1_DS_4096SETS (6 << CP0_CONFIG1_DS_SHIFT) +#define CP0_CONFIG1_IA_SHIFT (16) /* Bits 16-18: Icache associativity */ +#define CP0_CONFIG1_IA_MASK (7 << CP0_CONFIG1_IA_SHIFT) +# define CP0_CONFIG1_IA_DIRECT (0 << CP0_CONFIG1_IA_SHIFT) /* Direct mapped */ +# define CP0_CONFIG1_IA_2WAY (1 << CP0_CONFIG1_IA_SHIFT) /* 2-way */ +# define CP0_CONFIG1_IA_3WAY (2 << CP0_CONFIG1_IA_SHIFT) /* 3-way */ +# define CP0_CONFIG1_IA_4WAY (3 << CP0_CONFIG1_IA_SHIFT) /* 4-way */ +# define CP0_CONFIG1_IA_5WAY (4 << CP0_CONFIG1_IA_SHIFT) /* 5-way */ +# define CP0_CONFIG1_IA_6WAY (5 << CP0_CONFIG1_IA_SHIFT) /* 6-way */ +# define CP0_CONFIG1_IA_7WAY (6 << CP0_CONFIG1_IA_SHIFT) /* 7-way */ +# define CP0_CONFIG1_IA_8WAY (7 << CP0_CONFIG1_IA_SHIFT) /* 8-way */ +#define CP0_CONFIG1_IL_SHIFT (19) /* Bits 19-21: Icache line size */ +#define CP0_CONFIG1_IL_MASK (7 << CP0_CONFIG1_IL_SHIFT) +# define CP0_CONFIG1_IL_NONE (0 << CP0_CONFIG1_IL_SHIFT) /* No Dcache present */ +# define CP0_CONFIG1_IL_4BYTES (1 << CP0_CONFIG1_IL_SHIFT) /* 4 bytes */ +# define CP0_CONFIG1_IL_8BYTES (2 << CP0_CONFIG1_IL_SHIFT) /* 8 bytes */ +# define CP0_CONFIG1_IL_16BYTES (3 << CP0_CONFIG1_IL_SHIFT) /* 16 bytes */ +# define CP0_CONFIG1_IL_32BYTES (4 << CP0_CONFIG1_IL_SHIFT) /* 32 bytes */ +# define CP0_CONFIG1_IL_64BYTES (5 << CP0_CONFIG1_IL_SHIFT) /* 64 bytes */ +# define CP0_CONFIG1_IL_128BYTES (6 << CP0_CONFIG1_IL_SHIFT) /* 128 bytes */ +#define CP0_CONFIG1_IS_SHIFT (22) /* Bits 22-24: Icache sets per way */ +#define CP0_CONFIG1_IS_MASK (7 << CP0_CONFIG1_IS_SHIFT) +# define CP0_CONFIG1_IS_64SETS (0 << CP0_CONFIG1_IS_SHIFT) +# define CP0_CONFIG1_IS_128SETS (1 << CP0_CONFIG1_IS_SHIFT) +# define CP0_CONFIG1_IS_256SETS (2 << CP0_CONFIG1_IS_SHIFT) +# define CP0_CONFIG1_IS_512SETS (3 << CP0_CONFIG1_IS_SHIFT) +# define CP0_CONFIG1_IS_1024SETS (4 << CP0_CONFIG1_IS_SHIFT) +# define CP0_CONFIG1_IS_2048SETS (5 << CP0_CONFIG1_IS_SHIFT) +# define CP0_CONFIG1_IS_4096SETS (6 << CP0_CONFIG1_IS_SHIFT) +#define CP0_CONFIG1_MMUSIZE_SHIFT (25) /* Bits 25-30: Number of entries in the TLB minus one */ +#define CP0_CONFIG1_MMUSIZE_MASK (0x3f << CP0_CONFIG1_MMUSIZE_SHIFT) +#define CP0_CONFIG1_M (1 << 31) /* Bit 31: Config2 register is present */ + +/* Register Number: 16 Sel: 2 Name: Config2 + * Function: Configuration register 2 + * Compliance Level: Optional. + */ + +#define CP0_CONFIG2_TBS_SHIFT (0) /* Bits 0-30: Configuration of the level 2 and level 3 caches */ +#define CP0_CONFIG2_TBS_MASK (0x7fffffff << CP0_CONFIG2_TBS_SHIFT) +#define CP0_CONFIG2_M (1 << 31) /* Bit 31: Config3 register is present */ + +/* Register Number: 16 Sel: 3 Name: Config3 + * Function: Configuration register 3 + * Compliance Level: Optional. + */ +#define CP0_CONFIG3_TL (1 << 0) /* Bit 0: Trace Logic implemented */ +#define CP0_CONFIG3_SM (1 << 1) /* Bit 1: SmartMIPS™ ASE implemented */ +#define CP0_CONFIG3_M (1 << 31) /* Bit 31: Config4 register is present */ + +/* Register Number: 16 Sel: 6-7 (Available for implementation dependent use) */ + +/* Register Number: 17 Sel: 0 Name: LLAddr + * Function: Load linked address + * Compliance Level: Optional. + * + * This register contains a 32-bit address value; No fields need be defined for this + * register. + */ + +/* Register Number: 18 Sel: 0-n Name: WatchLo + * Function: Watchpoint address + * Compliance Level: Optional. + */ + +#define CP0_WATCHLO_W (1 << 0) /* Bit 0: Exceptions are enabled for stores */ +#define CP0_WATCHLO_R (1 << 1) /* Bit 0: Exceptions are enabled for loads */ +#define CP0_WATCHLO_I (1 << 2) /* Bit 0: Exceptions are enabled for instructions */ +#define CP0_WATCHLO_VADDR_SHIFT (3) /* Bits 3-31: Virtual address to match */ +#define CP0_WATCHLO_VADDR_MASK (0x1fffffff << CP0_WATCHLO_VADDR_SHIFT) + +/* Register Number: 19 Sel: 0-n Name: WatchHi + * Function: Watchpoint control + * Compliance Level: Optional. + */ + +#define CP0_WATCHHI_MASK_SHIFT (3) /* Bits 3-11: Mask that qualifies the WatchLo address */ +#define CP0_WATCHHI_MASK_MASK (0x1ff << CP0_WATCHHI_MASK_SHIFT) +#define CP0_WATCHHI_ASID_SHIFT (16) /* Bits 16-23: ASID value which to match that in the EntryHi register */ +#define CP0_WATCHHI_ASID_MASK (0xff << CP0_WATCHHI_ASID_SHIFT) +#define CP0_WATCHHI_G (1 << 30) /* Bit 30: Any address matcing the WatchLo addr will cause an exception */ +#define CP0_WATCHHI_M (1 << 31) /* Bit 30: Another pair of WatchHi/WatchLo registers at select n+1 */ + +/* Register Number: 20 Sel: 0 Name: XContext + * Function: in 64-bit implementations + * + * Register Number: 21 Sel: all (Reserved for future extensions) + * + * Register Number: 22 Sel: all Available for implementation dependent use) + * + * Register Number: 23 Sel: 0 Name: Debug + * Function: EJTAG Debug register + * Compliance Level: Optional, part of the EJTAG specification. + * + * Register Number: 24 Sel: 0 Name: DEPC + * Function: Program counter at last EJTAG debug exception + * Compliance Level: Optional, part of the EJTAG specification. + * + * This register contains a 32-bit address value; No fields need be defined for this + * register. + */ + +/* Register Number: 25 Sel: 0-n Name: PerfCnt + * Function: Performance counter interface + * Compliance Level: Recommended. + */ + +#define CP0_PERFCNT_EXL (1 << 0) /* Bit 0: Enables event counting when STATUS EXL=1 ERL=0 */ +#define CP0_PERFCNT_K (1 << 1) /* Bit 1: Enables event counting in Kernel Mode (EXL=0 ERL=0) */ +#define CP0_PERFCNT_S (1 << 2) /* Bit 2: Enables event counting in Supervisor Mode */ +#define CP0_PERFCNT_U (1 << 3) /* Bit 3: Enables event counting in User Mode */ +#define CP0_PERFCNT_IE (1 << 4) /* Bit 4: Interrupt Enable */ +#define CP0_PERFCNT_EVENT_SHIFT (5) /* Bits 5-10: Event to be counted */ +#define CP0_PERFCNT_EVENT_MASK (0xffff << CP0_PERFCNT_EVENT_SHIFT) +#define CP0_PERFCNT_M (1 << 31) /* Bit 31: Another pair of performance registers at n+2 and n+3 */ + +/* Register Number: 26 Sel: 0 Name: ErrCtl + * Function: Parity/ECC error control and status + * Compliance Level: Optional. + * + * The bit definitions within the ErrCtl register are implementation dependent. + * + * Register Number: 27 Sel: 0-3 Name: CacheErr + * Function: Cache parity error control and status + * Compliance Level: Optional. + * + * The bit definitions within the CacheErr register are implementation dependent. + * + * Register Number: 28 Sel: 0 Name: TagLo + * Function: Low-order portion of cache tag interface + * Compliance Level: Required if a cache is implemented; Optional otherwise. + * + * The bit definitions within the TagLo register are implementation dependent. + * + * Register Number: 28 Sel: 1, 3 Name: DataLo + * Function: The DataLo and DataHi registers are read-only registers that + * act as the interface to the cache data array and are intended for + * diagnostic operation only. + * Compliance Level: Optional. + * + * The bit definitions within the DataLo register are implementation dependent. + * + * Register Number: 29 Sel: 0 Name: TagHi + * Function: High-order portion of cache tag interface + * Compliance Level: Required if a cache is implemented; Optional otherwise. + * + * The bit definitions within the TagHi register are implementation dependent. + * + * Register Number: 29 Sel: 1, 3 Name: DataHi + * Function: The DataLo and DataHi registers are read-only registers that + * act as the interface to the cache data array and are intended for + * diagnostic operation only. + * Compliance Level: Optional. + * + * The bit definitions within the DataHi register are implementation dependent. + * + * Register Number: 30 Sel: 0 Name: ErrorEPC + * Function: Program counter at last error + * Compliance Level: Required. + * + * This register contains a 32-bit address value; No fields need be defined for this + * register. + * + * Register Number: 31 Sel: 0 Name: DESAVE + * Function: EJTAG debug exception save register + * Compliance Level: Optional, part of the EJTAG specification. + * + * This register contains a 32-bit address value; No fields need be defined for this + * register. + */ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/******************************************************************************************** + * Inline Functions + ********************************************************************************************/ + +/******************************************************************************************** + * Public Function Prototypes + ********************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_MIPS32_MIPS32_CP0_H */ diff --git a/arch/mips/src/mips32/mips32-memorymap.h b/arch/mips/src/mips32/mips32-memorymap.h new file mode 100755 index 00000000000..f4a0fed7d5d --- /dev/null +++ b/arch/mips/src/mips32/mips32-memorymap.h @@ -0,0 +1,96 @@ +/******************************************************************************************** + * arch/mips/src/mips32/mips32-memorymap.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_MIPS32_MIPS32_MEMORYMAP_H +#define __ARCH_MIPS_SRC_MIPS32_MIPS32_MEMORYMAP_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +/******************************************************************************************** + * Pre-Processor Definitions + ********************************************************************************************/ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/* MIPS32 address space organization */ + +#define USEG_BASE 0x00000000 +#define USEG_SIZE 0x80000000 + +#define KSEG0_BASE 0x80000000 +#define KSEG0_SIZE 0x20000000 + +#define KSEG1_BASE 0xa0000000 +#define KSEG1_SIZE 0x20000000 + +#define KSEG2_BASE 0xc0000000 +#define KSEG2_SIZE 0x20000000 + +#define KSEG3_BASE 0xe0000000 +#define KSEG3_SIZE 0x20000000 + +#define DSEG_BASE 0xff200000 +#define DSEG_SIZE 0x00200000 + +#ifndef __ASSEMBLY__ + +/******************************************************************************************** + * Inline Functions + ********************************************************************************************/ + +/******************************************************************************************** + * Public Function Prototypes + ********************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_MIPS32_MIPS32_MEMORYMAP_H */ diff --git a/arch/mips/src/pic32mx/pic32mx-cp0.h b/arch/mips/src/pic32mx/pic32mx-cp0.h new file mode 100755 index 00000000000..2ad658d3a1a --- /dev/null +++ b/arch/mips/src/pic32mx/pic32mx-cp0.h @@ -0,0 +1,380 @@ +/**************************************************************************** + * arch/mips/src/pic32mx/pic32mx-cp0.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CP0_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CP0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "mips32-cp0.h" + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ +/* CP0 Registers ************************************************************/ + +/* Register Number: 0-6: Reserved + * Compliance Level: Required for TLB-based MMU; Optional otherwise. + */ + +/* Register Number: 7 Sel: 0 Name: HWREna + * Function: Enables access via the RDHWR instruction to selected hardware + * registers in non-privileged mode. + * Compliance Level: (Reserved for future extensions) + */ + +#define CP0_HWRENA_SHIFT (0) /* Bits 0-3: Enable access to a hardware resource */ +#define CP0_HWRENA_MASK (15 << CP0_HWRENA_SHIFT) +# define CP0_HWRENA_BIT0 (1 << CP0_HWRENA_SHIFT) +# define CP0_HWRENA_BIT1 (2 << CP0_HWRENA_SHIFT) +# define CP0_HWRENA_BIT2 (4 << CP0_HWRENA_SHIFT) +# define CP0_HWRENA_BIT3 (8 << CP0_HWRENA_SHIFT) + +/* Register Number: 8 Sel: 0 Name: BadVAddr + * Function: Reports the address for the most recent address-related + * exception + * Compliance Level: Required. + * + * See arch/mips/src/mips32/mips32-cp0.h + * + * Register Number: 9 Sel: 0 Name: Count + * Function: Processor cycle count + * Compliance Level: Required. + * + * See arch/mips/src/mips32/mips32-cp0.h + * + * Register Number: 10 Reserved. + * Compliance Level: Required for TLB-based MMU; Optional otherwise. + * + * Register Number: 11 Sel: 0 Name: Compare + * Function: Timer interrupt control + * Compliance Level: Required. + * + * See arch/mips/src/mips32/mips32-cp0.h + */ + +/* Register Number: 12 Sel: 0 Name: Status + * Function: Processor status and control + * Compliance Level: Required. + * + * See arch/mips/src/mips32/mips32-cp0.h + * NOTES: + * 1. The following are reserved bits in the PIC32: + * CP0_STATUS_UX Bit 5: Enables 64-bit user address space (Not MIPS32) + * CP0_STATUS_SX Bit 6: Enables 64-bit supervisor address space (Not MIPS32) + * CP0_STATUS_KX Bit 7: Enables 64-bit kernel address space (Not MIPS32) + * CP0_STATUS_IMPL Bits 16-17: Interrupt Mask + * CP0_STATUS_TS Bit 21: TLB detected match on multiple entries + * CP0_STATUS_PX Bit 23: Enables 64-bit operations (Not MIPS32) + * CP0_STATUS_MX Bit 24: Enables MDMX™ (Not MIPS32) + */ + +#undef CP0_STATUS_UX +#undef CP0_STATUS_SX +#undef CP0_STATUS_KX +#undef CP0_STATUS_IMPL +#undef CP0_STATUS_IMPL_SHIFT +#undef CP0_STATUS_IMPL_MASK +#undef CP0_STATUS_TS +#undef CP0_STATUS_PX +#undef CP0_STATUS_MX + +/* 2. The following field is of a different width + * CP0_STATUS_IM Bits 8-15: Interrupt Mask + * Vs. + * CP0_STATUS_IPL Bits 10-15: Interrupt priority level + * Bitss 8-9 reserved + */ + +#undef CP0_STATUS_IM_SHIFT +#undef CP0_STATUS_IM_MASK +#undef CP0_STATUS_IM0 +#undef CP0_STATUS_IM1 +#undef CP0_STATUS_IM2 +#undef CP0_STATUS_IM3 +#undef CP0_STATUS_IM4 +#undef CP0_STATUS_IM5 +#undef CP0_STATUS_IM6 +#undef CP0_STATUS_IM7 + +#define CP0_STATUS_IPL_SHIFT (10) /* Bits 10-15: Interrupt priority level */ +#define CP0_STATUS_IPL_MASK (0x3f << CP0_STATUS_IPL_SHIFT) + +/* 3. Supervisor mode not supported + * CP0_STATUS_KSU Bits 3-4: Operating mode (with supervisor mode) + */ + +#undef CP0_STATUS_KSU_SHIFT +#undef CP0_STATUS_KSU_MASK +#undef CP0_STATUS_KSU_KERNEL +#undef CP0_STATUS_KSU_SUPER +#undef CP0_STATUS_KSU_USER + +/* Register Number: 12 Sel: x Name: IntCtl */ + +#define CP0_CONFIG_VS_SHIFT (5) /* Bits 5-9: Vector spacing bits */ +#define CP0_CONFIG_VS_MASK (0x1f << CP0_CONFIG_VS_SHIFT) +# define CP0_CONFIG_VS_0BYTES (0x00 << CP0_CONFIG_VS_SHIFT) +# define CP0_CONFIG_VS_32BYTES (0x01 << CP0_CONFIG_VS_SHIFT) +# define CP0_CONFIG_VS_64BYTES (0x02 << CP0_CONFIG_VS_SHIFT) +# define CP0_CONFIG_VS_128BYTES (0x04 << CP0_CONFIG_VS_SHIFT) +# define CP0_CONFIG_VS_256BYTES (0x08 << CP0_CONFIG_VS_SHIFT) +# define CP0_CONFIG_VS_512BYTES (0x10 << CP0_CONFIG_VS_SHIFT) + +/* Register Number: 12 Sel: x Name: SRSCtl */ + +#define CP0_SRSCTL_CSS_SHIFT (0) /* Bits 0-3: Current shadow bit set */ +#define CP0_SRSCTL_CSS_MASK (15 << CP0_SRSCTL_CSS_SHIFT) +#define CP0_SRSCTL_PSS_SHIFT (6) /* Bits 6-9: Previous shadow set */ +#define CP0_SRSCTL_PSS_MASK (15 << CP0_SRSCTL_PSS_SHIFT) +#define CP0_SRSCTL_ESS_SHIFT (12) /* Bits 12-15: Exception shadow sets */ +#define CP0_SRSCTL_ESS_MASK (15 << CP0_SRSCTL_ESS_SHIFT) +#define CP0_SRSCTL_EICSS_SHIFT (18) /* Bits 18-21: External interrupt controller shadow sets */ +#define CP0_SRSCTL_EICSS_MASK (15 << CP0_SRSCTL_EICSS_SHIFT) +#define CP0_SRSCTL_HSS_SHIFT (26) /* Bits 26-29: High shadow sets */ +#define CP0_SRSCTL_HSS_MASK (15 << CP0_SRSCTL_HSS_SHIFT) +# define CP0_SRSCTL_HSS_1SET (0 << CP0_SRSCTL_HSS_SHIFT) /* One shadow set (normal GPR set) */ +# define CP0_SRSCTL_HSS_2SETS (1 << CP0_SRSCTL_HSS_SHIFT) /* Two shadow sets */ +# define CP0_SRSCTL_HSS_4SETS (3 << CP0_SRSCTL_HSS_SHIFT) /* Four shadow sets */ + +/* Register Number: 12 Sel: x Name: SRSMap */ + +#define CP0_SRSMAP_SSV0_SHIFT (0) /* Bits 0-3: Shadow set vector 0 */ +#define CP0_SRSMAP_SSV0_MASK (15 << CP0_SRSMAP_SSV0_SHIFT) +#define CP0_SRSMAP_SSV1_SHIFT (4) /* Bits 4-7: Shadow set vector 1 */ +#define CP0_SRSMAP_SSV1_MASK (15 << CP0_SRSMAP_SSV1_SHIFT) +#define CP0_SRSMAP_SSV2_SHIFT (8) /* Bits 8-11: Shadow set vector 2 */ +#define CP0_SRSMAP_SSV2_MASK (15 << CP0_SRSMAP_SSV2_SHIFT) +#define CP0_SRSMAP_SSV3_SHIFT (12) /* Bits 12-15: Shadow set vector 3 */ +#define CP0_SRSMAP_SSV3_MASK (15 << CP0_SRSMAP_SSV3_SHIFT) +#define CP0_SRSMAP_SSV4_SHIFT (16) /* Bits 16-19: Shadow set vector 4 */ +#define CP0_SRSMAP_SSV4_MASK (15 << CP0_SRSMAP_SSV4_SHIFT) +#define CP0_SRSMAP_SSV5_SHIFT (20) /* Bits 20-23: Shadow set vector 5 */ +#define CP0_SRSMAP_SSV5_MASK (15 << CP0_SRSMAP_SSV5_SHIFT) +#define CP0_SRSMAP_SSV6_SHIFT (24) /* Bits 24-27: Shadow set vector 6 */ +#define CP0_SRSMAP_SSV6_MASK (15 << CP0_SRSMAP_SSV6_SHIFT) +#define CP0_SRSMAP_SSV7_SHIFT (28) /* Bits 28-31: Shadow set vector 7 */ +#define CP0_SRSMAP_SSV7_MASK (15 << CP0_SRSMAP_SSV7_SHIFT) + +/* Register Number: 13 Sel: 0 Name: Cause + * Function: Cause of last general exception + * Compliance Level: Required. + * + * See arch/mips/src/mips32/mips32-cp0.h + * NOTES: The following bits are added in the PIC32: + */ + +#define CP0_CAUSE_R (1 << 26) /* Bit 26: R bit */ +#define CP0_CAUSE_DC (1 << 27) /* Bit 27: Disable count */ +#define CP0_CAUSE_TI (1 << 30) /* Bit 30: Timer interrupt bit *. + +/* Register Number: 14 Sel: 0 Name: EPC + * Function: Program counter at last exception + * Compliance Level: Required. + * + * See arch/mips/src/mips32/mips32-cp0.h + */ + +/* Register Number: 15 Sel: 0 Name: PRId + * Function: Processor identification and revision + * Compliance Level: Required. + * + * See arch/mips/src/mips32/mips32-cp0.h + * NOTE: Slightly different bit interpretations of some fields: + */ + +#define CP0_PRID_PATCH_SHIFT (5) /* Bits 0-1: Patch level */ +#define CP0_PRID_PATCH_MASK (3 << CP0_PRID_PATCH_SHIFT) +#define CP0_PRID_MINOR_SHIFT (2) /* Bits 2-4: Minor revision number */ +#define CP0_PRID_MINOR_MASK (7 << CP0_PRID_MINOR_SHIFT) +#define CP0_PRID_MAJOR_SHIFT (5) /* Bits 5-7: Major revision number */ +#define CP0_PRID_MAJOR_MASK (7 << CP0_PRID_MAJOR_SHIFT) + +#undef CP0_PRID_OPTIONS_SHIFT +#undef CP0_PRID_OPTIONS_MASK + +/* Register Number: 15 Sel: x Name: EBASE */ + +#define CP_EBASE_CPUNUM_SHIFT (0) /* Bits 0-9: CPU number */ +#define CP_EBASE_CPUNUM_MASK (0x3ff << CP_EBASE_CPUNUM_SHIFT) +#define CP_EBASE_SHIFT (12) /* Bits 30-31=10, Bits 12-29: Exception base */ +#define CP_EBASE_MASK (0x3ffff << CP_EBASE_SHIFT) + +/* Register Number: 16 Sel: 0 Name: Config + * Function: Configuration register + * Compliance Level: Required. + * + * See arch/mips/src/mips32/mips32-cp0.h + * 1. PIC32MX is always little-endian. + * 2. Implementation specific bits defined. + */ + +#undef CP0_CONFIG_IMPL_SHIFT +#undef CP0_CONFIG_IMPL_MASK + +#define CP0_CONFIG_K23_SHIFT (0) /* Bits 28-30: KSEG2 and KSEG3 cacheability */ +#define CP0_CONFIG_K23_MASK (7 << CP0_CONFIG_K23_SHIFT) +# define CP0_CONFIG_K23_UNCACHED (2 << CP0_CONFIG_K23_SHIFT) +# define CP0_CONFIG_K23_CACHEABLE (3 << CP0_CONFIG_K23_SHIFT) +#define CP0_CONFIG_KU_SHIFT (0) /* Bits 0-2: KUSEG and USEG cacheability */ +#define CP0_CONFIG_KU_MASK (7 << CP0_CONFIG_KU_SHIFT) +# define CP0_CONFIG_KU_UNCACHED (2 << CP0_CONFIG_KU_SHIFT) +# define CP0_CONFIG_KU_CACHEABLE (3 << CP0_CONFIG_KU_SHIFT) +#define CP0_CONFIG_UDI (1 << 22) /* Bit 22: User defined bit */ +#define CP0_CONFIG_SB (1 << 21) /* Bit 32: Simple BE bus mode bit */ +#define CP0_CONFIG_MDU (1 << 20) /* Multipley/Divide unit bit */ +#define CP0_CONFIG_DS (1 << 16) /* Dual SRAM bit */ + +/* Register Number: 16 Sel: 1 Name: Config1 + * Function: Configuration register 1 + * Compliance Level: Required. + * + * See arch/mips/src/mips32/mips32-cp0.h + * + * Register Number: 16 Sel: 2 Name: Config2 + * Function: Configuration register 2 + * Compliance Level: Optional. + * + * See arch/mips/src/mips32/mips32-cp0.h + */ + +#undef CP0_CONFIG2_TBS_SHIFT +#undef CP0_CONFIG2_TBS_MASK + +/* Register Number: 16 Sel: 3 Name: Config3 + * Function: Configuration register 3 + * Compliance Level: Optional. + * + * See arch/mips/src/mips32/mips32-cp0.h + */ + +#define CP0_CONFIG3_SP (1 << 4) /* Bit 4: Support page bit */ +#define CP0_CONFIG3_VINT (1 << 5) /* Bit 5: Vector interrupt bit */ +#define CP0_CONFIG3_VEIC (1 << 6) /* Bit 6: External interrupt controller supported */ + +/* Register Number: 17-22 Reserved + * Compliance Level: Optional. + */ + +/* Register Number: 23 Sel: 0 Name: Debug + * Function: EJTAG Debug register + * Compliance Level: Optional. + */ + +#define CP0_DEBUG_DSS (1 << 0) /* Bit 0: Debug single-step exception */ +#define CP0_DEBUG_DBP (1 << 1) /* Bit 1: Debug software breakpoint exception */ +#define CP0_DEBUG_DDBL (1 << 2) /* Bit 2: Debug data break exception on load */ +#define CP0_DEBUG_DDBS (1 << 3) /* Bit 3: Debug data break exception on store */ +#define CP0_DEBUG_DIB (1 << 4) /* Bit 4: Debug instruction break exception */ +#define CP0_DEBUG_DINT (1 << 5) /* Bit 5: Debug interrupt exception */ +#define CP0_DEBUG_SST (1 << 8) /* Bit 6: Enable debug single step exception */ +#define CP0_DEBUG_NOSST (1 << 9) /* Bit 7: No single step feature available */ +#define CP0_DEBUG_DEXCCODE_SHIFT (10) /* Bits 10-14: Cause of latest exception in DEBUG mode */ +#define CP0_DEBUG_DEXCCODE_MASK (31 << CP0_DEBUG_DEXCCODE_SHIFT) +#define CP0_DEBUG_VER_SHIFT (15) /* Bits 15-17: EJTAG version */ +#define CP0_DEBUG_VER_MASK (7 << CP0_DEBUG_VER_SHIFT) +#define CP0_DEBUG_DDBLIMPR (1 << 18) /* Bit 18: Imprecise debug data break load instruction */ +#define CP0_DEBUG_DDBSIMPR (1 << 19) /* Bit 19: Imprecise debug data break store instruction */ +#define CP0_DEBUG_IEXI (1 << 20) /* Bit 20: Imprecise error exception inhibit */ +#define CP0_DEBUG_DBUSEP (1 << 21) /* Bit 21: Data access bus error exception pending */ +#define CP0_DEBUG_CACHEEP (1 << 22) /* Bit 22: Imprecise cache error exception is pending */ +#define CP0_DEBUG_MCHECKP (1 << 23) /* Bit 23: Imprecise machine check exception is pending */ +#define CP0_DEBUG_IBUSEP (1 << 24) /* Bit 24: Bus error exception pending */ +#define CP0_DEBUG_COUNTDM (1 << 25) /* Bit 25: Count register behavior (1=running) */ +#define CP0_DEBUG_HALT (1 << 26) /* Bit 26: Internal system bus clock stopped */ +#define CP0_DEBUG_DOZE (1 << 27) /* Bit 27: Processor in low power mode */ +#define CP0_DEBUG_LSNM (1 << 28) /* Bit 28: Load/store in DSEG goes to main memory */ +#define CP0_DEBUG_NODCR (1 << 29) /* Bit 29: No DSEG preset */ +#define CP0_DEBUG_DM (1 << 30) /* Bit 30: Processor is operating in DEBUG mode */ +#define CP0_DEBUG_DBD (1 << 31) /* Bit 31: Last debug exception occurred in a dely slot */ + +/* Register Number: 23 Sel: ? Name: Debug2 + * Is this documented anywhere? + */ + +/* Register Number: 24 Sel: 0 Name: DEPC + * Function: Program counter at last EJTAG debug exception + * Compliance Level: Optional. + * + * See arch/mips/src/mips32/mips32-cp0.h + * + * Register Number: 25-29 Reserved + * Compliance Level: Recommended/Optional. + * + * Register Number: 30 Sel: 0 Name: ErrorEPC + * Function: Program counter at last error + * Compliance Level: Required. + * + * See arch/mips/src/mips32/mips32-cp0.h + * + * Register Number: 31 Sel: 0 Name: DeSAVE + * Function: EJTAG debug exception save register + * Compliance Level: Optional. + * + * See arch/mips/src/mips32/mips32-cp0.h + */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CP0_H */