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arch/arm/src/tiva/hardware: Add CC13x0 and CC13x2 I2C header files.

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This commit is contained in:
Gregory Nutt
2019-02-16 09:32:38 -06:00
parent 4bd2a9e1b2
commit d1f65b127e
7 changed files with 2283 additions and 1009 deletions
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arch/arm/src/tiva/hardware/cc13x0/cc13x0_i2c.h
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/********************************************************************************************
* arch/arm/src/tiva/hardware/cc13x0/cc13x0_i2c.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_I2C_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_I2C_H
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* I2C register offsets *********************************************************************/
#define TIVA_I2C_SOAR_OFFSET 0x0000 /* Slave Own Address */
#define TIVA_I2C_SSTAT_OFFSET 0x0004 /* Slave Status */
#define TIVA_I2C_SCTL_OFFSET 0x0004 /* Slave Control */
#define TIVA_I2C_SDR_OFFSET 0x0008 /* Slave Data */
#define TIVA_I2C_SIMR_OFFSET 0x000c /* Slave Interrupt Mask */
#define TIVA_I2C_SRIS_OFFSET 0x0010 /* Slave Raw Interrupt Status */
#define TIVA_I2C_SMIS_OFFSET 0x0014 /* Slave Masked Interrupt Status */
#define TIVA_I2C_SICR_OFFSET 0x0018 /* Slave Interrupt Clear */
#define TIVA_I2C_MSA_OFFSET 0x0800 /* Master Slave Address */
#define TIVA_I2C_MSTAT_OFFSET 0x0804 /* Master Status */
#define TIVA_I2C_MCTRL_OFFSET 0x0804 /* Master Control */
#define TIVA_I2C_MDR_OFFSET 0x0808 /* Master Data */
#define TIVA_I2C_MTPR_OFFSET 0x080c /* I2C Master Timer Period */
#define TIVA_I2C_MIMR_OFFSET 0x0810 /* Master Interrupt Mask */
#define TIVA_I2C_MRIS_OFFSET 0x0814 /* Master Raw Interrupt Status */
#define TIVA_I2C_MMIS_OFFSET 0x0818 /* Master Masked Interrupt Status */
#define TIVA_I2C_MICR_OFFSET 0x081c /* Master Interrupt Clear */
#define TIVA_I2C_MCR_OFFSET 0x0820 /* Master Configuration */
/* I2C register addresses *******************************************************************/
#define TIVA_I2C0_SOAR (TIVA_I2C0_BASE + TIVA_I2C_SOAR_OFFSET)
#define TIVA_I2C0_SSTAT (TIVA_I2C0_BASE + TIVA_I2C_SSTAT_OFFSET)
#define TIVA_I2C0_SCTL (TIVA_I2C0_BASE + TIVA_I2C_SCTL_OFFSET)
#define TIVA_I2C0_SDR (TIVA_I2C0_BASE + TIVA_I2C_SDR_OFFSET)
#define TIVA_I2C0_SIMR (TIVA_I2C0_BASE + TIVA_I2C_SIMR_OFFSET)
#define TIVA_I2C0_SRIS (TIVA_I2C0_BASE + TIVA_I2C_SRIS_OFFSET)
#define TIVA_I2C0_SMIS (TIVA_I2C0_BASE + TIVA_I2C_SMIS_OFFSET)
#define TIVA_I2C0_SICR (TIVA_I2C0_BASE + TIVA_I2C_SICR_OFFSET)
#define TIVA_I2C0_MSA (TIVA_I2C0_BASE + TIVA_I2C_MSA_OFFSET)
#define TIVA_I2C0_MSTAT (TIVA_I2C0_BASE + TIVA_I2C_MSTAT_OFFSET)
#define TIVA_I2C0_MCTRL (TIVA_I2C0_BASE + TIVA_I2C_MCTRL_OFFSET)
#define TIVA_I2C0_MDR (TIVA_I2C0_BASE + TIVA_I2C_MDR_OFFSET)
#define TIVA_I2C0_MTPR (TIVA_I2C0_BASE + TIVA_I2C_MTPR_OFFSET)
#define TIVA_I2C0_MIMR (TIVA_I2C0_BASE + TIVA_I2C_MIMR_OFFSET)
#define TIVA_I2C0_MRIS (TIVA_I2C0_BASE + TIVA_I2C_MRIS_OFFSET)
#define TIVA_I2C0_MMIS (TIVA_I2C0_BASE + TIVA_I2C_MMIS_OFFSET)
#define TIVA_I2C0_MICR (TIVA_I2C0_BASE + TIVA_I2C_MICR_OFFSET)
#define TIVA_I2C0_MCR (TIVA_I2C0_BASE + TIVA_I2C_MCR_OFFSET)
/* I2C bitfield defintions ******************************************************************/
/* Slave Own Address */
#define I2C_SOAR_OAR_SHIFT (0) /* Bits 0-6: 2C slave own address */
#define I2C_SOAR_OAR_MASK (0x7f << I2C_SOAR_OAR_SHIFT)
# define I2C_SOAR_OAR(n) ((uint32_t)(n) << I2C_SOAR_OAR_SHIFT)
/* Slave Status */
#define I2C_SSTAT_RREQ (1 << 0) /* Bit 0: Receive request */
#define I2C_SSTAT_TREQ (1 << 1) /* Bit 1: Transmit request */
#define I2C_SSTAT_FBR (1 << 2) /* Bit 2: First byte received */
/* Slave Control */
#define I2C_SCTL_DA (1 << 0) /* Bit 0: Device active */
/* Slave Data */
#define I2C_SDR_DATA_SHIFT (0) /* Bits 0-7: Data for transfer */
#define I2C_SDR_DATA_MASK 0x000000ff
#define I2C_SDR_DATA_MASK (0xff << I2C_SDR_DATA_SHIFT)
# define I2C_SDR_DATA(n) ((uint32_t)(n) << I2C_SDR_DATA_SHIFT)
/* Slave Interrupt Mask */
#define I2C_SIMR_DATAIM (1 << 0) /* Bit 0: Data interrupt mask */
#define I2C_SIMR_STARTIM (1 << 1) /* Bit 1: Start condition interrupt mask */
#define I2C_SIMR_STOPIM (1 << 2) /* Bit 2: Stop condition interrupt mask */
/* Slave Raw Interrupt Status */
#define I2C_SRIS_DATARIS (1 << 0) /* Bit 0: Data raw interrupt status */
#define I2C_SRIS_STARTRIS (1 << 1) /* Bit 1: Start condition raw interrupt status */
#define I2C_SRIS_STOPRIS (1 << 2) /* Bit 2: Stop condition raw interrupt status */
/* Slave Masked Interrupt Status */
#define I2C_SMIS_DATAMIS (1 << 0) /* Bit 0: Data masked interrupt status */
#define I2C_SMIS_STARTMIS (1 << 1) /* Bit 1: Start condition masked interrupt status */
#define I2C_SMIS_STOPMIS (1 << 2) /* Bit 2: Stop condition masked interrupt status */
/* Slave Interrupt Clear */
#define I2C_SICR_DATAIC (1 << 0) /* Bit 0: Data interrupt clear */
#define I2C_SICR_STARTIC (1 << 1) /* Bit 1: Start condition interrupt clear */
#define I2C_SICR_STOPIC (1 << 2) /* Bit 2: top condition interrupt clear */
/* Master Slave Address */
#define I2C_MSA_RS (1 << 0) /* Bit 0: Receive or Send */
# define I2C_MSA_RS_TX 0
# define I2C_MSA_RS_RX I2C_MSA_RS
#define I2C_MSA_SA_SHIFT (1) /* Bits 1-7: I2C master slave address */
#define I2C_MSA_SA_MASK (0x7f << I2C_MSA_SA_SHIFT)
# define I2C_MSA_SA(n) ((uint32_t)(n) << I2C_MSA_SA_SHIFT)
/* Master Status */
#define I2C_MSTAT_BUSY (1 << 0) /* Bit 0: I2C busy */
#define I2C_MSTAT_ERR (1 << 1) /* Bit 1: Error */
#define I2C_MSTAT_ADRACK_N (1 << 2) /* Bit 2: Address Was Not Acknowledged */
#define I2C_MSTAT_DATACK_N (1 << 3) /* Bit 3: Data Was Not Acknowledged */
#define I2C_MSTAT_ARBLST (1 << 4) /* Bit 4: Arbitration lost */
#define I2C_MSTAT_IDLE (1 << 5) /* Bit 5: I2C idle */
#define I2C_MSTAT_BUSBSY (1 << 6) /* Bit 6: Bus busy */
/* Master Control */
#define I2C_MCTRL_RUN (1 << 0) /* Bit 0: Enable master transfer */
#define I2C_MCTRL_START (1 << 1) /* Bit 1: Generate [repeated] START */
#define I2C_MCTRL_STOP (1 << 2) /* Bit 2: STOP at end of data cyle */
#define I2C_MCTRL_ACK (1 << 3) /* Bit 3: Data acknowledge enable */
/* Master Data */
#define I2C_MDR_DATA_SHIFT (0) /* Bits 0-7: */
#define I2C_MDR_DATA_MASK (0xff << I2C_MDR_DATA_SHIFT)
# define I2C_MDR_DATA(n) ((uint32_t)(n) << I2C_MDR_DATA_SHIFT)
/* I2C Master Timer Period
*
* SCL_PRD = 2 * (1 + TPR) *( SCL_LP + SCL_HP) * CLK_PRD
*
* where:
* SCL_PRD - The SCL line period (I2C clock).
* TPR - The timer period register value (range of 1 to 127)
* SCL_LP - The SCL low period (fixed at 6).
* SCL_HP - The SCL high period (fixed at 4).
* CLK_PRD - The system clock period in ns.
*/
#define I2C_MTPR_TPR_SHIFT (0) /* Bits 0-6: SCL clock period */
#define I2C_MTPR_TPR_MASK (0x7f << I2C_MTPR_TPR_SHIFT)
# define I2C_MTPR_TPR(n) ((uint32_t)(n) << I2C_MTPR_TPR_SHIFT)
#define I2C_MTPR_TPR_7 (1 << 7) /* Bit 7: Lock TPR */
/* Master Interrupt Mask */
#define I2C_MIMR_IM (1 << 0) /* Bit 0: Interrupt mask */
/* Master Raw Interrupt Status */
#define I2C_MRIS_RIS (1 << 0) /* Bit 0: Raw interrupt status */
/* Master Masked Interrupt Status */
#define I2C_MMIS_MIS (1 << 0) /* Bit 0: Masked interrupt status */
/* Master Interrupt Clear */
#define I2C_MICR_IC (1 << 0) /* Bit 0: Interrupt clear */
/* Master Configuration */
#define I2C_MCR_LPBK (1 << 0) /* Bit 0: I2C loopback */
#define I2C_MCR_MFE (1 << 4) /* Bit 4: I2C master function enable */
#define I2C_MCR_SFE (1 << 5) /* Bit 5: I2C slave function enable */
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X0_CC13X0_I2C_H */
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_i2c.h
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/********************************************************************************************
* arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_i2c.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Technical content derives from a TI header file that has a compatible BSD license:
*
* Copyright (c) 2015-2017, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2_CC13X20_CC26X2_I2C_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2_CC13X20_CC26X2_I2C_H
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* I2C register offsets *********************************************************************/
#define TIVA_I2C_SOAR_OFFSET 0x0000 /* Slave Own Address */
#define TIVA_I2C_SSTAT_OFFSET 0x0004 /* Slave Status */
#define TIVA_I2C_SCTL_OFFSET 0x0004 /* Slave Control */
#define TIVA_I2C_SDR_OFFSET 0x0008 /* Slave Data */
#define TIVA_I2C_SIMR_OFFSET 0x000c /* Slave Interrupt Mask */
#define TIVA_I2C_SRIS_OFFSET 0x0010 /* Slave Raw Interrupt Status */
#define TIVA_I2C_SMIS_OFFSET 0x0014 /* Slave Masked Interrupt Status */
#define TIVA_I2C_SICR_OFFSET 0x0018 /* Slave Interrupt Clear */
#define TIVA_I2C_MSA_OFFSET 0x0800 /* Master Slave Address */
#define TIVA_I2C_MSTAT_OFFSET 0x0804 /* Master Status */
#define TIVA_I2C_MCTRL_OFFSET 0x0804 /* Master Control */
#define TIVA_I2C_MDR_OFFSET 0x0808 /* Master Data */
#define TIVA_I2C_MTPR_OFFSET 0x080c /* I2C Master Timer Period */
#define TIVA_I2C_MIMR_OFFSET 0x0810 /* Master Interrupt Mask */
#define TIVA_I2C_MRIS_OFFSET 0x0814 /* Master Raw Interrupt Status */
#define TIVA_I2C_MMIS_OFFSET 0x0818 /* Master Masked Interrupt Status */
#define TIVA_I2C_MICR_OFFSET 0x081c /* Master Interrupt Clear */
#define TIVA_I2C_MCR_OFFSET 0x0820 /* Master Configuration */
/* I2C register addresses *******************************************************************/
#define TIVA_I2C0_SOAR (TIVA_I2C0_BASE + TIVA_I2C_SOAR_OFFSET)
#define TIVA_I2C0_SSTAT (TIVA_I2C0_BASE + TIVA_I2C_SSTAT_OFFSET)
#define TIVA_I2C0_SCTL (TIVA_I2C0_BASE + TIVA_I2C_SCTL_OFFSET)
#define TIVA_I2C0_SDR (TIVA_I2C0_BASE + TIVA_I2C_SDR_OFFSET)
#define TIVA_I2C0_SIMR (TIVA_I2C0_BASE + TIVA_I2C_SIMR_OFFSET)
#define TIVA_I2C0_SRIS (TIVA_I2C0_BASE + TIVA_I2C_SRIS_OFFSET)
#define TIVA_I2C0_SMIS (TIVA_I2C0_BASE + TIVA_I2C_SMIS_OFFSET)
#define TIVA_I2C0_SICR (TIVA_I2C0_BASE + TIVA_I2C_SICR_OFFSET)
#define TIVA_I2C0_MSA (TIVA_I2C0_BASE + TIVA_I2C_MSA_OFFSET)
#define TIVA_I2C0_MSTAT (TIVA_I2C0_BASE + TIVA_I2C_MSTAT_OFFSET)
#define TIVA_I2C0_MCTRL (TIVA_I2C0_BASE + TIVA_I2C_MCTRL_OFFSET)
#define TIVA_I2C0_MDR (TIVA_I2C0_BASE + TIVA_I2C_MDR_OFFSET)
#define TIVA_I2C0_MTPR (TIVA_I2C0_BASE + TIVA_I2C_MTPR_OFFSET)
#define TIVA_I2C0_MIMR (TIVA_I2C0_BASE + TIVA_I2C_MIMR_OFFSET)
#define TIVA_I2C0_MRIS (TIVA_I2C0_BASE + TIVA_I2C_MRIS_OFFSET)
#define TIVA_I2C0_MMIS (TIVA_I2C0_BASE + TIVA_I2C_MMIS_OFFSET)
#define TIVA_I2C0_MICR (TIVA_I2C0_BASE + TIVA_I2C_MICR_OFFSET)
#define TIVA_I2C0_MCR (TIVA_I2C0_BASE + TIVA_I2C_MCR_OFFSET)
/* I2C bitfield defintions ******************************************************************/
/* Slave Own Address */
#define I2C_SOAR_OAR_SHIFT (0) /* Bits 0-6: 2C slave own address */
#define I2C_SOAR_OAR_MASK (0x7f << I2C_SOAR_OAR_SHIFT)
# define I2C_SOAR_OAR(n) ((uint32_t)(n) << I2C_SOAR_OAR_SHIFT)
/* Slave Status */
#define I2C_SSTAT_RREQ (1 << 0) /* Bit 0: Receive request */
#define I2C_SSTAT_TREQ (1 << 1) /* Bit 1: Transmit request */
#define I2C_SSTAT_FBR (1 << 2) /* Bit 2: First byte received */
/* Slave Control */
#define I2C_SCTL_DA (1 << 0) /* Bit 0: Device active */
/* Slave Data */
#define I2C_SDR_DATA_SHIFT (0) /* Bits 0-7: Data for transfer */
#define I2C_SDR_DATA_MASK 0x000000ff
#define I2C_SDR_DATA_MASK (0xff << I2C_SDR_DATA_SHIFT)
# define I2C_SDR_DATA(n) ((uint32_t)(n) << I2C_SDR_DATA_SHIFT)
/* Slave Interrupt Mask */
#define I2C_SIMR_DATAIM (1 << 0) /* Bit 0: Data interrupt mask */
#define I2C_SIMR_STARTIM (1 << 1) /* Bit 1: Start condition interrupt mask */
#define I2C_SIMR_STOPIM (1 << 2) /* Bit 2: Stop condition interrupt mask */
/* Slave Raw Interrupt Status */
#define I2C_SRIS_DATARIS (1 << 0) /* Bit 0: Data raw interrupt status */
#define I2C_SRIS_STARTRIS (1 << 1) /* Bit 1: Start condition raw interrupt status */
#define I2C_SRIS_STOPRIS (1 << 2) /* Bit 2: Stop condition raw interrupt status */
/* Slave Masked Interrupt Status */
#define I2C_SMIS_DATAMIS (1 << 0) /* Bit 0: Data masked interrupt status */
#define I2C_SMIS_STARTMIS (1 << 1) /* Bit 1: Start condition masked interrupt status */
#define I2C_SMIS_STOPMIS (1 << 2) /* Bit 2: Stop condition masked interrupt status */
/* Slave Interrupt Clear */
#define I2C_SICR_DATAIC (1 << 0) /* Bit 0: Data interrupt clear */
#define I2C_SICR_STARTIC (1 << 1) /* Bit 1: Start condition interrupt clear */
#define I2C_SICR_STOPIC (1 << 2) /* Bit 2: top condition interrupt clear */
/* Master Slave Address */
#define I2C_MSA_RS (1 << 0) /* Bit 0: Receive or Send */
# define I2C_MSA_RS_TX 0
# define I2C_MSA_RS_RX I2C_MSA_RS
#define I2C_MSA_SA_SHIFT (1) /* Bits 1-7: I2C master slave address */
#define I2C_MSA_SA_MASK (0x7f << I2C_MSA_SA_SHIFT)
# define I2C_MSA_SA(n) ((uint32_t)(n) << I2C_MSA_SA_SHIFT)
/* Master Status */
#define I2C_MSTAT_BUSY (1 << 0) /* Bit 0: I2C busy */
#define I2C_MSTAT_ERR (1 << 1) /* Bit 1: Error */
#define I2C_MSTAT_ADRACK_N (1 << 2) /* Bit 2: Address Was Not Acknowledged */
#define I2C_MSTAT_DATACK_N (1 << 3) /* Bit 3: Data Was Not Acknowledged */
#define I2C_MSTAT_ARBLST (1 << 4) /* Bit 4: Arbitration lost */
#define I2C_MSTAT_IDLE (1 << 5) /* Bit 5: I2C idle */
#define I2C_MSTAT_BUSBSY (1 << 6) /* Bit 6: Bus busy */
/* Master Control */
#define I2C_MCTRL_RUN (1 << 0) /* Bit 0: Enable master transfer */
#define I2C_MCTRL_START (1 << 1) /* Bit 1: Generate [repeated] START */
#define I2C_MCTRL_STOP (1 << 2) /* Bit 2: STOP at end of data cyle */
#define I2C_MCTRL_ACK (1 << 3) /* Bit 3: Data acknowledge enable */
/* Master Data */
#define I2C_MDR_DATA_SHIFT (0) /* Bits 0-7: */
#define I2C_MDR_DATA_MASK (0xff << I2C_MDR_DATA_SHIFT)
# define I2C_MDR_DATA(n) ((uint32_t)(n) << I2C_MDR_DATA_SHIFT)
/* I2C Master Timer Period
*
* SCL_PRD = 2 * (1 + TPR) *( SCL_LP + SCL_HP) * CLK_PRD
*
* where:
* SCL_PRD - The SCL line period (I2C clock).
* TPR - The timer period register value (range of 1 to 127)
* SCL_LP - The SCL low period (fixed at 6).
* SCL_HP - The SCL high period (fixed at 4).
* CLK_PRD - The system clock period in ns.
*/
#define I2C_MTPR_TPR_SHIFT (0) /* Bits 0-6: SCL clock period */
#define I2C_MTPR_TPR_MASK (0x7f << I2C_MTPR_TPR_SHIFT)
# define I2C_MTPR_TPR(n) ((uint32_t)(n) << I2C_MTPR_TPR_SHIFT)
#define I2C_MTPR_TPR_7 (1 << 7) /* Bit 7: Lock TPR */
/* Master Interrupt Mask */
#define I2C_MIMR_IM (1 << 0) /* Bit 0: Interrupt mask */
/* Master Raw Interrupt Status */
#define I2C_MRIS_RIS (1 << 0) /* Bit 0: Raw interrupt status */
/* Master Masked Interrupt Status */
#define I2C_MMIS_MIS (1 << 0) /* Bit 0: Masked interrupt status */
/* Master Interrupt Clear */
#define I2C_MICR_IC (1 << 0) /* Bit 0: Interrupt clear */
/* Master Configuration */
#define I2C_MCR_LPBK (1 << 0) /* Bit 0: I2C loopback */
#define I2C_MCR_MFE (1 << 4) /* Bit 4: I2C master function enable */
#define I2C_MCR_SFE (1 << 5) /* Bit 5: I2C slave function enable */
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2_CC13X20_CC26X2_I2C_H */
arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_uart.h
+3 -3
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@@ -38,8 +38,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2CC13X20_CC26X2UART_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2CC13X20_CC26X2UART_H
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2_CC13X20_CC26X2_UART_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2_CC13X20_CC26X2_UART_H
/************************************************************************************
* Included Files
@@ -273,4 +273,4 @@
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2CC13X20_CC26X2UART_H */
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_CC13X20_CC26X2_CC13X20_CC26X2_UART_H */
arch/arm/src/tiva/hardware/lm/lm_i2c.h
+434
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@@ -0,0 +1,434 @@
/************************************************************************************
* arch/arm/src/tiva/hardware/lm/lm_i2c.h
*
* Copyright (C) 2009, 2013-2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM_I2C_H
#define __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM_I2C_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* I2C Register Offsets *************************************************************/
/* I2C Master */
#define TIVA_I2CM_SA_OFFSET 0x0000 /* I2C Master Slave Address */
#define TIVA_I2CM_CS_OFFSET 0x0004 /* I2C Master Control/Status */
#define TIVA_I2CM_DR_OFFSET 0x0008 /* I2C Master Data */
#define TIVA_I2CM_TPR_OFFSET 0x000c /* I2C Master Timer Period */
#define TIVA_I2CM_IMR_OFFSET 0x0010 /* I2C Master Interrupt Mask */
#define TIVA_I2CM_RIS_OFFSET 0x0014 /* I2C Master Raw Interrupt Status */
#define TIVA_I2CM_MIS_OFFSET 0x0018 /* I2C Master Masked Interrupt Status */
#define TIVA_I2CM_ICR_OFFSET 0x001c /* I2C Master Interrupt Clear */
#define TIVA_I2CM_CR_OFFSET 0x0020 /* I2C Master Configuration */
/* I2C Slave */
#define TIVA_I2CS_OAR_OFFSET 0x0800 /* I2C Slave Own Address */
#define TIVA_I2CS_CSR_OFFSET 0x0804 /* I2C Slave Control/Status */
#define TIVA_I2CS_DR_OFFSET 0x0808 /* I2C Slave Data */
#define TIVA_I2CS_IMR_OFFSET 0x080c /* I2C Slave Interrupt Mask */
#define TIVA_I2CS_RIS_OFFSET 0x0810 /* I2C Slave Raw Interrupt Status */
#define TIVA_I2CS_MIS_OFFSET 0x0814 /* I2C Slave Masked Interrupt Status */
#define TIVA_I2CS_ICR_OFFSET 0x0818 /* I2C Slave Interrupt Clear */
/* I2C Register Addresses ***********************************************************/
#if TIVA_NI2C > 0
/* I2C0 Master */
#define TIVA_I2CM0_SA (TIVA_I2C0_BASE + TIVA_I2CM_SA_OFFSET)
#define TIVA_I2CM0_CS (TIVA_I2C0_BASE + TIVA_I2CM_CS_OFFSET)
#define TIVA_I2CM0_DR (TIVA_I2C0_BASE + TIVA_I2CM_DR_OFFSET)
#define TIVA_I2CM0_TPR (TIVA_I2C0_BASE + TIVA_I2CM_TPR_OFFSET)
#define TIVA_I2CM0_IMR (TIVA_I2C0_BASE + TIVA_I2CM_IMR_OFFSET)
#define TIVA_I2CM0_RIS (TIVA_I2C0_BASE + TIVA_I2CM_RIS_OFFSET)
#define TIVA_I2CM0_MIS (TIVA_I2C0_BASE + TIVA_I2CM_MIS_OFFSET)
#define TIVA_I2CM0_ICR (TIVA_I2C0_BASE + TIVA_I2CM_ICR_OFFSET)
#define TIVA_I2CM0_CR (TIVA_I2C0_BASE + TIVA_I2CM_CR_OFFSET)
/* I2C0 Slave */
#define TIVA_I2CS0_OAR (TIVA_I2C0_BASE + TIVA_I2CS_OAR_OFFSET)
#define TIVA_I2CS0_CSR (TIVA_I2C0_BASE + TIVA_I2CS_CSR_OFFSET)
#define TIVA_I2CS0_DR (TIVA_I2C0_BASE + TIVA_I2CS_DR_OFFSET)
#define TIVA_I2CS0_IMR (TIVA_I2C0_BASE + TIVA_I2CS_IMR_OFFSET)
#define TIVA_I2CS0_RIS (TIVA_I2C0_BASE + TIVA_I2CS_RIS_OFFSET)
#define TIVA_I2CS0_MIS (TIVA_I2C0_BASE + TIVA_I2CS_MIS_OFFSET)
#define TIVA_I2CS0_ICR (TIVA_I2C0_BASE + TIVA_I2CS_ICR_OFFSET)
#endif /* TIVA_NI2C > 0 */
#if TIVA_NI2C > 1
/* I2C1 Master */
#define TIVA_I2CM1_SA (TIVA_I2C1_BASE + TIVA_I2CM_SA_OFFSET)
#define TIVA_I2CM1_CS (TIVA_I2C1_BASE + TIVA_I2CM_CS_OFFSET)
#define TIVA_I2CM1_DR (TIVA_I2C1_BASE + TIVA_I2CM_DR_OFFSET)
#define TIVA_I2CM1_TPR (TIVA_I2C1_BASE + TIVA_I2CM_TPR_OFFSET)
#define TIVA_I2CM1_IMR (TIVA_I2C1_BASE + TIVA_I2CM_IMR_OFFSET)
#define TIVA_I2CM1_RIS (TIVA_I2C1_BASE + TIVA_I2CM_RIS_OFFSET)
#define TIVA_I2CM1_MIS (TIVA_I2C1_BASE + TIVA_I2CM_MIS_OFFSET)
#define TIVA_I2CM1_ICR (TIVA_I2C1_BASE + TIVA_I2CM_ICR_OFFSET)
#define TIVA_I2CM1_CR (TIVA_I2C1_BASE + TIVA_I2CM_CR_OFFSET)
/* I2C1 Slave */
#define TIVA_I2CS1_OAR (TIVA_I2C1_BASE + TIVA_I2CS_OAR_OFFSET)
#define TIVA_I2CS1_CSR (TIVA_I2C1_BASE + TIVA_I2CS_CSR_OFFSET)
#define TIVA_I2CS1_DR (TIVA_I2C1_BASE + TIVA_I2CS_DR_OFFSET)
#define TIVA_I2CS1_IMR (TIVA_I2C1_BASE + TIVA_I2CS_IMR_OFFSET)
#define TIVA_I2CS1_RIS (TIVA_I2C1_BASE + TIVA_I2CS_RIS_OFFSET)
#define TIVA_I2CS1_MIS (TIVA_I2C1_BASE + TIVA_I2CS_MIS_OFFSET)
#define TIVA_I2CS1_ICR (TIVA_I2C1_BASE + TIVA_I2CS_ICR_OFFSET)
#endif /* TIVA_NI2C > 1 */
#if TIVA_NI2C > 2
/* I2C2 Master */
#define TIVA_I2CM2_SA (TIVA_I2C2_BASE + TIVA_I2CM_SA_OFFSET)
#define TIVA_I2CM2_CS (TIVA_I2C2_BASE + TIVA_I2CM_CS_OFFSET)
#define TIVA_I2CM2_DR (TIVA_I2C2_BASE + TIVA_I2CM_DR_OFFSET)
#define TIVA_I2CM2_TPR (TIVA_I2C2_BASE + TIVA_I2CM_TPR_OFFSET)
#define TIVA_I2CM2_IMR (TIVA_I2C2_BASE + TIVA_I2CM_IMR_OFFSET)
#define TIVA_I2CM2_RIS (TIVA_I2C2_BASE + TIVA_I2CM_RIS_OFFSET)
#define TIVA_I2CM2_MIS (TIVA_I2C2_BASE + TIVA_I2CM_MIS_OFFSET)
#define TIVA_I2CM2_ICR (TIVA_I2C2_BASE + TIVA_I2CM_ICR_OFFSET)
#define TIVA_I2CM2_CR (TIVA_I2C2_BASE + TIVA_I2CM_CR_OFFSET)
/* I2C2 Slave */
#define TIVA_I2CS2_OAR (TIVA_I2C2_BASE + TIVA_I2CS_OAR_OFFSET)
#define TIVA_I2CS2_CSR (TIVA_I2C2_BASE + TIVA_I2CS_CSR_OFFSET)
#define TIVA_I2CS2_DR (TIVA_I2C2_BASE + TIVA_I2CS_DR_OFFSET)
#define TIVA_I2CS2_IMR (TIVA_I2C2_BASE + TIVA_I2CS_IMR_OFFSET)
#define TIVA_I2CS2_RIS (TIVA_I2C2_BASE + TIVA_I2CS_RIS_OFFSET)
#define TIVA_I2CS2_MIS (TIVA_I2C2_BASE + TIVA_I2CS_MIS_OFFSET)
#define TIVA_I2CS2_ICR (TIVA_I2C2_BASE + TIVA_I2CS_ICR_OFFSET)
#endif /* TIVA_NI2C > 2 */
#if TIVA_NI2C > 3
/* I2C3 Master */
#define TIVA_I2CM3_SA (TIVA_I2C3_BASE + TIVA_I2CM_SA_OFFSET)
#define TIVA_I2CM3_CS (TIVA_I2C3_BASE + TIVA_I2CM_CS_OFFSET)
#define TIVA_I2CM3_DR (TIVA_I2C3_BASE + TIVA_I2CM_DR_OFFSET)
#define TIVA_I2CM3_TPR (TIVA_I2C3_BASE + TIVA_I2CM_TPR_OFFSET)
#define TIVA_I2CM3_IMR (TIVA_I2C3_BASE + TIVA_I2CM_IMR_OFFSET)
#define TIVA_I2CM3_RIS (TIVA_I2C3_BASE + TIVA_I2CM_RIS_OFFSET)
#define TIVA_I2CM3_MIS (TIVA_I2C3_BASE + TIVA_I2CM_MIS_OFFSET)
#define TIVA_I2CM3_ICR (TIVA_I2C3_BASE + TIVA_I2CM_ICR_OFFSET)
#define TIVA_I2CM3_CR (TIVA_I2C3_BASE + TIVA_I2CM_CR_OFFSET)
/* I2C3 Slave */
#define TIVA_I2CS3_OAR (TIVA_I2C3_BASE + TIVA_I2CS_OAR_OFFSET)
#define TIVA_I2CS3_CSR (TIVA_I2C3_BASE + TIVA_I2CS_CSR_OFFSET)
#define TIVA_I2CS3_DR (TIVA_I2C3_BASE + TIVA_I2CS_DR_OFFSET)
#define TIVA_I2CS3_IMR (TIVA_I2C3_BASE + TIVA_I2CS_IMR_OFFSET)
#define TIVA_I2CS3_RIS (TIVA_I2C3_BASE + TIVA_I2CS_RIS_OFFSET)
#define TIVA_I2CS3_MIS (TIVA_I2C3_BASE + TIVA_I2CS_MIS_OFFSET)
#define TIVA_I2CS3_ICR (TIVA_I2C3_BASE + TIVA_I2CS_ICR_OFFSET)
#endif /* TIVA_NI2C > 3 */
#if TIVA_NI2C > 4
/* I2C4 Master */
#define TIVA_I2CM4_SA (TIVA_I2C4_BASE + TIVA_I2CM_SA_OFFSET)
#define TIVA_I2CM4_CS (TIVA_I2C4_BASE + TIVA_I2CM_CS_OFFSET)
#define TIVA_I2CM4_DR (TIVA_I2C4_BASE + TIVA_I2CM_DR_OFFSET)
#define TIVA_I2CM4_TPR (TIVA_I2C4_BASE + TIVA_I2CM_TPR_OFFSET)
#define TIVA_I2CM4_IMR (TIVA_I2C4_BASE + TIVA_I2CM_IMR_OFFSET)
#define TIVA_I2CM4_RIS (TIVA_I2C4_BASE + TIVA_I2CM_RIS_OFFSET)
#define TIVA_I2CM4_MIS (TIVA_I2C4_BASE + TIVA_I2CM_MIS_OFFSET)
#define TIVA_I2CM4_ICR (TIVA_I2C4_BASE + TIVA_I2CM_ICR_OFFSET)
#define TIVA_I2CM4_CR (TIVA_I2C4_BASE + TIVA_I2CM_CR_OFFSET)
/* I2C4 Slave */
#define TIVA_I2CS4_OAR (TIVA_I2C4_BASE + TIVA_I2CS_OAR_OFFSET)
#define TIVA_I2CS4_CSR (TIVA_I2C4_BASE + TIVA_I2CS_CSR_OFFSET)
#define TIVA_I2CS4_DR (TIVA_I2C4_BASE + TIVA_I2CS_DR_OFFSET)
#define TIVA_I2CS4_IMR (TIVA_I2C4_BASE + TIVA_I2CS_IMR_OFFSET)
#define TIVA_I2CS4_RIS (TIVA_I2C4_BASE + TIVA_I2CS_RIS_OFFSET)
#define TIVA_I2CS4_MIS (TIVA_I2C4_BASE + TIVA_I2CS_MIS_OFFSET)
#define TIVA_I2CS4_ICR (TIVA_I2C4_BASE + TIVA_I2CS_ICR_OFFSET)
#endif /* TIVA_NI2C > 4 */
#if TIVA_NI2C > 5
/* I2C5 Master */
#define TIVA_I2CM5_SA (TIVA_I2C5_BASE + TIVA_I2CM_SA_OFFSET)
#define TIVA_I2CM5_CS (TIVA_I2C5_BASE + TIVA_I2CM_CS_OFFSET)
#define TIVA_I2CM5_DR (TIVA_I2C5_BASE + TIVA_I2CM_DR_OFFSET)
#define TIVA_I2CM5_TPR (TIVA_I2C5_BASE + TIVA_I2CM_TPR_OFFSET)
#define TIVA_I2CM5_IMR (TIVA_I2C5_BASE + TIVA_I2CM_IMR_OFFSET)
#define TIVA_I2CM5_RIS (TIVA_I2C5_BASE + TIVA_I2CM_RIS_OFFSET)
#define TIVA_I2CM5_MIS (TIVA_I2C5_BASE + TIVA_I2CM_MIS_OFFSET)
#define TIVA_I2CM5_ICR (TIVA_I2C5_BASE + TIVA_I2CM_ICR_OFFSET)
#define TIVA_I2CM5_CR (TIVA_I2C5_BASE + TIVA_I2CM_CR_OFFSET)
/* I2C5 Slave */
#define TIVA_I2CS5_OAR (TIVA_I2C5_BASE + TIVA_I2CS_OAR_OFFSET)
#define TIVA_I2CS5_CSR (TIVA_I2C5_BASE + TIVA_I2CS_CSR_OFFSET)
#define TIVA_I2CS5_DR (TIVA_I2C5_BASE + TIVA_I2CS_DR_OFFSET)
#define TIVA_I2CS5_IMR (TIVA_I2C5_BASE + TIVA_I2CS_IMR_OFFSET)
#define TIVA_I2CS5_RIS (TIVA_I2C5_BASE + TIVA_I2CS_RIS_OFFSET)
#define TIVA_I2CS5_MIS (TIVA_I2C5_BASE + TIVA_I2CS_MIS_OFFSET)
#define TIVA_I2CS5_ICR (TIVA_I2C5_BASE + TIVA_I2CS_ICR_OFFSET)
#endif /* TIVA_NI2C > 5 */
#if TIVA_NI2C > 6
/* I2C6 Master */
#define TIVA_I2CM6_SA (TIVA_I2C6_BASE + TIVA_I2CM_SA_OFFSET)
#define TIVA_I2CM6_CS (TIVA_I2C6_BASE + TIVA_I2CM_CS_OFFSET)
#define TIVA_I2CM6_DR (TIVA_I2C6_BASE + TIVA_I2CM_DR_OFFSET)
#define TIVA_I2CM6_TPR (TIVA_I2C6_BASE + TIVA_I2CM_TPR_OFFSET)
#define TIVA_I2CM6_IMR (TIVA_I2C6_BASE + TIVA_I2CM_IMR_OFFSET)
#define TIVA_I2CM6_RIS (TIVA_I2C6_BASE + TIVA_I2CM_RIS_OFFSET)
#define TIVA_I2CM6_MIS (TIVA_I2C6_BASE + TIVA_I2CM_MIS_OFFSET)
#define TIVA_I2CM6_ICR (TIVA_I2C6_BASE + TIVA_I2CM_ICR_OFFSET)
#define TIVA_I2CM6_CR (TIVA_I2C6_BASE + TIVA_I2CM_CR_OFFSET)
/* I2C6 Slave */
#define TIVA_I2CS6_OAR (TIVA_I2C6_BASE + TIVA_I2CS_OAR_OFFSET)
#define TIVA_I2CS6_CSR (TIVA_I2C6_BASE + TIVA_I2CS_CSR_OFFSET)
#define TIVA_I2CS6_DR (TIVA_I2C6_BASE + TIVA_I2CS_DR_OFFSET)
#define TIVA_I2CS6_IMR (TIVA_I2C6_BASE + TIVA_I2CS_IMR_OFFSET)
#define TIVA_I2CS6_RIS (TIVA_I2C6_BASE + TIVA_I2CS_RIS_OFFSET)
#define TIVA_I2CS6_MIS (TIVA_I2C6_BASE + TIVA_I2CS_MIS_OFFSET)
#define TIVA_I2CS6_ICR (TIVA_I2C6_BASE + TIVA_I2CS_ICR_OFFSET)
#endif /* TIVA_NI2C > 5 */
#if TIVA_NI2C > 7
/* I2C7 Master */
#define TIVA_I2CM7_SA (TIVA_I2C7_BASE + TIVA_I2CM_SA_OFFSET)
#define TIVA_I2CM7_CS (TIVA_I2C7_BASE + TIVA_I2CM_CS_OFFSET)
#define TIVA_I2CM7_DR (TIVA_I2C7_BASE + TIVA_I2CM_DR_OFFSET)
#define TIVA_I2CM7_TPR (TIVA_I2C7_BASE + TIVA_I2CM_TPR_OFFSET)
#define TIVA_I2CM7_IMR (TIVA_I2C7_BASE + TIVA_I2CM_IMR_OFFSET)
#define TIVA_I2CM7_RIS (TIVA_I2C7_BASE + TIVA_I2CM_RIS_OFFSET)
#define TIVA_I2CM7_MIS (TIVA_I2C7_BASE + TIVA_I2CM_MIS_OFFSET)
#define TIVA_I2CM7_ICR (TIVA_I2C7_BASE + TIVA_I2CM_ICR_OFFSET)
#define TIVA_I2CM7_CR (TIVA_I2C7_BASE + TIVA_I2CM_CR_OFFSET)
/* I2C7 Slave */
#define TIVA_I2CS7_OAR (TIVA_I2C7_BASE + TIVA_I2CS_OAR_OFFSET)
#define TIVA_I2CS7_CSR (TIVA_I2C7_BASE + TIVA_I2CS_CSR_OFFSET)
#define TIVA_I2CS7_DR (TIVA_I2C7_BASE + TIVA_I2CS_DR_OFFSET)
#define TIVA_I2CS7_IMR (TIVA_I2C7_BASE + TIVA_I2CS_IMR_OFFSET)
#define TIVA_I2CS7_RIS (TIVA_I2C7_BASE + TIVA_I2CS_RIS_OFFSET)
#define TIVA_I2CS7_MIS (TIVA_I2C7_BASE + TIVA_I2CS_MIS_OFFSET)
#define TIVA_I2CS7_ICR (TIVA_I2C7_BASE + TIVA_I2CS_ICR_OFFSET)
#if TIVA_NI2C > 8
/* I2C8 Master */
#define TIVA_I2CM8_SA (TIVA_I2C8_BASE + TIVA_I2CM_SA_OFFSET)
#define TIVA_I2CM8_CS (TIVA_I2C8_BASE + TIVA_I2CM_CS_OFFSET)
#define TIVA_I2CM8_DR (TIVA_I2C8_BASE + TIVA_I2CM_DR_OFFSET)
#define TIVA_I2CM8_TPR (TIVA_I2C8_BASE + TIVA_I2CM_TPR_OFFSET)
#define TIVA_I2CM8_IMR (TIVA_I2C8_BASE + TIVA_I2CM_IMR_OFFSET)
#define TIVA_I2CM8_RIS (TIVA_I2C8_BASE + TIVA_I2CM_RIS_OFFSET)
#define TIVA_I2CM8_MIS (TIVA_I2C8_BASE + TIVA_I2CM_MIS_OFFSET)
#define TIVA_I2CM8_ICR (TIVA_I2C8_BASE + TIVA_I2CM_ICR_OFFSET)
#define TIVA_I2CM8_CR (TIVA_I2C8_BASE + TIVA_I2CM_CR_OFFSET)
/* I2C8 Slave */
#define TIVA_I2CS8_OAR (TIVA_I2C8_BASE + TIVA_I2CS_OAR_OFFSET)
#define TIVA_I2CS8_CSR (TIVA_I2C8_BASE + TIVA_I2CS_CSR_OFFSET)
#define TIVA_I2CS8_DR (TIVA_I2C8_BASE + TIVA_I2CS_DR_OFFSET)
#define TIVA_I2CS8_IMR (TIVA_I2C8_BASE + TIVA_I2CS_IMR_OFFSET)
#define TIVA_I2CS8_RIS (TIVA_I2C8_BASE + TIVA_I2CS_RIS_OFFSET)
#define TIVA_I2CS8_MIS (TIVA_I2C8_BASE + TIVA_I2CS_MIS_OFFSET)
#define TIVA_I2CS8_ICR (TIVA_I2C8_BASE + TIVA_I2CS_ICR_OFFSET)
#endif /* TIVA_NI2C > 5 */
#if TIVA_NI2C > 9
/* I2C9 Master */
#define TIVA_I2CM9_SA (TIVA_I2C9_BASE + TIVA_I2CM_SA_OFFSET)
#define TIVA_I2CM9_CS (TIVA_I2C9_BASE + TIVA_I2CM_CS_OFFSET)
#define TIVA_I2CM9_DR (TIVA_I2C9_BASE + TIVA_I2CM_DR_OFFSET)
#define TIVA_I2CM9_TPR (TIVA_I2C9_BASE + TIVA_I2CM_TPR_OFFSET)
#define TIVA_I2CM9_IMR (TIVA_I2C9_BASE + TIVA_I2CM_IMR_OFFSET)
#define TIVA_I2CM9_RIS (TIVA_I2C9_BASE + TIVA_I2CM_RIS_OFFSET)
#define TIVA_I2CM9_MIS (TIVA_I2C9_BASE + TIVA_I2CM_MIS_OFFSET)
#define TIVA_I2CM9_ICR (TIVA_I2C9_BASE + TIVA_I2CM_ICR_OFFSET)
#define TIVA_I2CM9_CR (TIVA_I2C9_BASE + TIVA_I2CM_CR_OFFSET)
/* I2C9 Slave */
#define TIVA_I2CS9_OAR (TIVA_I2C9_BASE + TIVA_I2CS_OAR_OFFSET)
#define TIVA_I2CS9_CSR (TIVA_I2C9_BASE + TIVA_I2CS_CSR_OFFSET)
#define TIVA_I2CS9_DR (TIVA_I2C9_BASE + TIVA_I2CS_DR_OFFSET)
#define TIVA_I2CS9_IMR (TIVA_I2C9_BASE + TIVA_I2CS_IMR_OFFSET)
#define TIVA_I2CS9_RIS (TIVA_I2C9_BASE + TIVA_I2CS_RIS_OFFSET)
#define TIVA_I2CS9_MIS (TIVA_I2C9_BASE + TIVA_I2CS_MIS_OFFSET)
#define TIVA_I2CS9_ICR (TIVA_I2C9_BASE + TIVA_I2CS_ICR_OFFSET)
#endif /* TIVA_NI2C > 5 */
/* I2C_Register Bit Definitions *****************************************************/
/* I2C Master Slave Address (I2CM_SA) */
#define I2CM_SA_RS (1 << 0) /* Bit 0: Receive/Send */
#define I2CM_SA_SA_SHIFT 1 /* Bits 7-1: I2C Slave Address */
#define I2CM_SA_SA_MASK (0x7f << I2CM_SA_SA_SHIFT)
/* I2C Master Control/Status (I2CM_CS) */
#define I2CM_CS_BUSY (1 << 0) /* Bit 0: I2C Busy (read) */
#define I2CM_CS_ERROR (1 << 1) /* Bit 1: Error in last bus operation (read) */
#define I2CM_CS_ADRACK (1 << 2) /* Bit 2: Acknowledge Address (read) */
#define I2CM_CS_DATACK (1 << 3) /* Bit 3: Acknowledge Data (read) */
#define I2CM_CS_ARBLST (1 << 4) /* Bit 4: Arbitration Lost (read) */
#define I2CM_CS_IDLE (1 << 5) /* Bit 5: I2C Idle (read) */
#define I2CM_CS_BUSBSY (1 << 6) /* Bit 6: Bus Busy (read) */
#define I2CM_CS_RUN (1 << 0) /* Bit 0: I2C Master Enable (write) */
#define I2CM_CS_START (1 << 1) /* Bit 1: Generate START (write) */
#define I2CM_CS_STOP (1 << 2) /* Bit 2: Generate STOP (write) */
#define I2CM_CS_ACK (1 << 3) /* Bit 3: Data Acknowledge Enable (write) */
/* I2C Master Data (I2CM_DR) */
#define I2CM_DR_SHIFT (0) /* Bits 7-0: Data transferred */
#define I2CM_DR_MASK (0xff << I2CM_DR_SHIFT)
/* I2C Master Timer Period (I2CM_TPR) */
#define I2CM_TPR_SHIFT (0) /* Bits 7-0: SCL Clock Period */
#define I2CM_TPR_MASK (0xff << I2CM_TPR_SHIFT)
/* I2C Master Interrupt Mask (I2CM_IMR) */
#define I2CM_IMR_MIM (1 << 0) /* Bit 0: Master Interrupt Mask */
/* I2C Master Raw Interrupt Status (I2CM_RIS) */
#define I2CM_RIS_MRIS (1 << 0) /* Bit 0: Master Raw Interrupt Status */
/* I2C Master Masked Interrupt Status (I2CM_MIS) */
#define I2CM_MIS_MMIS (1 << 0) /* Bit 0: Maseter Masked Interrupt Status */
/* I2C Master Masked Interrupt Status (I2CM_ICR) */
#define I2CM_ICR_MIC (1 << 0) /* Bit 0: Master Masked Interrupt Clear */
/* I2C Master Configuration (I2CM_CR) */
#define I2CM_CR_LPBK (1 << 0) /* Bit 0:: I2C Loopback */
#define I2CM_CR_MFE (1 << 4) /* Bit 4: I2C Master Function Enable */
#define I2CM_CR_SFE (1 << 5) /* Bit 5: I2C Slave Function Enable */
/* I2C Slave Own Address (I2CS_OAR) */
#define I2CS_OAR_MASK 0x7f /* Bits 6-0: I2C Slave Own Address */
/* I2C Slave Control/Status (I2CS_CSR) */
#define I2CS_CSR_RREQ (1 << 0) /* Bit 0: Receive Request (read) */
#define I2CS_CSR_TREQ (1 << 1) /* Bit 1: Transmit Request (read) */
#define I2CS_CSR_FBR (1 << 2) /* Bit 2: First Byte Received (read) */
#define I2CS_CSR_DA (1 << 0) /* Bit 0: Device Active (write) */
/* I2C Slave Data (I2CS_DR) */
#define I2CS_DR_SHIFT (0) /* Bits 7-0: Data for Transfer */
#define I2CS_DR_MASK (0xff << I2CS_DR_SHIFT)
/* I2C Slave Interrupt Mask (I2CS_IMR) */
#define I2CS_IMR_DATAIM (1 << 0) /* Bit 0: Data Interrupt Mask */
/* I2C Slave Raw Interrupt Status (I2CS_RIS) */
#define I2CS_RIS_DATARIS (1 << 0) /* Bit 0: Data Raw Interrupt Status */
/* I2C Slave Masked Interrupt Status (I2CS_MIS) */
#define I2CS_MIS_DATAMIS (1 << 0) /* Bit 0: Data Masked Interrupt Status */
/* I2C Slave Interrupt Clear (I2CS_ICR) */
#define I2CS_ICR_DATAIC (1 << 0) /* Bit 0: Data Interrupt Clear */
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_LM_LM_I2C_H */
arch/arm/src/tiva/hardware/tiva_i2c.h
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arch/arm/src/tiva/hardware/tm4c/tm4c123_i2c.h
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arch/arm/src/tiva/hardware/tm4c/tm4c129_i2c.h
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