diff --git a/arch/arm/src/c5471/c5471_serial.c b/arch/arm/src/c5471/c5471_serial.c index 0c1ef4a01ca..51e922f4998 100644 --- a/arch/arm/src/c5471/c5471_serial.c +++ b/arch/arm/src/c5471/c5471_serial.c @@ -71,7 +71,9 @@ struct up_dev_s unsigned int uartbase; /* Base address of UART registers */ unsigned int baud_base; /* Base baud for conversions */ unsigned int baud; /* Configured baud */ + uint8_t xmit_fifo_size; /* Size of transmit FIFO */ + uint8_t irq; /* IRQ associated with this UART */ uint8_t parity; /* 0=none, 1=odd, 2=even */ uint8_t bits; /* Number of bits (7 or 8) */ @@ -160,7 +162,7 @@ static uart_dev_t g_irdaport = { .size = CONFIG_UART_IRDA_TXBUFSIZE, .buffer = g_irdatxbuffer, - }, + }, .ops = &g_uart_ops, .priv = &g_irdapriv, }; @@ -227,7 +229,8 @@ static inline uint32_t up_inserial(struct up_dev_s *priv, uint32_t offset) * Name: up_serialout ****************************************************************************/ -static inline void up_serialout(struct up_dev_s *priv, uint32_t offset, uint32_t value) +static inline void up_serialout(struct up_dev_s *priv, + uint32_t offset, uint32_t value) { putreg32(value, priv->uartbase + offset); } @@ -242,6 +245,7 @@ static inline void up_disableuartint(struct up_dev_s *priv, uint16_t *ier) { *ier = priv->regs.ier & UART_IER_INTMASK; } + priv->regs.ier &= ~UART_IER_INTMASK; up_serialout(priv, UART_IER_OFFS, priv->regs.ier); } @@ -272,6 +276,7 @@ static inline void up_waittxready(struct up_dev_s *priv) } } } + /**************************************************************************** * Name: up_disablebreaks ****************************************************************************/ @@ -408,7 +413,7 @@ static int up_setup(struct uart_dev_s *dev) up_setrate(priv, priv->baud); - priv->regs.lcr &= 0xffffffe0; /* clear original field, and... */ + priv->regs.lcr &= 0xffffffe0; /* clear original field, and... */ priv->regs.lcr |= (uint32_t)cval; /* Set new bits in that field. */ up_serialout(priv, UART_LCR_OFFS, priv->regs.lcr); @@ -436,6 +441,7 @@ static int up_setup(struct uart_dev_s *dev) } #endif #endif + return OK; } @@ -457,14 +463,15 @@ static void up_shutdown(struct uart_dev_s *dev) * Name: up_attach * * Description: - * Configure the UART to operation in interrupt driven mode. This method is + * Configure the UART to operation in interrupt driven mode. This method is * called when the serial port is opened. Normally, this is just after the * the setup() method is called, however, the serial console may operate in * a non-interrupt driven mode during the boot phase. * - * RX and TX interrupts are not enabled when by the attach method (unless the - * hardware supports multiple levels of interrupt enabling). The RX and TX - * interrupts are not enabled until the txint() and rxint() methods are called. + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supports multiple levels of interrupt enabling). The RX and + * TX interrupts are not enabled until the txint() and rxint() methods are + * called. * ****************************************************************************/ @@ -493,8 +500,8 @@ static int up_attach(struct uart_dev_s *dev) * * Description: * Detach UART interrupts. This method is called when the serial port is - * closed normally just before the shutdown method is called. The exception is - * the serial console which is never shutdown. + * closed normally just before the shutdown method is called. The exception + * is the serial console which is never shutdown. * ****************************************************************************/ diff --git a/arch/arm/src/c5471/c5471_timerisr.c b/arch/arm/src/c5471/c5471_timerisr.c index 62df889171c..ea94ea44ca8 100644 --- a/arch/arm/src/c5471/c5471_timerisr.c +++ b/arch/arm/src/c5471/c5471_timerisr.c @@ -98,7 +98,7 @@ void up_timer_initialize(void) * so that an interrupt is generated at the rate USEC_PER_TICK. */ - val = ((CLKS_PER_INT-1) << CLKS_PER_INT_SHIFT) | AR | ST | PTV; + val = ((CLKS_PER_INT - 1) << CLKS_PER_INT_SHIFT) | AR | ST | PTV; putreg32(val, C5471_TIMER2_CTRL); /* Attach and enable the timer interrupt */ diff --git a/arch/arm/src/c5471/c5471_vectors.S b/arch/arm/src/c5471/c5471_vectors.S index 8909db2a21f..f60f78aed27 100644 --- a/arch/arm/src/c5471/c5471_vectors.S +++ b/arch/arm/src/c5471/c5471_vectors.S @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/c5471/c5471_vectors.S * * Licensed to the Apache Software Foundation (ASF) under one or more @@ -16,11 +16,11 @@ * License for the specific language governing permissions and limitations * under the License. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include #include @@ -29,13 +29,13 @@ #include "chip.h" #include "arm_arch.h" -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ .data g_irqtmp: @@ -48,29 +48,29 @@ g_aborttmp: .word 0 /* Saved lr */ .word 0 /* Saved spsr */ -/************************************************************************************ +/**************************************************************************** * Assembly Macros - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ .text -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ .text -/************************************************************************************ +/**************************************************************************** * Name: arm_vectorirq * * Description: * Interrupt exception. Entered in IRQ mode with spsr = SVC * CPSR, lr = SVC PC - ************************************************************************************/ + ****************************************************************************/ .globl arm_vectorirq .type arm_vectorirq, %function @@ -168,12 +168,12 @@ arm_vectorirq: #endif .align 5 -/************************************************************************************ +/**************************************************************************** * Function: arm_vectorswi * * Description: * SWI interrupt. We enter the SWI in SVC mode - ************************************************************************************/ + ****************************************************************************/ .globl arm_vectorswi .type arm_vectorswi, %function @@ -221,7 +221,7 @@ arm_vectorswi: .align 5 -/************************************************************************************ +/**************************************************************************** * Name: arm_vectordata * * Description: @@ -229,7 +229,7 @@ arm_vectorswi: * abort handler. This function is entered in ABORT mode * with spsr = SVC CPSR, lr = SVC PC * - ************************************************************************************/ + ****************************************************************************/ .globl arm_vectordata .type arm_vectordata, %function @@ -289,13 +289,13 @@ arm_vectordata: .align 5 -/************************************************************************************ +/**************************************************************************** * Name: arm_vectorprefetch * * Description: * Prefetch abort exception. Entered in ABT mode with * spsr = SVC CPSR, lr = SVC PC - ************************************************************************************/ + ****************************************************************************/ .globl arm_vectorprefetch .type arm_vectorprefetch, %function @@ -355,14 +355,14 @@ arm_vectorprefetch: .align 5 -/************************************************************************************ +/**************************************************************************** * Name: arm_vectorundefinsn * * Description: * Undefined instruction entry exception. Entered in * UND mode, spsr = SVC CPSR, lr = SVC PC * - ************************************************************************************/ + ****************************************************************************/ .globl arm_vectorundefinsn .type arm_vectorundefinsn, %function @@ -421,38 +421,38 @@ arm_vectorundefinsn: .align 5 -/************************************************************************************ +/**************************************************************************** * Name: arm_vectorfiq * * Description: * Shouldn't happen - ************************************************************************************/ + ****************************************************************************/ .globl arm_vectorfiq .type arm_vectorfiq, %function arm_vectorfiq: subs pc, lr, #4 -/************************************************************************************ +/**************************************************************************** * Name: up_vectoraddrexcption * * Description: * Shouldn't happen * - ************************************************************************************/ + ****************************************************************************/ .globl arm_vectoraddrexcptn .type arm_vectoraddrexcptn, %function arm_vectoraddrexcptn: b arm_vectoraddrexcptn -/************************************************************************************ +/**************************************************************************** * Name: g_intstackalloc/g_intstackbase * * Description: * Shouldn't happen * - ************************************************************************************/ + ****************************************************************************/ #if CONFIG_ARCH_INTERRUPTSTACK > 3 .bss diff --git a/arch/arm/src/c5471/chip.h b/arch/arm/src/c5471/chip.h index c9ed5b8d615..647b15e42b2 100644 --- a/arch/arm/src/c5471/chip.h +++ b/arch/arm/src/c5471/chip.h @@ -148,6 +148,7 @@ #define UART_IRDA_XMIT_FIFO_SIZE 64 /* UART_LCR Register */ + /* Bits 31-7: Reserved */ #define UART_LCR_BOC 0x00000040 /* Bit 6: Break Control */ /* Bit 5: Parity Type 2 */ @@ -203,39 +204,39 @@ #define GIO_REGISTER_BASE 0xffff2800 #define GPIO_IO 0xffff2800 /* Writeable when I/O is configured - * as an output; reads value on I/O - * pin when I/O is configured as an - * input */ + * as an output; reads value on I/O + * pin when I/O is configured as an + * input */ #define GPIO_CIO 0xffff2804 /* GPIO configuration register */ #define GPIO_IRQA 0xffff2808 /* In conjunction with GPIO_IRQB - * determines the behavior when GPIO - * pins configured as input IRQ */ + * determines the behavior when GPIO + * pins configured as input IRQ */ #define GPIO_IRQB 0xffff280c /* Determines the behavior when GPIO - * pins configured as input IRQ */ + * pins configured as input IRQ */ #define GPIO_DDIO 0xffff2810 /* Delta Detect Register - * (detects changes in the I/O pins) */ + * (detects changes in the I/O pins) */ #define GPIO_EN 0xffff2814 /* Selects register for muxed GPIOs */ #define KGIO_REGISTER_BASE 0xffff2900 #define KBGPIO_IO 0xffff2900 /* Keyboard I/O bits: Writeable - * when KBGPIO is configured as an - * output; reads value on I/O pin - * when KBGPIO is configured as an - * input */ + * when KBGPIO is configured as an + * output; reads value on I/O pin + * when KBGPIO is configured as an + * input */ #define KBGPIO_CIO 0xffff2904 /* KBGPIO configuration register */ #define KBGPIO_IRQA 0xffff2908 /* In conjunction with KBGPIO_IRQB - * determines the behavior when - * KBGPIO pins configured as input - * IRQ */ + * determines the behavior when + * KBGPIO pins configured as input + * IRQ */ #define KBGPIO_IRQB 0xffff290c /* In conjunction with KBGPIO_IRQA - * determines the behavior when - * KBGPIO pins configured as input - * IRQ */ + * determines the behavior when + * KBGPIO pins configured as input + * IRQ */ #define KBGPIO_DDIO 0xffff2910 /* Delta Detect Register (detects - * changes in the KBGPIO pins) */ + * changes in the KBGPIO pins) */ #define KBGPIO_EN 0xffff2914 /* Selects register for muxed - * KBGPIOs */ + * KBGPIOs */ /* Timers *******************************************************************/