From d1ac44242fc2930d20e74f083b50a32eb78027c4 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Sat, 21 Sep 2013 15:47:00 -0600 Subject: [PATCH] ARMv7-A: Fix some error in alignment to cache line boundaries in the cache operations --- arch/arm/src/armv7-a/cp15_clean_dcache.S | 2 +- arch/arm/src/armv7-a/cp15_flush_dcache.S | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/armv7-a/cp15_clean_dcache.S b/arch/arm/src/armv7-a/cp15_clean_dcache.S index fdc7513ede8..6a244dac9ed 100755 --- a/arch/arm/src/armv7-a/cp15_clean_dcache.S +++ b/arch/arm/src/armv7-a/cp15_clean_dcache.S @@ -99,7 +99,7 @@ cp15_clean_dcache: mov r2, r2, lsl r3 /* Get the cache line size in bytes */ sub r3, r2, #1 /* R3=Cache line size mask */ - bic r12, r0, r3 /* R12=aligned start address */ + bic r0, r0, r3 /* R0=aligned start address */ /* Loop, cleaning each cache line by writing its contents to memory */ diff --git a/arch/arm/src/armv7-a/cp15_flush_dcache.S b/arch/arm/src/armv7-a/cp15_flush_dcache.S index 2e21db5981c..ba5b753badd 100755 --- a/arch/arm/src/armv7-a/cp15_flush_dcache.S +++ b/arch/arm/src/armv7-a/cp15_flush_dcache.S @@ -99,7 +99,7 @@ cp15_flush_dcache: mov r2, r2, lsl r3 /* Get the cache line size in bytes */ sub r3, r2, #1 /* R3=Cache line size mask */ - bic r12, r0, r3 /* R12=aligned start address */ + bic r0, r0, r3 /* R0=aligned start address */ /* Loop, cleaning and invaliding each D cache line in the address range */