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Remove the configs/ directory
This commit is contained in:
Gregory Nutt
@@ -1,109 +0,0 @@
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# NXP LPC1766 Cortex-M3 with 256kB Flash and 32kB+32kB Local On-Chip SRAM,
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#daemon configuration
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telnet_port 4444
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gdb_port 3333
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#interface
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interface ft2232
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ft2232_device_desc "Olimex OpenOCD JTAG A"
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ft2232_layout "olimex-jtag"
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ft2232_vid_pid 0x15BA 0x0003
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# LPC17xx chips support both JTAG and SWD transports.
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# Adapt based on what transport is active.
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source [find target/swj-dp.tcl]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME lpc1766
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}
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# After reset the chip is clocked by the ~4MHz internal RC oscillator.
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# When board-specific code (reset-init handler or device firmware)
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# configures another oscillator and/or PLL0, set CCLK to match; if
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# you don't, then flash erase and write operations may misbehave.
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# (The ROM code doing those updates cares about core clock speed...)
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#
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# CCLK is the core clock frequency in KHz
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if { [info exists CCLK ] } {
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set _CCLK $CCLK
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} else {
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set _CCLK 4000
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0x4ba00477
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}
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if { [info exists CPURAMSIZE] } {
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set _CPURAMSIZE $CPURAMSIZE
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} else {
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set _CPURAMSIZE 0x8000
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}
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if { [info exists CPUROMSIZE] } {
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set _CPUROMSIZE $CPUROMSIZE
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} else {
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set _CPUROMSIZE 0x40000
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}
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#delays on reset lines
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adapter_nsrst_delay 200
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jtag_ntrst_delay 200
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# LPC2000 & LPC1700 -> SRST causes TRST
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reset_config trst_and_srst srst_pulls_trst
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#swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
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jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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# openocd-0.4:
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# target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME
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# openocd-0.7:
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target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
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# LPC1766 has 32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000)
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# and 32K more on AHB, in the ARMv7-M "SRAM" area, (at 0x2007c000).
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$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE
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# LPC1766 has 256kB of flash memory, managed by ROM code (including a
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# boot loader which verifies the flash exception table's checksum).
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# flash bank <name> lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc checksum]
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME lpc2000 0x0 $_CPUROMSIZE 0 0 $_TARGETNAME \
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lpc1700 $_CCLK calc_checksum
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# Run with *real slow* clock by default since the
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# boot rom could have been playing with the PLL, so
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# we have no idea what clock the target is running at.
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# openocd-0.4:
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# jtag_khz 100
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# openocd-0.7
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adapter_khz 100
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$_TARGETNAME configure -event reset-init {
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# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
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# "User Flash Mode" where interrupt vectors are _not_ remapped,
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# and reside in flash instead).
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#
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# See Table 612. Memory Mapping Control register (MEMMAP - 0x400F C040) bit description
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# Bit Symbol Value Description Reset
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# value
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# 0 MAP Memory map control. 0
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# 0 Boot mode. A portion of the Boot ROM is mapped to address 0.
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# 1 User mode. The on-chip Flash memory is mapped to address 0.
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# 31:1 - Reserved. The value read from a reserved bit is not defined. NA
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#
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# http://ics.nxp.com/support/documents/microcontrollers/?scope=LPC1766&type=user
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mww 0x400FC040 0x01
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}
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# if srst is not fitted use VECTRESET to
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# perform a soft reset - SYSRESETREQ is not supported
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# openocd-0.7:
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cortex_m reset_config vectreset
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@@ -1,52 +0,0 @@
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#!/bin/sh
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#
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# See configs/olimex-lpc1766stk/README.txt for information about
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# this file.
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TOPDIR=$1
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USAGE="$0 <TOPDIR> [-d]"
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if [ -z "${TOPDIR}" ]; then
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echo "Missing argument"
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echo $USAGE
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exit 1
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fi
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# Assume that OpenOCD was installed and at /usr/local/bin or maybe c:\OpenOCD
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#OPENOCD_PATH="/cygdrive/c/OpenOCD/openocd-0.4.0/src"
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#TARGET_PATH="c:\OpenOCD\openocd-0.4.0\tcl"
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OPENOCD_PATH="/usr/local/bin"
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TARGET_PATH="/usr/local/share/openocd/scripts"
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OPENOCD_EXE=openocd.exe
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#OPENOCD_CFG=`cygpath -w "${TOPDIR}/configs/olimex-lpc1766stk/tools/olimex.cfg"`
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OPENOCD_CFG="${TOPDIR}/configs/olimex-lpc1766stk/tools/olimex.cfg"
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OPENOCD_ARGS="-f ${OPENOCD_CFG} -s ${TARGET_PATH}"
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if [ "X$2" = "X-d" ]; then
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OPENOCD_ARGS=$OPENOCD_ARGS" -d3"
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set -x
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fi
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if [ ! -d ${OPENOCD_PATH} ]; then
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echo "OpenOCD path does not exist: ${OPENOCD_PATH}"
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exit 1
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fi
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if [ ! -x ${OPENOCD_PATH}/${OPENOCD_EXE} ]; then
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echo "OpenOCD does not exist: ${OPENOCD_PATH}/${OPENOCD_EXE}"
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exit 1
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fi
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if [ ! -f ${OPENOCD_CFG} ]; then
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echo "OpenOCD config file does not exist: ${OPENOCD_CFG}"
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exit 1
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fi
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echo "Starting OpenOCD"
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cd ${OPENOCD_PATH} || { echo "Failed to CD to ${OPENOCD_PATH}"; exit 1; }
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${OPENOCD_EXE} ${OPENOCD_ARGS} &
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echo "OpenOCD daemon started"
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ps -ef | grep openocd
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echo "In GDB: target remote localhost:3333"
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@@ -1,25 +0,0 @@
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https://www.olimex.com/dev/pdf/ARM/JTAG/Repair%20Procedure%20for%20OpenOcd-Rev.%20G%20drivers.pdf
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Repair procedure for ARM-USB-OCD drivers
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1. Uninstalling ARM-USB-OCD drivers
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-------------------------------------
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1.1. Connect your programmer/debugger to your computer, open Device Manager
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and uninstall the drivers for ARM-USB-OCD.
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1.2. After you have uninstalled ARM-USB-TINY driver from Device Manager,
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disconnect the programmer from your computer.
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1.3. Now you should download FTClean.exe from here:
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http://www.ftdichip.com/Support/Utilities/FTClean.zip.
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1.4. After download is complete extract the "*.zip" file, open folder FTClean,
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and run FTClean.exe
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1.5. Ror VID (Hex) select "Other". And after that fill the first box with 15ba
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and "PID (Hex)" with 0004.
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1.6. Press "Clean System" button. Make sure that all FTDI devices are
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disconnected. (My require administrator privileges).
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2. Re-installing the ARM-USB-OCD driver
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---------------------------------------
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2.1 Connect the programmer/debugger to the computer.
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2.2 When prompted, browse to the C:\gccfd\DRIVERS\ARM-USB-OCD-DRIVER
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directory and install. (A different driver is required for OpenOCD
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0.4.0. That driver is available from the olimex.com web site).
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