diff --git a/arch/arm/include/armv7-m/irq.h b/arch/arm/include/armv7-m/irq.h index ef9b05b9127..061b6194dcb 100644 --- a/arch/arm/include/armv7-m/irq.h +++ b/arch/arm/include/armv7-m/irq.h @@ -49,7 +49,7 @@ #include #ifndef __ASSEMBLY__ # include -# include +# include # include #endif @@ -61,10 +61,6 @@ # include #endif -#ifdef CONFIG_ARMV7M_USEBASEPRI -# include -#endif - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/arch/arm/include/armv7-m/nvicpri.h b/arch/arm/include/armv7-m/nvicpri.h new file mode 100644 index 00000000000..540b095c20a --- /dev/null +++ b/arch/arm/include/armv7-m/nvicpri.h @@ -0,0 +1,100 @@ +/************************************************************************************ + * arch/arm/include/rmv7-m/nvicpri.h + * + * Copyright (C) 2009, 2011-2014, 2017-2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Dave Marples + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_ARM7_M_NVICPRI_H +#define __ARCH_ARM_INCLUDE_ARM7_M_NVICPRI_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled + * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most + * interrupts will not have execution priority. SVCall must have execution + * priority in all cases. + * + * In the normal cases, interrupts are not nest-able and all interrupts run + * at an execution priority between NVIC_SYSH_PRIORITY_MIN and + * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). + * + * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special + * high priority interrupts are supported. These are not "nested" in the + * normal sense of the word. These high priority interrupts can interrupt + * normal processing but execute outside of OS (although they can "get back + * into the game" via a PendSV interrupt). + * + * In the normal course of things, interrupts must occasionally be disabled + * using the up_irq_save() inline function to prevent contention in use of + * resources that may be shared between interrupt level and non-interrupt + * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, + * do we disable all interrupts (except SVCall), or do we only disable the + * "normal" interrupts. Since the high priority interrupts cannot interact + * with the OS, you may want to permit the high priority interrupts even if + * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be + * used to select either behavior: + * + * ----------------------------+--------------+---------------------------- + * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES + * ----------------------------+--------------+--------------+------------- + * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO + * ----------------------------+--------------+--------------+------------- + * | | | SVCall + * | SVCall | SVCall | HIGH + * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL + * | | MAXNORMAL | + * ----------------------------+--------------+--------------+------------- + * + */ + +#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) +# define NVIC_SYSH_MAXNORMAL_PRIORITY NVIC_SYSH_PRIORITY_DEFAULT +# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_DEFAULT - 1*NVIC_SYSH_PRIORITY_STEP) +# define NVIC_SYSH_DISABLE_PRIORITY (NVIC_SYSH_PRIORITY_DEFAULT - 1*NVIC_SYSH_PRIORITY_STEP) +# define NVIC_SYSH_SVCALL_PRIORITY (NVIC_SYSH_PRIORITY_DEFAULT - 2*NVIC_SYSH_PRIORITY_STEP) +#else +# define NVIC_SYSH_MAXNORMAL_PRIORITY NVIC_SYSH_PRIORITY_DEFAULT +# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_DEFAULT - 1*NVIC_SYSH_PRIORITY_STEP) +# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_PRIORITY_DEFAULT +# define NVIC_SYSH_SVCALL_PRIORITY (NVIC_SYSH_PRIORITY_DEFAULT - 1*NVIC_SYSH_PRIORITY_STEP) +#endif + +#endif /* __ARCH_ARM_INCLUDE_ARM7_M_NVICPRI_H */ diff --git a/arch/arm/include/efm32/chip.h b/arch/arm/include/efm32/chip.h index 2b73f7844fd..3559dfed0f5 100644 --- a/arch/arm/include/efm32/chip.h +++ b/arch/arm/include/efm32/chip.h @@ -77,53 +77,4 @@ #define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ #define NVIC_SYSH_PRIORITY_STEP 0x20 /* Three bits of interrupt priority used */ -/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled - * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most - * interrupts will not have execution priority. SVCall must have execution - * priority in all cases. - * - * In the normal cases, interrupts are not nest-able and all interrupts run - * at an execution priority between NVIC_SYSH_PRIORITY_MIN and - * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). - * - * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special - * high priority interrupts are supported. These are not "nested" in the - * normal sense of the word. These high priority interrupts can interrupt - * normal processing but execute outside of OS (although they can "get back - * into the game" via a PendSV interrupt). - * - * In the normal course of things, interrupts must occasionally be disabled - * using the up_irq_save() inline function to prevent contention in use of - * resources that may be shared between interrupt level and non-interrupt - * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, - * do we disable all interrupts (except SVCall), or do we only disable the - * "normal" interrupts. Since the high priority interrupts cannot interact - * with the OS, you may want to permit the high priority interrupts even if - * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be - * used to select either behavior: - * - * ----------------------------+--------------+---------------------------- - * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES - * ----------------------------+--------------+--------------+------------- - * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO - * ----------------------------+--------------+--------------+------------- - * | | | SVCall - * | SVCall | SVCall | HIGH - * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL - * | | MAXNORMAL | - * ----------------------------+--------------+--------------+------------- - */ - -#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#else -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#endif - #endif /* __ARCH_ARM_INCLUDE_EFM32_CHIP_H */ diff --git a/arch/arm/include/imxrt/chip.h b/arch/arm/include/imxrt/chip.h index 5229ab93ef9..b2942107806 100644 --- a/arch/arm/include/imxrt/chip.h +++ b/arch/arm/include/imxrt/chip.h @@ -89,55 +89,6 @@ #define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ #define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ -/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled - * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most - * interrupts will not have execution priority. SVCall must have execution - * priority in all cases. - * - * In the normal cases, interrupts are not nest-able and all interrupts run - * at an execution priority between NVIC_SYSH_PRIORITY_MIN and - * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). - * - * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special - * high priority interrupts are supported. These are not "nested" in the - * normal sense of the word. These high priority interrupts can interrupt - * normal processing but execute outside of OS (although they can "get back - * into the game" via a PendSV interrupt). - * - * In the normal course of things, interrupts must occasionally be disabled - * using the up_irq_save() inline function to prevent contention in use of - * resources that may be shared between interrupt level and non-interrupt - * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, - * do we disable all interrupts (except SVCall), or do we only disable the - * "normal" interrupts. Since the high priority interrupts cannot interact - * with the OS, you may want to permit the high priority interrupts even if - * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be - * used to select either behavior: - * - * ----------------------------+--------------+---------------------------- - * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES - * ----------------------------+--------------+--------------+------------- - * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO - * ----------------------------+--------------+--------------+------------- - * | | | SVCall - * | SVCall | SVCall | HIGH - * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL - * | | MAXNORMAL | - * ----------------------------+--------------+--------------+------------- - */ - -#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#else -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#endif - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/include/kinetis/chip.h b/arch/arm/include/kinetis/chip.h index d201ff32523..a36e09e8e92 100644 --- a/arch/arm/include/kinetis/chip.h +++ b/arch/arm/include/kinetis/chip.h @@ -1608,55 +1608,6 @@ #define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ #define NVIC_SYSH_PRIORITY_STEP 0x10 /* Steps between supported priority values */ -/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled - * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most - * interrupts will not have execution priority. SVCall must have execution - * priority in all cases. - * - * In the normal cases, interrupts are not nest-able and all interrupts run - * at an execution priority between NVIC_SYSH_PRIORITY_MIN and - * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). - * - * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special - * high priority interrupts are supported. These are not "nested" in the - * normal sense of the word. These high priority interrupts can interrupt - * normal processing but execute outside of OS (although they can "get back - * into the game" via a PendSV interrupt). - * - * In the normal course of things, interrupts must occasionally be disabled - * using the up_irq_save() inline function to prevent contention in use of - * resources that may be shared between interrupt level and non-interrupt - * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, - * do we disable all interrupts (except SVCall), or do we only disable the - * "normal" interrupts. Since the high priority interrupts cannot interact - * with the OS, you may want to permit the high priority interrupts even if - * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be - * used to select either behavior: - * - * ----------------------------+--------------+---------------------------- - * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES - * ----------------------------+--------------+--------------+------------- - * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO - * ----------------------------+--------------+--------------+------------- - * | | | SVCall - * | SVCall | SVCall | HIGH - * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL - * | | MAXNORMAL | - * ----------------------------+--------------+--------------+------------- - */ - -#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#else -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#endif - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/include/lc823450/chip.h b/arch/arm/include/lc823450/chip.h index 0aaee76864d..bbf82dc107f 100644 --- a/arch/arm/include/lc823450/chip.h +++ b/arch/arm/include/lc823450/chip.h @@ -54,55 +54,6 @@ #define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ #define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ -/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled - * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most - * interrupts will not have execution priority. SVCall must have execution - * priority in all cases. - * - * In the normal cases, interrupts are not nest-able and all interrupts run - * at an execution priority between NVIC_SYSH_PRIORITY_MIN and - * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). - * - * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special - * high priority interrupts are supported. These are not "nested" in the - * normal sense of the word. These high priority interrupts can interrupt - * normal processing but execute outside of OS (although they can "get back - * into the game" via a PendSV interrupt). - * - * In the normal course of things, interrupts must occasionally be disabled - * using the irqsave() inline function to prevent contention in use of - * resources that may be shared between interrupt level and non-interrupt - * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, - * do we disable all interrupts (except SVCall), or do we only disable the - * "normal" interrupts. Since the high priority interrupts cannot interact - * with the OS, you may want to permit the high priority interrupts even if - * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be - * used to select either behavior: - * - * ----------------------------+--------------+---------------------------- - * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES - * ----------------------------+--------------+--------------+------------- - * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO - * ----------------------------+--------------+--------------+------------- - * | | | SVCall - * | SVCall | SVCall | HIGH - * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL - * | | MAXNORMAL | - * ----------------------------+--------------+--------------+------------- - */ - -#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#else -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#endif - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/include/lpc11xx/chip.h b/arch/arm/include/lpc11xx/chip.h index 1c381df7d96..7d287d325f0 100644 --- a/arch/arm/include/lpc11xx/chip.h +++ b/arch/arm/include/lpc11xx/chip.h @@ -77,55 +77,6 @@ #define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ #define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ -/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled - * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most - * interrupts will not have execution priority. SVCall must have execution - * priority in all cases. - * - * In the normal cases, interrupts are not nest-able and all interrupts run - * at an execution priority between NVIC_SYSH_PRIORITY_MIN and - * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). - * - * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special - * high priority interrupts are supported. These are not "nested" in the - * normal sense of the word. These high priority interrupts can interrupt - * normal processing but execute outside of OS (although they can "get back - * into the game" via a PendSV interrupt). - * - * In the normal course of things, interrupts must occasionally be disabled - * using the up_irq_save() inline function to prevent contention in use of - * resources that may be shared between interrupt level and non-interrupt - * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, - * do we disable all interrupts (except SVCall), or do we only disable the - * "normal" interrupts. Since the high priority interrupts cannot interact - * with the OS, you may want to permit the high priority interrupts even if - * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be - * used to select either behavior: - * - * ----------------------------+--------------+---------------------------- - * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES - * ----------------------------+--------------+--------------+------------- - * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO - * ----------------------------+--------------+--------------+------------- - * | | | SVCall - * | SVCall | SVCall | HIGH - * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL - * | | MAXNORMAL | - * ----------------------------+--------------+--------------+------------- - */ - -#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#else -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#endif - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/include/lpc17xx/chip.h b/arch/arm/include/lpc17xx/chip.h index 5eebd0f7bf5..91b15abad69 100644 --- a/arch/arm/include/lpc17xx/chip.h +++ b/arch/arm/include/lpc17xx/chip.h @@ -373,55 +373,6 @@ #define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ #define NVIC_SYSH_PRIORITY_STEP 0x08 /* Five bits of interrupt priority used */ -/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled - * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most - * interrupts will not have execution priority. SVCall must have execution - * priority in all cases. - * - * In the normal cases, interrupts are not nest-able and all interrupts run - * at an execution priority between NVIC_SYSH_PRIORITY_MIN and - * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). - * - * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special - * high priority interrupts are supported. These are not "nested" in the - * normal sense of the word. These high priority interrupts can interrupt - * normal processing but execute outside of OS (although they can "get back - * into the game" via a PendSV interrupt). - * - * In the normal course of things, interrupts must occasionally be disabled - * using the up_irq_save() inline function to prevent contention in use of - * resources that may be shared between interrupt level and non-interrupt - * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, - * do we disable all interrupts (except SVCall), or do we only disable the - * "normal" interrupts. Since the high priority interrupts cannot interact - * with the OS, you may want to permit the high priority interrupts even if - * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be - * used to select either behavior: - * - * ----------------------------+--------------+---------------------------- - * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES - * ----------------------------+--------------+--------------+------------- - * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO - * ----------------------------+--------------+--------------+------------- - * | | | SVCall - * | SVCall | SVCall | HIGH - * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL - * | | MAXNORMAL | - * ----------------------------+--------------+--------------+------------- - */ - -#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#else -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#endif - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/include/lpc43xx/chip.h b/arch/arm/include/lpc43xx/chip.h index 3729ff8f81f..d8e4b32a36c 100644 --- a/arch/arm/include/lpc43xx/chip.h +++ b/arch/arm/include/lpc43xx/chip.h @@ -713,55 +713,6 @@ #define NVIC_SYSH_PRIORITY_MAX LPC43M4_SYSH_PRIORITY_MAX #define NVIC_SYSH_PRIORITY_STEP LPC43M4_SYSH_PRIORITY_STEP -/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled - * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most - * interrupts will not have execution priority. SVCall must have execution - * priority in all cases. - * - * In the normal cases, interrupts are not nest-able and all interrupts run - * at an execution priority between NVIC_SYSH_PRIORITY_MIN and - * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). - * - * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special - * high priority interrupts are supported. These are not "nested" in the - * normal sense of the word. These high priority interrupts can interrupt - * normal processing but execute outside of OS (although they can "get back - * into the game" via a PendSV interrupt). - * - * In the normal course of things, interrupts must occasionally be disabled - * using the up_irq_save() inline function to prevent contention in use of - * resources that may be shared between interrupt level and non-interrupt - * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, - * do we disable all interrupts (except SVCall), or do we only disable the - * "normal" interrupts. Since the high priority interrupts cannot interact - * with the OS, you may want to permit the high priority interrupts even if - * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be - * used to select either behavior: - * - * ----------------------------+--------------+---------------------------- - * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES - * ----------------------------+--------------+--------------+------------- - * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO - * ----------------------------+--------------+--------------+------------- - * | | | SVCall - * | SVCall | SVCall | HIGH - * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL - * | | MAXNORMAL | - * ----------------------------+--------------+--------------+------------- - */ - -#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#else -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#endif - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/include/lpc54xx/chip.h b/arch/arm/include/lpc54xx/chip.h index 962dc0300f9..e1b9fb6b950 100644 --- a/arch/arm/include/lpc54xx/chip.h +++ b/arch/arm/include/lpc54xx/chip.h @@ -70,55 +70,6 @@ #define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ #define NVIC_SYSH_PRIORITY_STEP 0x20 /* Steps between priorities */ -/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled - * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most - * interrupts will not have execution priority. SVCall must have execution - * priority in all cases. - * - * In the normal cases, interrupts are not nest-able and all interrupts run - * at an execution priority between NVIC_SYSH_PRIORITY_MIN and - * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). - * - * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special - * high priority interrupts are supported. These are not "nested" in the - * normal sense of the word. These high priority interrupts can interrupt - * normal processing but execute outside of OS (although they can "get back - * into the game" via a PendSV interrupt). - * - * In the normal course of things, interrupts must occasionally be disabled - * using the up_irq_save() inline function to prevent contention in use of - * resources that may be shared between interrupt level and non-interrupt - * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, - * do we disable all interrupts (except SVCall), or do we only disable the - * "normal" interrupts. Since the high priority interrupts cannot interact - * with the OS, you may want to permit the high priority interrupts even if - * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be - * used to select either behavior: - * - * ----------------------------+--------------+---------------------------- - * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES - * ----------------------------+--------------+--------------+------------- - * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO - * ----------------------------+--------------+--------------+------------- - * | | | SVCall - * | SVCall | SVCall | HIGH - * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL - * | | MAXNORMAL | - * ----------------------------+--------------+--------------+------------- - */ - -#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#else -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#endif - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/include/max326xx/chip.h b/arch/arm/include/max326xx/chip.h index 668df0ec02b..09036769a5f 100644 --- a/arch/arm/include/max326xx/chip.h +++ b/arch/arm/include/max326xx/chip.h @@ -200,55 +200,6 @@ #define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ #define NVIC_SYSH_PRIORITY_STEP 0x20 /* Eight priority levels in steps 0x20 */ -/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled - * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most - * interrupts will not have execution priority. SVCall must have execution - * priority in all cases. - * - * In the normal cases, interrupts are not nest-able and all interrupts run - * at an execution priority between NVIC_SYSH_PRIORITY_MIN and - * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). - * - * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special - * high priority interrupts are supported. These are not "nested" in the - * normal sense of the word. These high priority interrupts can interrupt - * normal processing but execute outside of OS (although they can "get back - * into the game" via a PendSV interrupt). - * - * In the normal course of things, interrupts must occasionally be disabled - * using the up_irq_save() inline function to prevent contention in use of - * resources that may be shared between interrupt level and non-interrupt - * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, - * do we disable all interrupts (except SVCall), or do we only disable the - * "normal" interrupts. Since the high priority interrupts cannot interact - * with the OS, you may want to permit the high priority interrupts even if - * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be - * used to select either behavior: - * - * ----------------------------+--------------+---------------------------- - * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES - * ----------------------------+--------------+--------------+------------- - * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO - * ----------------------------+--------------+--------------+------------- - * | | | SVCall - * | SVCall | SVCall | HIGH - * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL - * | | MAXNORMAL | - * ----------------------------+--------------+--------------+------------- - */ - -#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#else -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#endif - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/include/nrf52/chip.h b/arch/arm/include/nrf52/chip.h index 9007d9557d3..43a2e8a4c9e 100644 --- a/arch/arm/include/nrf52/chip.h +++ b/arch/arm/include/nrf52/chip.h @@ -58,55 +58,6 @@ #define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ #define NVIC_SYSH_PRIORITY_STEP 0x20 /* Steps between priorities */ -/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled - * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most - * interrupts will not have execution priority. SVCall must have execution - * priority in all cases. - * - * In the normal cases, interrupts are not nest-able and all interrupts run - * at an execution priority between NVIC_SYSH_PRIORITY_MIN and - * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). - * - * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special - * high priority interrupts are supported. These are not "nested" in the - * normal sense of the word. These high priority interrupts can interrupt - * normal processing but execute outside of OS (although they can "get back - * into the game" via a PendSV interrupt). - * - * In the normal course of things, interrupts must occasionally be disabled - * using the up_irq_save() inline function to prevent contention in use of - * resources that may be shared between interrupt level and non-interrupt - * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, - * do we disable all interrupts (except SVCall), or do we only disable the - * "normal" interrupts. Since the high priority interrupts cannot interact - * with the OS, you may want to permit the high priority interrupts even if - * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be - * used to select either behavior: - * - * ----------------------------+--------------+---------------------------- - * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES - * ----------------------------+--------------+--------------+------------- - * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO - * ----------------------------+--------------+--------------+------------- - * | | | SVCall - * | SVCall | SVCall | HIGH - * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL - * | | MAXNORMAL | - * ----------------------------+--------------+--------------+------------- - */ - -#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#else -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#endif - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/include/sam34/chip.h b/arch/arm/include/sam34/chip.h index fc67f3b5fd4..fbfda2dccc7 100644 --- a/arch/arm/include/sam34/chip.h +++ b/arch/arm/include/sam34/chip.h @@ -905,55 +905,6 @@ #define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ #define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ -/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled - * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most - * interrupts will not have execution priority. SVCall must have execution - * priority in all cases. - * - * In the normal cases, interrupts are not nest-able and all interrupts run - * at an execution priority between NVIC_SYSH_PRIORITY_MIN and - * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). - * - * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special - * high priority interrupts are supported. These are not "nested" in the - * normal sense of the word. These high priority interrupts can interrupt - * normal processing but execute outside of OS (although they can "get back - * into the game" via a PendSV interrupt). - * - * In the normal course of things, interrupts must occasionally be disabled - * using the up_irq_save() inline function to prevent contention in use of - * resources that may be shared between interrupt level and non-interrupt - * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, - * do we disable all interrupts (except SVCall), or do we only disable the - * "normal" interrupts. Since the high priority interrupts cannot interact - * with the OS, you may want to permit the high priority interrupts even if - * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be - * used to select either behavior: - * - * ----------------------------+--------------+---------------------------- - * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES - * ----------------------------+--------------+--------------+------------- - * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO - * ----------------------------+--------------+--------------+------------- - * | | | SVCall - * | SVCall | SVCall | HIGH - * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL - * | | MAXNORMAL | - * ----------------------------+--------------+--------------+------------- - */ - -#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#else -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#endif - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/include/samv7/chip.h b/arch/arm/include/samv7/chip.h index 2d52b3de8a6..6def881b8aa 100644 --- a/arch/arm/include/samv7/chip.h +++ b/arch/arm/include/samv7/chip.h @@ -397,55 +397,6 @@ #define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ #define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ -/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled - * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most - * interrupts will not have execution priority. SVCall must have execution - * priority in all cases. - * - * In the normal cases, interrupts are not nest-able and all interrupts run - * at an execution priority between NVIC_SYSH_PRIORITY_MIN and - * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). - * - * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special - * high priority interrupts are supported. These are not "nested" in the - * normal sense of the word. These high priority interrupts can interrupt - * normal processing but execute outside of OS (although they can "get back - * into the game" via a PendSV interrupt). - * - * In the normal course of things, interrupts must occasionally be disabled - * using the up_irq_save() inline function to prevent contention in use of - * resources that may be shared between interrupt level and non-interrupt - * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, - * do we disable all interrupts (except SVCall), or do we only disable the - * "normal" interrupts. Since the high priority interrupts cannot interact - * with the OS, you may want to permit the high priority interrupts even if - * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be - * used to select either behavior: - * - * ----------------------------+--------------+---------------------------- - * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES - * ----------------------------+--------------+--------------+------------- - * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO - * ----------------------------+--------------+--------------+------------- - * | | | SVCall - * | SVCall | SVCall | HIGH - * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL - * | | MAXNORMAL | - * ----------------------------+--------------+--------------+------------- - */ - -#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#else -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#endif - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/include/stm32/chip.h b/arch/arm/include/stm32/chip.h index 1746b9e32dd..d6bc5eaeedc 100644 --- a/arch/arm/include/stm32/chip.h +++ b/arch/arm/include/stm32/chip.h @@ -3308,53 +3308,4 @@ #define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ #define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ -/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled - * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most - * interrupts will not have execution priority. SVCall must have execution - * priority in all cases. - * - * In the normal cases, interrupts are not nest-able and all interrupts run - * at an execution priority between NVIC_SYSH_PRIORITY_MIN and - * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). - * - * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special - * high priority interrupts are supported. These are not "nested" in the - * normal sense of the word. These high priority interrupts can interrupt - * normal processing but execute outside of OS (although they can "get back - * into the game" via a PendSV interrupt). - * - * In the normal course of things, interrupts must occasionally be disabled - * using the up_irq_save() inline function to prevent contention in use of - * resources that may be shared between interrupt level and non-interrupt - * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, - * do we disable all interrupts (except SVCall), or do we only disable the - * "normal" interrupts. Since the high priority interrupts cannot interact - * with the OS, you may want to permit the high priority interrupts even if - * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be - * used to select either behavior: - * - * ----------------------------+--------------+---------------------------- - * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES - * ----------------------------+--------------+--------------+------------- - * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO - * ----------------------------+--------------+--------------+------------- - * | | | SVCall - * | SVCall | SVCall | HIGH - * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL - * | | MAXNORMAL | - * ----------------------------+--------------+--------------+------------- - */ - -#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#else -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#endif - #endif /* __ARCH_ARM_INCLUDE_STM32_CHIP_H */ diff --git a/arch/arm/include/stm32f0/chip.h b/arch/arm/include/stm32f0/chip.h index 196a15e2211..892755e4716 100644 --- a/arch/arm/include/stm32f0/chip.h +++ b/arch/arm/include/stm32f0/chip.h @@ -249,55 +249,6 @@ #define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ #define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ -/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled - * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most - * interrupts will not have execution priority. SVCall must have execution - * priority in all cases. - * - * In the normal cases, interrupts are not nest-able and all interrupts run - * at an execution priority between NVIC_SYSH_PRIORITY_MIN and - * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). - * - * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special - * high priority interrupts are supported. These are not "nested" in the - * normal sense of the word. These high priority interrupts can interrupt - * normal processing but execute outside of OS (although they can "get back - * into the game" via a PendSV interrupt). - * - * In the normal course of things, interrupts must occasionally be disabled - * using the up_irq_save() inline function to prevent contention in use of - * resources that may be shared between interrupt level and non-interrupt - * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, - * do we disable all interrupts (except SVCall), or do we only disable the - * "normal" interrupts. Since the high priority interrupts cannot interact - * with the OS, you may want to permit the high priority interrupts even if - * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be - * used to select either behavior: - * - * ----------------------------+--------------+---------------------------- - * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES - * ----------------------------+--------------+--------------+------------- - * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO - * ----------------------------+--------------+--------------+------------- - * | | | SVCall - * | SVCall | SVCall | HIGH - * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL - * | | MAXNORMAL | - * ----------------------------+--------------+--------------+------------- - */ - -#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#else -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#endif - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/include/stm32f7/chip.h b/arch/arm/include/stm32f7/chip.h index 4ce6e2ef5be..1a31384da19 100644 --- a/arch/arm/include/stm32f7/chip.h +++ b/arch/arm/include/stm32f7/chip.h @@ -381,53 +381,4 @@ #define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ #define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ -/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled - * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most - * interrupts will not have execution priority. SVCall must have execution - * priority in all cases. - * - * In the normal cases, interrupts are not nest-able and all interrupts run - * at an execution priority between NVIC_SYSH_PRIORITY_MIN and - * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). - * - * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special - * high priority interrupts are supported. These are not "nested" in the - * normal sense of the word. These high priority interrupts can interrupt - * normal processing but execute outside of OS (although they can "get back - * into the game" via a PendSV interrupt). - * - * In the normal course of things, interrupts must occasionally be disabled - * using the up_irq_save() inline function to prevent contention in use of - * resources that may be shared between interrupt level and non-interrupt - * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, - * do we disable all interrupts (except SVCall), or do we only disable the - * "normal" interrupts. Since the high priority interrupts cannot interact - * with the OS, you may want to permit the high priority interrupts even if - * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be - * used to select either behavior: - * - * ----------------------------+--------------+---------------------------- - * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES - * ----------------------------+--------------+--------------+------------- - * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO - * ----------------------------+--------------+--------------+------------- - * | | | SVCall - * | SVCall | SVCall | HIGH - * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL - * | | MAXNORMAL | - * ----------------------------+--------------+--------------+------------- - */ - -#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#else -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#endif - #endif /* __ARCH_ARM_INCLUDE_STM32F7_CHIP_H */ diff --git a/arch/arm/include/stm32h7/chip.h b/arch/arm/include/stm32h7/chip.h index 53b0a3252ce..63cfaf54e88 100644 --- a/arch/arm/include/stm32h7/chip.h +++ b/arch/arm/include/stm32h7/chip.h @@ -137,54 +137,4 @@ #define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ #define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ -/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled - * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most - * interrupts will not have execution priority. SVCall must have execution - * priority in all cases. - * - * In the normal cases, interrupts are not nest-able and all interrupts run - * at an execution priority between NVIC_SYSH_PRIORITY_MIN and - * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). - * - * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special - * high priority interrupts are supported. These are not "nested" in the - * normal sense of the word. These high priority interrupts can interrupt - * normal processing but execute outside of OS (although they can "get back - * into the game" via a PendSV interrupt). - * - * In the normal course of things, interrupts must occasionally be disabled - * using the up_irq_save() inline function to prevent contention in use of - * resources that may be shared between interrupt level and non-interrupt - * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, - * do we disable all interrupts (except SVCall), or do we only disable the - * "normal" interrupts. Since the high priority interrupts cannot interact - * with the OS, you may want to permit the high priority interrupts even if - * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be - * used to select either behavior: - * - * ----------------------------+--------------+---------------------------- - * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES - * ----------------------------+--------------+--------------+------------- - * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO - * ----------------------------+--------------+--------------+------------- - * | | | SVCall - * | SVCall | SVCall | HIGH - * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL - * | | MAXNORMAL | - * ----------------------------+--------------+--------------+------------- - */ - -// TODO: check this -#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#else -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#endif - #endif /* __ARCH_ARM_INCLUDE_STM32H7_CHIP_H */ diff --git a/arch/arm/include/stm32l4/chip.h b/arch/arm/include/stm32l4/chip.h index 0c814725a5f..d9311b0909a 100644 --- a/arch/arm/include/stm32l4/chip.h +++ b/arch/arm/include/stm32l4/chip.h @@ -343,53 +343,4 @@ #define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ #define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ -/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled - * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most - * interrupts will not have execution priority. SVCall must have execution - * priority in all cases. - * - * In the normal cases, interrupts are not nest-able and all interrupts run - * at an execution priority between NVIC_SYSH_PRIORITY_MIN and - * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). - * - * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special - * high priority interrupts are supported. These are not "nested" in the - * normal sense of the word. These high priority interrupts can interrupt - * normal processing but execute outside of OS (although they can "get back - * into the game" via a PendSV interrupt). - * - * In the normal course of things, interrupts must occasionally be disabled - * using the irqsave() inline function to prevent contention in use of - * resources that may be shared between interrupt level and non-interrupt - * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, - * do we disable all interrupts (except SVCall), or do we only disable the - * "normal" interrupts. Since the high priority interrupts cannot interact - * with the OS, you may want to permit the high priority interrupts even if - * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be - * used to select either behavior: - * - * ----------------------------+--------------+---------------------------- - * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES - * ----------------------------+--------------+--------------+------------- - * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO - * ----------------------------+--------------+--------------+------------- - * | | | SVCall - * | SVCall | SVCall | HIGH - * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL - * | | MAXNORMAL | - * ----------------------------+--------------+--------------+------------- - */ - -#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#else -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#endif - #endif /* __ARCH_ARM_INCLUDE_STM32L4_CHIP_H */ diff --git a/arch/arm/include/tiva/chip.h b/arch/arm/include/tiva/chip.h index 053ba098d39..e378312e561 100644 --- a/arch/arm/include/tiva/chip.h +++ b/arch/arm/include/tiva/chip.h @@ -375,55 +375,6 @@ #define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ #define NVIC_SYSH_PRIORITY_STEP 0x20 /* Three bits of interrupt priority used */ -/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled - * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most - * interrupts will not have execution priority. SVCall must have execution - * priority in all cases. - * - * In the normal cases, interrupts are not nest-able and all interrupts run - * at an execution priority between NVIC_SYSH_PRIORITY_MIN and - * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). - * - * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special - * high priority interrupts are supported. These are not "nested" in the - * normal sense of the word. These high priority interrupts can interrupt - * normal processing but execute outside of OS (although they can "get back - * into the game" via a PendSV interrupt). - * - * In the normal course of things, interrupts must occasionally be disabled - * using the up_irq_save() inline function to prevent contention in use of - * resources that may be shared between interrupt level and non-interrupt - * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, - * do we disable all interrupts (except SVCall), or do we only disable the - * "normal" interrupts. Since the high priority interrupts cannot interact - * with the OS, you may want to permit the high priority interrupts even if - * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be - * used to select either behavior: - * - * ----------------------------+--------------+---------------------------- - * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES - * ----------------------------+--------------+--------------+------------- - * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO - * ----------------------------+--------------+--------------+------------- - * | | | SVCall - * | SVCall | SVCall | HIGH - * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL - * | | MAXNORMAL | - * ----------------------------+--------------+--------------+------------- - */ - -#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#else -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#endif - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/include/xmc4/chip.h b/arch/arm/include/xmc4/chip.h index 8ee065ffc36..d0ffae2ffb1 100644 --- a/arch/arm/include/xmc4/chip.h +++ b/arch/arm/include/xmc4/chip.h @@ -75,55 +75,6 @@ #define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ #define NVIC_SYSH_PRIORITY_STEP 0x04 /* Steps between supported priority values */ -/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled - * by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most - * interrupts will not have execution priority. SVCall must have execution - * priority in all cases. - * - * In the normal cases, interrupts are not nest-able and all interrupts run - * at an execution priority between NVIC_SYSH_PRIORITY_MIN and - * NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall). - * - * If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special - * high priority interrupts are supported. These are not "nested" in the - * normal sense of the word. These high priority interrupts can interrupt - * normal processing but execute outside of OS (although they can "get back - * into the game" via a PendSV interrupt). - * - * In the normal course of things, interrupts must occasionally be disabled - * using the up_irq_save() inline function to prevent contention in use of - * resources that may be shared between interrupt level and non-interrupt - * level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT, - * do we disable all interrupts (except SVCall), or do we only disable the - * "normal" interrupts. Since the high priority interrupts cannot interact - * with the OS, you may want to permit the high priority interrupts even if - * interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be - * used to select either behavior: - * - * ----------------------------+--------------+---------------------------- - * CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES - * ----------------------------+--------------+--------------+------------- - * CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO - * ----------------------------+--------------+--------------+------------- - * | | | SVCall - * | SVCall | SVCall | HIGH - * Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL - * | | MAXNORMAL | - * ----------------------------+--------------+--------------+------------- - */ - -#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL) -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#else -# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP) -# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX -# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY -# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX -#endif - /************************************************************************************ * Public Types ************************************************************************************/ diff --git a/arch/arm/src/armv7-m/gnu/up_exception.S b/arch/arm/src/armv7-m/gnu/up_exception.S index ddf04afc7cf..0eddc05449f 100644 --- a/arch/arm/src/armv7-m/gnu/up_exception.S +++ b/arch/arm/src/armv7-m/gnu/up_exception.S @@ -41,9 +41,10 @@ #include #include -#include "exc_return.h" +#include #include "chip.h" +#include "exc_return.h" /************************************************************************************ * Pre-processor Definitions diff --git a/arch/arm/src/armv7-m/gnu/up_lazyexception.S b/arch/arm/src/armv7-m/gnu/up_lazyexception.S index a47a0137e63..a8334ab281f 100644 --- a/arch/arm/src/armv7-m/gnu/up_lazyexception.S +++ b/arch/arm/src/armv7-m/gnu/up_lazyexception.S @@ -40,9 +40,10 @@ #include #include -#include "exc_return.h" +#include #include "chip.h" +#include "exc_return.h" /************************************************************************************************ * Pre-processor Definitions diff --git a/arch/arm/src/armv7-m/up_initialstate.c b/arch/arm/src/armv7-m/up_initialstate.c index 498464761d1..a6ac40b8eec 100644 --- a/arch/arm/src/armv7-m/up_initialstate.c +++ b/arch/arm/src/armv7-m/up_initialstate.c @@ -44,6 +44,7 @@ #include #include +#include #include "up_internal.h" #include "up_arch.h" diff --git a/arch/arm/src/armv7-m/up_schedulesigaction.c b/arch/arm/src/armv7-m/up_schedulesigaction.c index fd682294ba1..df994c41fad 100644 --- a/arch/arm/src/armv7-m/up_schedulesigaction.c +++ b/arch/arm/src/armv7-m/up_schedulesigaction.c @@ -45,6 +45,7 @@ #include #include +#include #include "psr.h" #include "exc_return.h" diff --git a/arch/arm/src/efm32/efm32_irq.c b/arch/arm/src/efm32/efm32_irq.c index 8d1e6cce834..a2b25d800d5 100644 --- a/arch/arm/src/efm32/efm32_irq.c +++ b/arch/arm/src/efm32/efm32_irq.c @@ -46,6 +46,7 @@ #include #include #include +#include #include "nvic.h" #include "ram_vectors.h" diff --git a/arch/arm/src/imxrt/imxrt_irq.c b/arch/arm/src/imxrt/imxrt_irq.c index 0b50e806629..60475b3e967 100644 --- a/arch/arm/src/imxrt/imxrt_irq.c +++ b/arch/arm/src/imxrt/imxrt_irq.c @@ -44,7 +44,9 @@ #include #include + #include +#include #include "nvic.h" #include "ram_vectors.h" diff --git a/arch/arm/src/kinetis/kinetis_irq.c b/arch/arm/src/kinetis/kinetis_irq.c index c5ed3755086..bf938390c51 100644 --- a/arch/arm/src/kinetis/kinetis_irq.c +++ b/arch/arm/src/kinetis/kinetis_irq.c @@ -45,6 +45,7 @@ #include #include #include +#include #include "nvic.h" #include "ram_vectors.h" diff --git a/arch/arm/src/lc823450/lc823450_irq.c b/arch/arm/src/lc823450/lc823450_irq.c index a2982c65498..33438d8f3b3 100644 --- a/arch/arm/src/lc823450/lc823450_irq.c +++ b/arch/arm/src/lc823450/lc823450_irq.c @@ -48,7 +48,8 @@ #include #include #include -#include + +#include #include "nvic.h" #include "ram_vectors.h" @@ -61,6 +62,8 @@ # include "lc823450_dvfs2.h" #endif +#include + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/arch/arm/src/lpc17xx/lpc17_irq.c b/arch/arm/src/lpc17xx/lpc17_irq.c index ba94de43770..c15d33baf9b 100644 --- a/arch/arm/src/lpc17xx/lpc17_irq.c +++ b/arch/arm/src/lpc17xx/lpc17_irq.c @@ -45,6 +45,7 @@ #include #include #include +#include #include "nvic.h" #include "ram_vectors.h" diff --git a/arch/arm/src/lpc43xx/lpc43_irq.c b/arch/arm/src/lpc43xx/lpc43_irq.c index f64f10a74a1..de71352bfb9 100644 --- a/arch/arm/src/lpc43xx/lpc43_irq.c +++ b/arch/arm/src/lpc43xx/lpc43_irq.c @@ -45,6 +45,7 @@ #include #include #include +#include #include "chip.h" #include "nvic.h" diff --git a/arch/arm/src/lpc54xx/lpc54_irq.c b/arch/arm/src/lpc54xx/lpc54_irq.c index 004ab779757..e71afbbd3ee 100644 --- a/arch/arm/src/lpc54xx/lpc54_irq.c +++ b/arch/arm/src/lpc54xx/lpc54_irq.c @@ -45,6 +45,7 @@ #include #include #include +#include #include "chip.h" #include "nvic.h" diff --git a/arch/arm/src/max326xx/common/max326_irq.c b/arch/arm/src/max326xx/common/max326_irq.c index fb2c9153b64..ed1fb0a6b05 100644 --- a/arch/arm/src/max326xx/common/max326_irq.c +++ b/arch/arm/src/max326xx/common/max326_irq.c @@ -45,6 +45,7 @@ #include #include #include +#include #include "chip.h" #include "nvic.h" diff --git a/arch/arm/src/nrf52/nrf52_irq.c b/arch/arm/src/nrf52/nrf52_irq.c index 7452d689078..3f44bc9cb41 100644 --- a/arch/arm/src/nrf52/nrf52_irq.c +++ b/arch/arm/src/nrf52/nrf52_irq.c @@ -45,6 +45,7 @@ #include #include #include +#include #include "chip.h" #include "nvic.h" diff --git a/arch/arm/src/sam34/sam_irq.c b/arch/arm/src/sam34/sam_irq.c index 7200d028f76..8e1a998b4f3 100644 --- a/arch/arm/src/sam34/sam_irq.c +++ b/arch/arm/src/sam34/sam_irq.c @@ -45,6 +45,7 @@ #include #include #include +#include #include "nvic.h" #include "ram_vectors.h" diff --git a/arch/arm/src/samd5e5/sam_irq.c b/arch/arm/src/samd5e5/sam_irq.c index 0d40eccd282..6f09ec06844 100644 --- a/arch/arm/src/samd5e5/sam_irq.c +++ b/arch/arm/src/samd5e5/sam_irq.c @@ -45,6 +45,7 @@ #include #include #include +#include #include "nvic.h" #include "ram_vectors.h" diff --git a/arch/arm/src/samv7/sam_irq.c b/arch/arm/src/samv7/sam_irq.c index 99bdd54fd5c..191256d5b9f 100644 --- a/arch/arm/src/samv7/sam_irq.c +++ b/arch/arm/src/samv7/sam_irq.c @@ -45,6 +45,7 @@ #include #include #include +#include #include "nvic.h" #include "ram_vectors.h" diff --git a/arch/arm/src/stm32/stm32_irq.c b/arch/arm/src/stm32/stm32_irq.c index 402351aafa2..dfd1969e9a3 100644 --- a/arch/arm/src/stm32/stm32_irq.c +++ b/arch/arm/src/stm32/stm32_irq.c @@ -45,6 +45,7 @@ #include #include #include +#include #include "nvic.h" #include "ram_vectors.h" diff --git a/arch/arm/src/stm32f7/stm32_irq.c b/arch/arm/src/stm32f7/stm32_irq.c index 19267740067..a0836e7a325 100644 --- a/arch/arm/src/stm32f7/stm32_irq.c +++ b/arch/arm/src/stm32f7/stm32_irq.c @@ -46,7 +46,7 @@ #include #include -#include +#include #include "nvic.h" #include "ram_vectors.h" diff --git a/arch/arm/src/stm32h7/stm32_irq.c b/arch/arm/src/stm32h7/stm32_irq.c index d008e778fdd..408c530819a 100644 --- a/arch/arm/src/stm32h7/stm32_irq.c +++ b/arch/arm/src/stm32h7/stm32_irq.c @@ -46,7 +46,7 @@ #include #include -#include +#include #include "nvic.h" #include "ram_vectors.h" diff --git a/arch/arm/src/stm32l4/stm32l4_irq.c b/arch/arm/src/stm32l4/stm32l4_irq.c index 4b401d88301..7e60dcf37f7 100644 --- a/arch/arm/src/stm32l4/stm32l4_irq.c +++ b/arch/arm/src/stm32l4/stm32l4_irq.c @@ -45,6 +45,7 @@ #include #include #include +#include #include "nvic.h" #include "ram_vectors.h" diff --git a/arch/arm/src/tiva/common/tiva_irq.c b/arch/arm/src/tiva/common/tiva_irq.c index aca7352f4cf..280f90ac68f 100644 --- a/arch/arm/src/tiva/common/tiva_irq.c +++ b/arch/arm/src/tiva/common/tiva_irq.c @@ -46,6 +46,7 @@ #include #include #include +#include #include "nvic.h" #include "ram_vectors.h" diff --git a/arch/arm/src/xmc4/xmc4_irq.c b/arch/arm/src/xmc4/xmc4_irq.c index b701f64f185..73637fdbf2f 100644 --- a/arch/arm/src/xmc4/xmc4_irq.c +++ b/arch/arm/src/xmc4/xmc4_irq.c @@ -45,7 +45,7 @@ #include #include #include -#include +#include #include "nvic.h" #include "ram_vectors.h" diff --git a/configs/nucleo-f302r8/src/stm32_highpri.c b/configs/nucleo-f302r8/src/stm32_highpri.c index bcfe1ccc248..c42175ce6f5 100644 --- a/configs/nucleo-f302r8/src/stm32_highpri.c +++ b/configs/nucleo-f302r8/src/stm32_highpri.c @@ -48,20 +48,21 @@ #include #include -#include -#include - -#include "up_internal.h" -#include "ram_vectors.h" +#include #include #include #include +#include "up_internal.h" +#include "ram_vectors.h" + #include "stm32_pwm.h" #include "stm32_adc.h" #include "stm32_dma.h" +#include + #ifdef CONFIG_NUCLEOF302R8_HIGHPRI /**************************************************************************** diff --git a/configs/nucleo-f334r8/src/stm32_highpri.c b/configs/nucleo-f334r8/src/stm32_highpri.c index 74d64d7740f..1778291f188 100644 --- a/configs/nucleo-f334r8/src/stm32_highpri.c +++ b/configs/nucleo-f334r8/src/stm32_highpri.c @@ -48,21 +48,22 @@ #include #include -#include -#include - -#include "up_internal.h" -#include "ram_vectors.h" +#include #include #include #include +#include "up_internal.h" +#include "ram_vectors.h" + #include "stm32_hrtim.h" #include "stm32_pwm.h" #include "stm32_adc.h" #include "stm32_dma.h" +#include + #ifdef CONFIG_NUCLEOF334R8_HIGHPRI /**************************************************************************** diff --git a/configs/stm32f334-disco/src/stm32_smps.c b/configs/stm32f334-disco/src/stm32_smps.c index 89a94630382..227aacac0b6 100644 --- a/configs/stm32f334-disco/src/stm32_smps.c +++ b/configs/stm32f334-disco/src/stm32_smps.c @@ -39,6 +39,10 @@ #include +#include +#include +#include + #include #include #include @@ -49,24 +53,23 @@ #include #include -#include -#include -#include - #include #include #include - -#include "up_internal.h" -#include "ram_vectors.h" - #include #include #include +#include + +#include "up_internal.h" +#include "ram_vectors.h" + #include "stm32_hrtim.h" #include "stm32_adc.h" +#include + #if defined(CONFIG_EXAMPLES_SMPS) && defined(CONFIG_DRIVERS_SMPS) #ifndef CONFIG_LIBDSP diff --git a/configs/stm32f429i-disco/src/stm32_highpri.c b/configs/stm32f429i-disco/src/stm32_highpri.c index 13b39e4543b..5227fe74e7c 100644 --- a/configs/stm32f429i-disco/src/stm32_highpri.c +++ b/configs/stm32f429i-disco/src/stm32_highpri.c @@ -46,22 +46,21 @@ #include #include - -#include -#include -#include - -#include "up_internal.h" -#include "ram_vectors.h" - #include #include #include +#include +#include + +#include "up_internal.h" +#include "ram_vectors.h" + #include "stm32_pwm.h" #include "stm32_adc.h" #include "stm32_dma.h" +#include #ifdef CONFIG_STM32F429I_DISCO_HIGHPRI /**************************************************************************** diff --git a/configs/viewtool-stm32f107/src/stm32_highpri.c b/configs/viewtool-stm32f107/src/stm32_highpri.c index 5eea8d60ac8..19a9b4ac66a 100644 --- a/configs/viewtool-stm32f107/src/stm32_highpri.c +++ b/configs/viewtool-stm32f107/src/stm32_highpri.c @@ -47,8 +47,7 @@ #include #include -#include -#include +#include #include "up_internal.h" #include "ram_vectors.h" @@ -56,6 +55,8 @@ #include "viewtool_stm32f107.h" +#include + #ifdef CONFIG_VIEWTOOL_HIGHPRI /****************************************************************************