Mirrors_Framework/nuttx
1
0
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2026-06-01 07:45:16 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

esp32s3: add simple boot support

Browse Source 
The Simple Boot feature for Espressif chips is a method of booting
that doesn't depend on a 2nd stage bootloader. Its not the
intention to replace a 2nd stage bootloader such as MCUboot and
ESP-IDF bootloader, but to have a minimal and straight-forward way
of booting, and also simplify the building.

This commit also removes deprecated code and makes this bootloader
configuration as default for esp32s3 targets and removes the need
for running 'make bootloader' command for it.

Other related fix, but not directly to Simple Boot:
- Instrumentation is required to run from IRAM to support it during
initialization. `is_eco0` function also needs to run from IRAM.
- `rtc.data` section placement was fixed.
- Provide arch-defined interfaces for efuses, in order to decouple
board config level from arch-defined values.

Signed-off-by: Almir Okato <almir.okato@espressif.com>
This commit is contained in:
Almir Okato
2024-02-09 16:15:33 -03:00
committed by Xiang Xiao
parent 9009cd6f2d
commit d098c1dc87
49 changed files with 1211 additions and 7600 deletions
Download Patch File Download Diff File Expand all files Collapse all files
boards/xtensa/esp32s3/common/scripts/flat_memory.ld
+27 -14
View File
@@ -48,6 +48,8 @@
#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT
#define SRAM_IRAM_END 0x403ba000
#elif defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
#define SRAM_IRAM_END 0x403c0000
#else
#define SRAM_IRAM_END 0x403cc700
#endif
@@ -77,6 +79,8 @@
# define FLASH_SIZE 0x2000000
#endif
#define RESERVE_RTC_MEM 24
MEMORY
{
#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT
@@ -92,6 +96,16 @@ MEMORY
metadata (RX) : org = CONFIG_ESP32S3_APP_MCUBOOT_HEADER_SIZE, len = 0x20
ROM (RX) : org = ORIGIN(metadata) + LENGTH(metadata),
len = FLASH_SIZE - ORIGIN(ROM)
#elif defined (CONFIG_ESPRESSIF_SIMPLE_BOOT)
/* The 0x20 offset is a convenience for the app binary image generation.
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
* header. Setting this offset makes it simple to meet the flash cache MMU's
* constraint that (paddr % 64KB == vaddr % 64KB).
*/
ROM (RX) : org = 0x20,
len = FLASH_SIZE - ORIGIN(ROM)
#endif
/* Below values assume the flash cache is on, and have the blocks this
@@ -109,12 +123,7 @@ MEMORY
#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT
irom0_0_seg (RX) : org = 0x42000000, len = FLASH_SIZE
#else
/* The 0x20 offset is a convenience for the app binary image generation.
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
* header. Setting this offset makes it simple to meet the flash cache MMU's
* constraint that (paddr % 64KB == vaddr % 64KB).
*/
/* (See ROM segment above for meaning of 0x20 offset.) */
irom0_0_seg (RX) : org = 0x42000020, len = FLASH_SIZE - 0x20
#endif
@@ -144,23 +153,27 @@ MEMORY
drom0_0_seg (R) : org = 0x3c000000 + ORIGIN(ROM),
len = FLASH_SIZE - ORIGIN(ROM)
#else
/* The 0x20 offset is a convenience for the app binary image generation.
* Flash cache has 64KB pages. The .bin file which is flashed to the chip
* has a 0x18 byte file header, and each segment has a 0x08 byte segment
* header. Setting this offset makes it simple to meet the flash cache MMU's
* constraint that (paddr % 64KB == vaddr % 64KB).
*/
/* (See ROM segment above for meaning of 0x20 offset.) */
drom0_0_seg (R) : org = 0x3c000020, len = FLASH_SIZE - 0x20
#endif
/* RTC fast memory (executable). Persists over deep sleep. */
rtc_iram_seg(RWX) : org = 0x600fe000, len = 0x2000
rtc_iram_seg(RWX) : org = 0x600fe000, len = 0x2000 - RESERVE_RTC_MEM
/* RTC fast memory (same block as above), viewed from data bus */
rtc_data_seg(RW) : org = 0x600fe000, len = 0x2000
rtc_data_seg(RW) : org = 0x600fe000, len = 0x2000 - RESERVE_RTC_MEM
/* We reduced the size of rtc_iram_seg by RESERVE_RTC_MEM value.
It reserves the amount of RTC fast memory that we use for this memory segment.
This segment is intended for keeping:
- (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
- (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
The aim of this is to keep data that will not be moved around and have a fixed address.
*/
rtc_reserved_seg(RW) : org = 0x600fe000 + 0x2000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM
/* RTC slow memory (data accessible). Persists over deep sleep.
* Start of RTC slow memory is reserved for ULP co-processor code + data,
boards/xtensa/esp32s3/common/scripts/kernel-space.ld
+9
View File
@@ -118,6 +118,8 @@ SECTIONS
*libsched.a:irq_csection.*(.literal .text .literal.* .text.*)
*libsched.a:irq_dispatch.*(.literal .text .literal.* .text.*)
*libc.a:*lib_instrument.*(.text .text.* .literal .literal.*)
*(.wifirxiram .wifirxiram.*)
*(.wifi0iram .wifi0iram.*)
*(.wifiorslpiram .wifiorslpiram.*)
@@ -168,6 +170,8 @@ SECTIONS
*libsched.a:irq_csection.*(.bss .bss.* COMMON)
*libsched.a:irq_dispatch.*(.bss .bss.* COMMON)
*libc.a:*lib_instrument.*(.bss .bss.* COMMON)
. = ALIGN(8);
_ebss = ABSOLUTE(.);
} >KDRAM
@@ -214,6 +218,8 @@ SECTIONS
*libsched.a:irq_csection.*(.rodata .rodata.*)
*libsched.a:irq_dispatch.*(.rodata .rodata.*)
*libc.a:*lib_instrument.*(.rodata .rodata.*)
. = ALIGN(4);
_edata = ABSOLUTE(.);
@@ -225,6 +231,8 @@ SECTIONS
.flash.text :
{
_stext = .;
_instruction_reserved_start = ABSOLUTE(.);
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
@@ -239,6 +247,7 @@ SECTIONS
. += 16;
_instruction_reserved_end = ABSOLUTE(.);
_etext = .;
} >KIROM
boards/xtensa/esp32s3/common/scripts/legacy_sections.ld
+3
View File
@@ -237,6 +237,8 @@ SECTIONS
.flash.text :
{
_stext = .;
_instruction_reserved_start = ABSOLUTE(.);
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
@@ -251,6 +253,7 @@ SECTIONS
. += 16;
_instruction_reserved_end = ABSOLUTE(.);
_etext = .;
} >default_code_seg
boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld
+17 -6
View File
@@ -61,7 +61,7 @@ SECTIONS
_image_drom_lma = LOADADDR(.flash.rodata);
_image_drom_size = LOADADDR(.flash.rodata) + SIZEOF(.flash.rodata) - _image_drom_lma;
.flash.rodata :
.flash.rodata : ALIGN(4)
{
_rodata_reserved_start = .;
@@ -69,8 +69,6 @@ SECTIONS
*(EXCLUDE_FILE (esp32s3_start.*) .rodata)
*(EXCLUDE_FILE (esp32s3_start.*) .rodata.*)
*(.rodata)
*(.rodata.*)
#ifdef CONFIG_ESP32S3_WIRELESS
*(.rodata_wlog_verbose.*)
*(.rodata_wlog_debug.*)
@@ -128,7 +126,7 @@ SECTIONS
/* Send .iram0 code to iram */
.iram0.vectors :
.iram0.vectors : ALIGN(4)
{
_iram_start = ABSOLUTE(.);
@@ -168,7 +166,7 @@ SECTIONS
*(.init)
} >iram0_0_seg AT>ROM
.iram0.text :
.iram0.text : ALIGN(4)
{
/* Code marked as running out of IRAM */
@@ -185,6 +183,10 @@ SECTIONS
*libarch.a:xtensa_irqdispatch.*(.literal .text .literal.* .text.*)
*libarch.a:xtensa_modifyreg32.*(.literal .text .literal.* .text.*)
*libarch.a:xtensa_testset.*(.literal .text .literal.* .text.*)
*libarch.a:*cache_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*uart_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*)
*libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*)
#ifdef CONFIG_ESP32S3_BLE
*libc.a:sq_remlast.*(.literal .text .literal.* .text.*)
@@ -299,7 +301,7 @@ SECTIONS
. = ALIGN(4);
} >dram0_0_seg
.dram0.data :
.dram0.data : ALIGN(4)
{
/* .data initialized on power-up in ROMed configurations. */
@@ -320,6 +322,12 @@ SECTIONS
*libphy.a:(.rodata .rodata.*)
*libarch.a:xtensa_context.*(.rodata .rodata.*)
*libarch.a:esp32s3_spiflash.*(.rodata .rodata.*)
*libarch.a:*cache_hal.*(.rodata .rodata.*)
*libarch.a:*uart_hal.*(.rodata .rodata.*)
*libarch.a:*mpu_hal.*(.rodata .rodata.*)
*libarch.a:*mmu_hal.*(.rodata .rodata.*)
#if defined(CONFIG_STACK_CANARIES) && \
(defined(CONFIG_ESP32S3_SPIFLASH) || \
defined(CONFIG_ESP32S3_SPIRAM))
@@ -393,6 +401,8 @@ SECTIONS
.flash.text : ALIGN(0x00010000)
{
_stext = .;
_instruction_reserved_start = ABSOLUTE(.);
*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
*(.fini.literal)
@@ -407,6 +417,7 @@ SECTIONS
. += 16;
_instruction_reserved_end = ABSOLUTE(.);
_etext = .;
} >irom0_0_seg AT>ROM
boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld
+572
View File
File diff suppressed because it is too large Load Diff
boards/xtensa/esp32s3/common/src/esp32s3_lan9250.c
+3 -4
View File
@@ -35,14 +35,13 @@
#include <arch/board/board.h>
#include "xtensa.h"
#include "esp32s3_efuse.h"
#include "esp32s3_gpio.h"
#ifdef CONFIG_LAN9250_SPI
#include "esp32s3_spi.h"
#else
#include "esp32s3_qspi.h"
#endif
#include "hardware/esp32s3_efuse.h"
#include "hardware/esp32s3_gpio_sigmap.h"
/****************************************************************************
* Pre-processor Definitions
@@ -175,8 +174,8 @@ static void lan9250_getmac(const struct lan9250_lower_s *lower, uint8_t *mac)
uint32_t regval[2];
uint8_t *data = (uint8_t *)regval;
regval[0] = getreg32(EFUSE_RD_MAC_SPI_SYS_0_REG);
regval[1] = getreg32(EFUSE_RD_MAC_SPI_SYS_1_REG);
regval[0] = esp32s3_efuse_read_reg(EFUSE_BLK1, 0);
regval[1] = esp32s3_efuse_read_reg(EFUSE_BLK1, 1);
for (int i = 0; i < 6; i++)
{
boards/xtensa/esp32s3/esp32s3-box/scripts/Make.defs
+2
View File
@@ -38,6 +38,8 @@ else
ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld)
ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
endif
boards/xtensa/esp32s3/esp32s3-devkit/configs/eth_lan9250/defconfig
+1
View File
@@ -25,6 +25,7 @@ CONFIG_ARCH_XTENSA=y
CONFIG_BOARD_LOOPSPERMSEC=16717
CONFIG_BUILTIN=y
CONFIG_DEFAULT_TASK_STACKSIZE=4096
CONFIG_ESP32S3_EFUSE=y
CONFIG_ESP32S3_GPIO_IRQ=y
CONFIG_ESP32S3_SPI2=y
CONFIG_ESP32S3_SPI_SWCS=y
boards/xtensa/esp32s3/esp32s3-devkit/scripts/Make.defs
+2
View File
@@ -38,6 +38,8 @@ else
ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld)
ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
endif
boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_ledc.c
-1
View File
@@ -33,7 +33,6 @@
#include <arch/board/board.h>
#include "chip.h"
#include "esp32s3_ledc.h"
/****************************************************************************
boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_twai.c
-2
View File
@@ -30,8 +30,6 @@
#include <nuttx/can/can.h>
#include <arch/board/board.h>
#include "chip.h"
#include "esp32s3_twai.h"
#include "esp32s3-devkit.h"
boards/xtensa/esp32s3/esp32s3-eye/scripts/Make.defs
+7 -1
View File
@@ -36,7 +36,13 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
ARCHSCRIPT += $(call FINDSCRIPT,kernel-space.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld)
ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
endif
endif
ifneq ($(CONFIG_DEBUG_NOOPT),y)
boards/xtensa/esp32s3/esp32s3-lcd-ev/scripts/Make.defs
+2
View File
@@ -38,6 +38,8 @@ else
ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld)
ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
endif
boards/xtensa/esp32s3/esp32s3-meadow/scripts/Make.defs
+7 -1
View File
@@ -36,7 +36,13 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
ARCHSCRIPT += $(call FINDSCRIPT,kernel-space.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld)
ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld)
else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld)
else
ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld)
endif
endif
ifneq ($(CONFIG_DEBUG_NOOPT),y)