From ceaafc20191f9158fe34c85f29f496922a9c5911 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 28 Jun 2018 15:58:08 -0600 Subject: [PATCH] arch/arm/src/stm32: Fix scope of naming. CONFIG_RTC_LSECLOCK->CONFIG_STM32_RTC_LSECLOCK, for example. Fix some usage. Although CONFIG_STM32L4_RTC_xxxCLOCK was defined in the Kconfig, CONFIG_RTX_xxxCLOCK was used in numerous places in the code --- arch/arm/src/stm32/Kconfig | 8 +++---- arch/arm/src/stm32/stm32_rtcc.c | 24 +++++++++---------- arch/arm/src/stm32/stm32_rtcounter.c | 4 ++-- arch/arm/src/stm32/stm32f10xxx_rcc.c | 4 ++-- arch/arm/src/stm32/stm32f20xxx_rcc.c | 6 ++--- arch/arm/src/stm32/stm32f30xxx_rcc.c | 4 ++-- arch/arm/src/stm32/stm32f33xxx_rcc.c | 4 ++-- arch/arm/src/stm32/stm32f37xxx_rcc.c | 4 ++-- arch/arm/src/stm32/stm32f40xxx_rcc.c | 6 ++--- arch/arm/src/stm32/stm32f40xxx_rtcc.c | 24 +++++++++---------- arch/arm/src/stm32/stm32l15xxx_rcc.c | 8 +++---- arch/arm/src/stm32/stm32l15xxx_rtcc.c | 22 ++++++++--------- arch/arm/src/stm32l4/stm32l4x3xx_rcc.c | 4 ++-- arch/arm/src/stm32l4/stm32l4x5xx_rcc.c | 4 ++-- arch/arm/src/stm32l4/stm32l4x6xx_rcc.c | 4 ++-- configs/stm32l476-mdk/src/stm32_clockconfig.c | 2 +- .../stm32l476vg-disco/src/stm32_clockconfig.c | 2 +- 17 files changed, 67 insertions(+), 67 deletions(-) diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index e846af9a062..882867707c3 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -7706,19 +7706,19 @@ config STM32_RTC_MAGIC_TIME_SET choice prompt "RTC clock source" - default RTC_LSECLOCK + default STM32_RTC_LSECLOCK -config RTC_LSECLOCK +config STM32_RTC_LSECLOCK bool "LSE clock" ---help--- Drive the RTC with the LSE clock -config RTC_LSICLOCK +config STM32_RTC_LSICLOCK bool "LSI clock" ---help--- Drive the RTC with the LSI clock -config RTC_HSECLOCK +config STM32_RTC_HSECLOCK bool "HSE clock" ---help--- Drive the RTC with the HSE clock, divided down to 1MHz. diff --git a/arch/arm/src/stm32/stm32_rtcc.c b/arch/arm/src/stm32/stm32_rtcc.c index 08d09e2dfec..11b7f62b5aa 100644 --- a/arch/arm/src/stm32/stm32_rtcc.c +++ b/arch/arm/src/stm32/stm32_rtcc.c @@ -446,7 +446,7 @@ static int rtc_setup(void) /* Configure RTC pre-scaler with the required values */ -#ifdef CONFIG_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* For a 1 MHz clock this yields 0.9999360041 Hz on the second * timer - which is pretty close. */ @@ -556,17 +556,17 @@ int up_rtc_initialize(void) * rate clock */ -#ifdef CONFIG_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Use the HSE clock as the input to the RTC block */ modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_HSE); -#elif defined(CONFIG_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) /* Use the LSI clock as the input to the RTC block */ modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSI); -#elif defined(CONFIG_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) /* Use the LSE clock as the input to the RTC block */ modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); @@ -578,16 +578,16 @@ int up_rtc_initialize(void) } else /* The RTC is already in use: check if the clock source is changed */ { -#if defined(CONFIG_RTC_HSECLOCK) || defined(CONFIG_RTC_LSICLOCK) || \ - defined(CONFIG_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_STM32_RTC_LSICLOCK) || \ + defined(CONFIG_STM32_RTC_LSECLOCK) uint32_t clksrc = getreg32(STM32_RCC_BDCR); -#if defined(CONFIG_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) if ((clksrc & RCC_BDCR_RTCSEL_MASK) != RCC_BDCR_RTCSEL_HSE) -#elif defined(CONFIG_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) if ((clksrc & RCC_BDCR_RTCSEL_MASK) != RCC_BDCR_RTCSEL_LSI) -#elif defined(CONFIG_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) if ((clksrc & RCC_BDCR_RTCSEL_MASK) != RCC_BDCR_RTCSEL_LSE) #endif #endif @@ -597,15 +597,15 @@ int up_rtc_initialize(void) modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); -#if defined(CONFIG_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) /* Change to the new clock as the input to the RTC block */ modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_HSE); -#elif defined(CONFIG_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSI); -#elif defined(CONFIG_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); #endif diff --git a/arch/arm/src/stm32/stm32_rtcounter.c b/arch/arm/src/stm32/stm32_rtcounter.c index c01f21d58bd..284d75c03d1 100644 --- a/arch/arm/src/stm32/stm32_rtcounter.c +++ b/arch/arm/src/stm32/stm32_rtcounter.c @@ -118,9 +118,9 @@ #endif #ifdef CONFIG_STM32_STM32F10XX -# if defined(CONFIG_RTC_HSECLOCK) +# if defined(CONFIG_STM32_RTC_HSECLOCK) # error "RTC with HSE clock not yet implemented for STM32F10XXX" -# elif defined(CONFIG_RTC_LSICLOCK) +# elif defined(CONFIG_STM32_RTC_LSICLOCK) # error "RTC with LSI clock not yet implemented for STM32F10XXX" # endif #endif diff --git a/arch/arm/src/stm32/stm32f10xxx_rcc.c b/arch/arm/src/stm32/stm32f10xxx_rcc.c index 218e534e222..b8b9bafc61f 100644 --- a/arch/arm/src/stm32/stm32f10xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f10xxx_rcc.c @@ -751,7 +751,7 @@ static void stm32_stdclockconfig(void) while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); -#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); @@ -769,7 +769,7 @@ static inline void rcc_enableperipherals(void) rcc_enableapb2(); rcc_enableapb1(); -#if defined(CONFIG_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * For F1 it requires PWR and BKP from APB1 */ diff --git a/arch/arm/src/stm32/stm32f20xxx_rcc.c b/arch/arm/src/stm32/stm32f20xxx_rcc.c index fac0dc911d0..92bdf21f6b7 100644 --- a/arch/arm/src/stm32/stm32f20xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f20xxx_rcc.c @@ -619,7 +619,7 @@ static void stm32_stdclockconfig(void) regval |= STM32_RCC_CFGR_PPRE1; putreg32(regval, STM32_RCC_CFGR); -#ifdef CONFIG_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -664,13 +664,13 @@ static void stm32_stdclockconfig(void) while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL); -#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32/stm32f30xxx_rcc.c b/arch/arm/src/stm32/stm32f30xxx_rcc.c index a62d6d5bd14..129e4bff61d 100644 --- a/arch/arm/src/stm32/stm32f30xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f30xxx_rcc.c @@ -649,7 +649,7 @@ static void stm32_stdclockconfig(void) while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); -#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI * * TODO: There is another case where the LSI needs to @@ -659,7 +659,7 @@ static void stm32_stdclockconfig(void) stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Normally peripheral clocks are enabled later in bootup, but we need * clock on PWR *now* as without this setting registers that enable LSE * won't work. diff --git a/arch/arm/src/stm32/stm32f33xxx_rcc.c b/arch/arm/src/stm32/stm32f33xxx_rcc.c index 093134627d0..d3fb82b0fa9 100644 --- a/arch/arm/src/stm32/stm32f33xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f33xxx_rcc.c @@ -467,7 +467,7 @@ static void stm32_stdclockconfig(void) while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); -#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI * * TODO: There is another case where the LSI needs to @@ -477,7 +477,7 @@ static void stm32_stdclockconfig(void) stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32/stm32f37xxx_rcc.c b/arch/arm/src/stm32/stm32f37xxx_rcc.c index 7cb9300e0f6..5c1d026f119 100644 --- a/arch/arm/src/stm32/stm32f37xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f37xxx_rcc.c @@ -587,7 +587,7 @@ static void stm32_stdclockconfig(void) while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); -#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI * * TODO: There is another case where the LSI needs to @@ -597,7 +597,7 @@ static void stm32_stdclockconfig(void) stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32/stm32f40xxx_rcc.c b/arch/arm/src/stm32/stm32f40xxx_rcc.c index 20e748686e6..e3d67f28ab0 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f40xxx_rcc.c @@ -717,7 +717,7 @@ static void stm32_stdclockconfig(void) regval |= STM32_RCC_CFGR_PPRE1; putreg32(regval, STM32_RCC_CFGR); -#ifdef CONFIG_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -944,13 +944,13 @@ static void stm32_stdclockconfig(void) } #endif -#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c index 625ca8b0d4d..d508a8ae32f 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c +++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c @@ -515,7 +515,7 @@ static int rtc_setup(void) /* Configure RTC pre-scaler with the required values */ -#ifdef CONFIG_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* For a 1 MHz clock this yields 0.9999360041 Hz on the second * timer - which is pretty close. */ @@ -952,19 +952,19 @@ int up_rtc_initialize(void) * or the external high rate clock */ -#ifdef CONFIG_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Use the HSE clock as the input to the RTC block */ rtc_dumpregs("On reset HSE"); modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_HSE); -#elif defined(CONFIG_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) /* Use the LSI clock as the input to the RTC block */ rtc_dumpregs("On reset LSI"); modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSI); -#elif defined(CONFIG_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) /* Use the LSE clock as the input to the RTC block */ rtc_dumpregs("On reset LSE"); @@ -977,18 +977,18 @@ int up_rtc_initialize(void) } else /* The RTC is already in use: check if the clock source is changed */ { -#if defined(CONFIG_RTC_HSECLOCK) || defined(CONFIG_RTC_LSICLOCK) || \ - defined(CONFIG_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_STM32_RTC_LSICLOCK) || \ + defined(CONFIG_STM32_RTC_LSECLOCK) uint32_t clksrc = getreg32(STM32_RCC_XXX); rtc_dumpregs("On reset warm"); -#if defined(CONFIG_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) if ((clksrc & RCC_XXX_RTCSEL_MASK) != RCC_XXX_RTCSEL_HSE) -#elif defined(CONFIG_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) if ((clksrc & RCC_XXX_RTCSEL_MASK) != RCC_XXX_RTCSEL_LSI) -#elif defined(CONFIG_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) if ((clksrc & RCC_XXX_RTCSEL_MASK) != RCC_XXX_RTCSEL_LSE) #endif #endif @@ -998,15 +998,15 @@ int up_rtc_initialize(void) modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); -#if defined(CONFIG_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) /* Change to the new clock as the input to the RTC block */ modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_HSE); -#elif defined(CONFIG_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSI); -#elif defined(CONFIG_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSE); #endif diff --git a/arch/arm/src/stm32/stm32l15xxx_rcc.c b/arch/arm/src/stm32/stm32l15xxx_rcc.c index 8640934e990..1085a6ccecd 100644 --- a/arch/arm/src/stm32/stm32l15xxx_rcc.c +++ b/arch/arm/src/stm32/stm32l15xxx_rcc.c @@ -525,7 +525,7 @@ static inline bool stm32_rcc_enablehse(void) static void stm32_stdclockconfig(void) { uint32_t regval; -#if defined(CONFIG_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) uint16_t pwrcr; #endif uint32_t pwr_vos; @@ -576,7 +576,7 @@ static void stm32_stdclockconfig(void) stm32_pwr_setvos(pwr_vos); -#if defined(CONFIG_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) /* If RTC / LCD selects HSE as clock source, the RTC prescaler * needs to be set before HSEON bit is set. */ @@ -756,7 +756,7 @@ static void stm32_stdclockconfig(void) while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); #if defined(CONFIG_STM32_IWDG) || \ - defined(CONFIG_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK) + defined(CONFIG_STM32_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK) /* Low speed internal clock source LSI * * TODO: There is another case where the LSI needs to @@ -767,7 +767,7 @@ static void stm32_stdclockconfig(void) #endif -#if defined(CONFIG_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32/stm32l15xxx_rtcc.c b/arch/arm/src/stm32/stm32l15xxx_rtcc.c index ec59ebd856c..e05077fccca 100644 --- a/arch/arm/src/stm32/stm32l15xxx_rtcc.c +++ b/arch/arm/src/stm32/stm32l15xxx_rtcc.c @@ -83,9 +83,9 @@ # error "CONFIG_STM32_PWR must selected to use this driver" #endif -#if defined(CONFIG_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # warning "RTC with HSE clock not yet tested on STM32L15XXX" -#elif defined(CONFIG_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # warning "RTC with LSI clock not yet tested on STM32L15XXX" #endif @@ -918,11 +918,11 @@ int up_rtc_initialize(void) stm32_pwr_enablebkp(true); -#if defined(CONFIG_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) modifyreg32(STM32_RCC_CSR, RCC_CSR_RTCSEL_MASK, RCC_CSR_RTCSEL_HSE); -#elif defined(CONFIG_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) modifyreg32(STM32_RCC_CSR, RCC_CSR_RTCSEL_MASK, RCC_CSR_RTCSEL_LSI); -#elif defined(CONFIG_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) modifyreg32(STM32_RCC_CSR, RCC_CSR_RTCSEL_MASK, RCC_CSR_RTCSEL_LSE); #else # error "No clock for RTC!" @@ -964,7 +964,7 @@ int up_rtc_initialize(void) /* Configure RTC pre-scaler with the required values */ -#ifdef CONFIG_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* The HSE is divided by 32 prior to the prescaler we set here. * * NOTE: max HSE/32 is 4 MHz if it is to be used with RTC @@ -977,13 +977,13 @@ int up_rtc_initialize(void) putreg32(((uint32_t)7812 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), STM32_RTC_PRER); -#elif defined(CONFIG_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) /* Suitable values for 32.000 KHz LSI clock (29.5 - 34 KHz, though) */ putreg32(((uint32_t)0xf9 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), STM32_RTC_PRER); -#else /* defined(CONFIG_RTC_LSECLOCK) */ +#else /* defined(CONFIG_STM32_RTC_LSECLOCK) */ /* Correct values for 32.768 KHz LSE clock */ putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) | @@ -1734,11 +1734,11 @@ int stm32_rtc_setperiodic(FAR const struct timespec *period, wakeupcb_t callback uint32_t secs; uint32_t millisecs; -#if defined(CONFIG_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # error "Periodic wakeup not available for HSE" -#elif defined(CONFIG_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # error "Periodic wakeup not available for LSI (and it is too inaccurate!)" -#elif defined(CONFIG_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffU / STM32_LSE_FREQUENCY; #else # error "No clock for RTC!" diff --git a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c index f4f95ee4e37..076af5b1fcf 100644 --- a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c @@ -691,7 +691,7 @@ static void stm32l4_stdclockconfig(void) regval |= STM32L4_RCC_CFGR_PPRE1; putreg32(regval, STM32L4_RCC_CFGR); -#ifdef CONFIG_RTC_HSECLOCK +#ifdef CONFIG_STM32L4_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32L4_RCC_CFGR); @@ -838,7 +838,7 @@ static void stm32l4_stdclockconfig(void) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_RTC_LSICLOCK) +#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32l4_rcc_enablelsi(); diff --git a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c index 3eaa7b81946..32d39e25bc2 100644 --- a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c @@ -716,7 +716,7 @@ static void stm32l4_stdclockconfig(void) regval |= STM32L4_RCC_CFGR_PPRE1; putreg32(regval, STM32L4_RCC_CFGR); -#ifdef CONFIG_RTC_HSECLOCK +#ifdef CONFIG_STM32L4_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32L4_RCC_CFGR); @@ -863,7 +863,7 @@ static void stm32l4_stdclockconfig(void) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_RTC_LSICLOCK) +#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32l4_rcc_enablelsi(); diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c index d349255a509..eea24cbfc41 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c @@ -761,7 +761,7 @@ static void stm32l4_stdclockconfig(void) regval |= STM32L4_RCC_CFGR_PPRE1; putreg32(regval, STM32L4_RCC_CFGR); -#ifdef CONFIG_RTC_HSECLOCK +#ifdef CONFIG_STM32L4_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32L4_RCC_CFGR); @@ -908,7 +908,7 @@ static void stm32l4_stdclockconfig(void) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_RTC_LSICLOCK) +#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32l4_rcc_enablelsi(); diff --git a/configs/stm32l476-mdk/src/stm32_clockconfig.c b/configs/stm32l476-mdk/src/stm32_clockconfig.c index 134097b083f..33a8bcfad24 100644 --- a/configs/stm32l476-mdk/src/stm32_clockconfig.c +++ b/configs/stm32l476-mdk/src/stm32_clockconfig.c @@ -204,7 +204,7 @@ void stm32l4_board_clockconfig(void) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_RTC_LSICLOCK) +#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) /* Low speed internal clock source LSI */ diff --git a/configs/stm32l476vg-disco/src/stm32_clockconfig.c b/configs/stm32l476vg-disco/src/stm32_clockconfig.c index 16de23808cd..9c81603ef95 100644 --- a/configs/stm32l476vg-disco/src/stm32_clockconfig.c +++ b/configs/stm32l476vg-disco/src/stm32_clockconfig.c @@ -204,7 +204,7 @@ void stm32l4_board_clockconfig(void) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_RTC_LSICLOCK) +#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) /* Low speed internal clock source LSI */