Run codespell -w with the latest dictonary again

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>

arch/x86/include/i486/arch.h

@@ -278,7 +278,7 @@
 #define PIT_REG_COUNTER2        0x42
 #define PIT_REG_COMMAND         0x43
 
-/* PIT command bit defintions */
+/* PIT command bit definitions */
 
 #  define PIT_OCW_BINCOUNT_BCD  (1 << 0) /* vs binary */
 #  define PIT_OCW_MODE_SHIFT    (1)

arch/x86/src/i486/up_irq.c

@@ -291,7 +291,7 @@ void up_disable_irq(int irq)
 
   if (irq >= IRQ0)
     {
-      /* Map the IRQ IMR regiser to a PIC and a bit number */
+      /* Map the IRQ IMR register to a PIC and a bit number */
 
       if (irq <= IRQ7)
         {
@@ -329,7 +329,7 @@ void up_enable_irq(int irq)
 
   if (irq >= IRQ0)
     {
-      /* Map the IRQ IMR regiser to a PIC and a bit number */
+      /* Map the IRQ IMR register to a PIC and a bit number */
 
       if (irq <= IRQ7)
         {

arch/x86/src/i486/up_savestate.c

@@ -67,7 +67,7 @@
  * Description:
  *   This function saves the interrupt level context information in the
  *   TCB.  This would just be a up_copystate but we have to handle one
- *   special case.  In the case where the privilige level changes, the
+ *   special case.  In the case where the privilege level changes, the
  *   value of sp and ss will not be saved on stack by the interrupt handler.
  *   So, in that case, we will have to fudge those values here.
  *

arch/x86/src/qemu/qemu_vectors.S

@@ -239,14 +239,14 @@ irq_common:
 .Lreturn:
 	add		$4, %esp
 
-	/* EAX may possibly hold a pointer to a different regiser save area on
+	/* EAX may possibly hold a pointer to a different register save area on
 	 * return.  Are we switching to a new context?
 	 */
 
 	cmp		%eax, %esp
 	je		.Lnoswitch
 
-	/* A context swith will be performed. EAX holds the address of the new
+	/* A context switch will be performed. EAX holds the address of the new
 	 * register save structure.
 	 *
 	 * Jump to up_fullcontextrestore().  We perform a call here, but that function