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configs/nucleo-l452re: Fix TIMx clock configuration. This is cloned from 391f3715 for nucleo-l432kc. Also fixes DAC build failure.

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This commit is contained in:
Juha Niskanen
2018-08-08 06:57:22 -06:00
committed by Gregory Nutt
parent 84f8e01c17
commit cd897d71d8
2 changed files with 67 additions and 58 deletions
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configs/nucleo-l452re/include/board.h
+6
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@@ -217,6 +217,12 @@
#define ADC1_MEASURE_CHANNEL 9 #define ADC1_MEASURE_CHANNEL 9
#define GPIO_MEASURE_ADC (GPIO_ADC1_IN9) #define GPIO_MEASURE_ADC (GPIO_ADC1_IN9)
/* DAC
* Default is PA4 (same as ADC, do not use both at the same time)
*/
#define GPIO_DAC1_OUT GPIO_DAC1_OUT_1
/* Quadrature encoder /* Quadrature encoder
* Default is to use timer 5 (32-bit) and encoder on PA0/PA1 * Default is to use timer 5 (32-bit) and encoder on PA0/PA1
*/ */
configs/nucleo-l452re/include/nucleo-l452re.h
+50 -47
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@@ -273,33 +273,35 @@
#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ #define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) #define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1)
/* Timers driven from APB1 will be twice PCLK1 */ /* The timer clock frequencies are automatically defined by hardware.
/* REVISIT : this can be configured */ * If the APB prescaler equals 1, the timer clock frequencies are set to the
* same frequency as that of the APB domain. Otherwise they are set to twice.
*
* REVISIT : this can be configured
*/
#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) #define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) #define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) #define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) #define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) #define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) #define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY)
/* APB2 clock (PCLK2) is HCLK (80MHz) */ /* APB2 clock (PCLK2) is HCLK (80MHz) */
#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ #define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) #define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1)
/* Timers driven from APB2 will be twice PCLK2 */ /* The timer clock frequencies are automatically defined by hardware.
/* REVISIT : this can be configured */ * If the APB prescaler equals 1, the timer clock frequencies are set to the
* same frequency as that of the APB domain. Otherwise they are set to twice.
#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) *
#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) * REVISIT : this can be configured
#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
* otherwise frequency is 2xAPBx.
* Note: TIM1,15,16 are on APB2, others on APB1
*/ */
/* REVISIT : this can be configured */
#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY)
#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY)
#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY)
/* TODO SDMMC */ /* TODO SDMMC */
@@ -367,21 +369,21 @@
#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ #define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) #define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1)
#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) #define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) #define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) #define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) #define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) #define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) #define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY)
/* Configure the APB2 prescaler */ /* Configure the APB2 prescaler */
#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ #define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) #define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1)
#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) #define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY)
#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) #define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY)
#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) #define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY)
#elif defined(MSI_CLOCK_CONFIG) #elif defined(MSI_CLOCK_CONFIG)
@@ -448,40 +450,41 @@
#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ #define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) #define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1)
#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) #define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) #define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) #define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) #define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) #define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY)
#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) #define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY)
/* Configure the APB2 prescaler */ /* Configure the APB2 prescaler */
#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ #define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) #define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1)
#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) #define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY)
#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) #define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY)
#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) #define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY)
#endif #endif
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx /* The timer clock frequencies are automatically defined by hardware.
* otherwise frequency is 2xAPBx. * If the APB prescaler equals 1, the timer clock frequencies are set to the same
* frequency as that of the APB domain. Otherwise they are set to twice.
* Note: TIM1,15,16 are on APB2, others on APB1 * Note: TIM1,15,16 are on APB2, others on APB1
*/ */
#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY #define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY
#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) #define BOARD_TIM2_FREQUENCY STM32L4_HCLK_FREQUENCY
#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) #define BOARD_TIM3_FREQUENCY STM32L4_HCLK_FREQUENCY
#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) #define BOARD_TIM4_FREQUENCY STM32L4_HCLK_FREQUENCY
#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) #define BOARD_TIM5_FREQUENCY STM32L4_HCLK_FREQUENCY
#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) #define BOARD_TIM6_FREQUENCY STM32L4_HCLK_FREQUENCY
#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) #define BOARD_TIM7_FREQUENCY STM32L4_HCLK_FREQUENCY
#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY #define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY
#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY #define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY
#define BOARD_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) #define BOARD_LPTIM1_FREQUENCY STM32L4_HCLK_FREQUENCY
#define BOARD_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) #define BOARD_LPTIM2_FREQUENCY STM32L4_HCLK_FREQUENCY
/************************************************************************************ /************************************************************************************
* Public Data * Public Data