diff --git a/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h b/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h
index 117f8f30adc..134ee2844cd 100644
--- a/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h
+++ b/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h
@@ -714,11 +714,11 @@
 #define RCC_BDCR_LSEBYP             (1 << 2)  /* Bit 2: External Low Speed oscillator Bypass */
 
 #define RCC_BDCR_LSEDRV_SHIFT       (3)       /* Bits 3-4: LSE oscillator drive capability */
-#define RCC_BDCR_LSEDRV_MASK        (3 << DCC_BDCR_LSEDRV_SHIFT)
-#  define RCC_BDCR_LSEDRV_LOWER     (0 << DCC_BDCR_LSEDRV_SHIFT) /* 00: Lower driving capability */
-#  define RCC_BDCR_LSEDRV_MIDLOW    (1 << DCC_BDCR_LSEDRV_SHIFT) /* 01: Medium Low driving capability */
-#  define RCC_BDCR_LSEDRV_MIDHI     (2 << DCC_BDCR_LSEDRV_SHIFT) /* 10: Medium High driving capability*/
-#  define RCC_BDCR_LSEDRV_HIGER     (3 << DCC_BDCR_LSEDRV_SHIFT) /* 11: Higher driving capability */
+#define RCC_BDCR_LSEDRV_MASK        (3 << RCC_BDCR_LSEDRV_SHIFT)
+#  define RCC_BDCR_LSEDRV_LOWER     (0 << RCC_BDCR_LSEDRV_SHIFT) /* 00: Lower driving capability */
+#  define RCC_BDCR_LSEDRV_MIDLOW    (1 << RCC_BDCR_LSEDRV_SHIFT) /* 01: Medium Low driving capability */
+#  define RCC_BDCR_LSEDRV_MIDHI     (2 << RCC_BDCR_LSEDRV_SHIFT) /* 10: Medium High driving capability*/
+#  define RCC_BDCR_LSEDRV_HIGER     (3 << RCC_BDCR_LSEDRV_SHIFT) /* 11: Higher driving capability */
 
 #define RCC_BDCR_LSECSSON           (1 << 5) /* Bit 5: CSS on LSE enable */
 #define RCC_BDCR_LSECSSD            (1 << 6) /* Bit 6: CSS on LSE failure Detection */