arch/mips/src/pic32mz/pic32mz-spi.c: Transfers can now be configured to use DMA.

arch/mips/src/pic32mz/Kconfig

@@ -47,11 +47,15 @@ config ARCH_CHIP_PIC32MZEC
 	bool
 	default n
 	select ARCH_MIPS_M14K
+	select MIPS32_HAVE_ICACHE
+	select MIPS32_HAVE_DCACHE
 
 config ARCH_CHIP_PIC32MZEF
 	bool
 	default n
 	select ARCH_MIPS_M14K
+	select MIPS32_HAVE_ICACHE
+	select MIPS32_HAVE_DCACHE
 
 config PIC32MZ_MVEC
 	bool
@@ -941,12 +945,14 @@ menu "SPI Driver Configuration"
 config PIC32MZ_SPI_INTERRUPTS
 	bool "SPI Interrupt Driven"
 	default n
-	depends on EXPERIMENTAL
+	---help---
+		SPI Transfers are done through interrupts.
 
 config PIC32MZ_SPI_ENHBUF
 	bool "SPI Enhanced Buffer Mode"
 	default n
-	depends on EXPERIMENTAL
+	---help---
+		Enable the enhanced buffer feature (Queue SPI)
 
 config PIC32MZ_SPI_REGDEBUG
 	bool "SPI Register level debug"
@@ -956,6 +962,56 @@ config PIC32MZ_SPI_REGDEBUG
 		Output detailed register-level SPI device debug information.
 		Requires also CONFIG_DEBUG_FEATURES.
 
+config PIC32MZ_SPI_DMA
+	bool "SPI DMA"
+	depends on PIC32MZ_DMA
+	default n
+	---help---
+		Use DMA to improve SPI transfer performance.
+
+config PIC32MZ_SPI_DMATHRESHOLD
+	int "SPI DMA threshold"
+	default 4
+	depends on PIC32MZ_SPI_DMA
+	---help---
+		When SPI DMA is enabled, small DMA transfers will still be performed
+		by polling logic.  But we need a threshold value to determine what
+		is small.  That value is provided by SAMV7_SPI_DMATHRESHOLD.
+
+config PIC32MZ_SPI_DMABUFFSIZE
+	int "SPI DMA buffer size"
+	default 256
+	depends on PIC32MZ_SPI_DMA
+	---help---
+		This buffer is used when transmitting/receveing dummy data.
+		It should be the size of the largest transfer.
+
+config PIC32MZ_SPI_DMA_RXPRIO
+	int "SPI DMA RX priority"
+	default 0
+	range 0 3
+	depends on PIC32MZ_SPI_DMA
+	---help---
+		RX channel priority. From 0 to 3
+
+config PIC32MZ_SPI_DMA_TXPRIO
+	int "SPI DMA TX priority"
+	default 0
+	range 0 3
+	depends on PIC32MZ_SPI_DMA
+	---help---
+		RX channel priority. From 0 to 3
+
+config PIC32MZ_SPI_DMADEBUG
+	bool "SPI DMA transfer debug"
+	depends on PIC32MZ_SPI_DMA && DEBUG_FEATURES && DEBUG_DMA
+	default n
+	---help---
+		Enable special debug instrumentation analyze SPI DMA data transfers.
+		This logic is as non-invasive as possible:  It samples DMA
+		registers at key points in the data transfer and then dumps all of
+		the registers at the end of the transfer.
+
 endmenu # SPI Driver Configuration
 
 menu "I2C Driver Configuration"
@@ -1037,9 +1093,9 @@ config PIC32MZ_ETH_NRXDESC
 		Configured number of Rx descriptors. Default: 4
 
 config PIC32MZ_ETH_PRIORITY
-	int ""
+	int "Interrupt priority"
-	default 28
+	default 7
-	depends on PIC32MZ_ETHERNET
+	depends on PIC32MZ_ETHERNET && ARCH_IRQPRIO
 	---help---
 		Ethernet interrupt priority.  The is default is the highest priority.
 

arch/mips/src/pic32mz/hardware/pic32mz-spi.h

@@ -1,7 +1,7 @@
 /****************************************************************************
  * arch/mips/src/pic32mz/hardware/pic32mz-spi.h
  *
- *   Copyright (C) 2015,m 2019 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2015, 2019 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -253,23 +253,23 @@
 
 /* SPI control register 2 */
 
-#define SPI2_CON2_AUDMOD_SHIFT     (0)       /* Bits 0-1: Audio Protocol Mode */
+#define SPI_CON2_AUDMOD_SHIFT     (0)       /* Bits 0-1: Audio Protocol Mode */
-#define SPI2_CON2_AUDMOD_MASK      (3 << SPI2_CON2_AUDMOD_SHIFT)
+#define SPI_CON2_AUDMOD_MASK      (3 << SPI2_CON2_AUDMOD_SHIFT)
-#  define SPI2_CON2_AUDMOD_I2S     (0 << SPI2_CON2_AUDMOD_SHIFT) /* I2S mode */
+#  define SPI_CON2_AUDMOD_I2S     (0 << SPI2_CON2_AUDMOD_SHIFT) /* I2S mode */
-#  define SPI2_CON2_AUDMOD_LJ      (1 << SPI2_CON2_AUDMOD_SHIFT) /* Left Justified mode */
+#  define SPI_CON2_AUDMOD_LJ      (1 << SPI2_CON2_AUDMOD_SHIFT) /* Left Justified mode */
-#  define SPI2_CON2_AUDMOD_RJ      (2 << SPI2_CON2_AUDMOD_SHIFT) /* Right Justified mode */
+#  define SPI_CON2_AUDMOD_RJ      (2 << SPI2_CON2_AUDMOD_SHIFT) /* Right Justified mode */
-#  define SPI2_CON2_AUDMOD_PCM     (3 << SPI2_CON2_AUDMOD_SHIFT) /* PCM/DSP mode */
+#  define SPI_CON2_AUDMOD_PCM     (3 << SPI2_CON2_AUDMOD_SHIFT) /* PCM/DSP mode */
                                              /* Bit 2: Reserved */
-#define SPI2_CON2_AUDMONO          (1 << 3)  /* Bit 3:  Transmit Audio Data Format */
+#define SPI_CON2_AUDMONO          (1 << 3)  /* Bit 3:  Transmit Audio Data Format */
                                              /* Bits 5-6: Reserved */
-#define SPI2_CON2_AUDEN            (1 << 7)  /* Bit 7:  Enable Audio CODEC Support */
+#define SPI_CON2_AUDEN            (1 << 7)  /* Bit 7:  Enable Audio CODEC Support */
-#define SPI2_CON2_IGNTUR           (1 << 8)  /* Bit 8:  Ignore Transmit Underrun bit */
+#define SPI_CON2_IGNTUR           (1 << 8)  /* Bit 8:  Ignore Transmit Underrun bit */
-#define SPI2_CON2_IGNROV           (1 << 9)  /* Bit 9:  Ignore Receive Overflow */
+#define SPI_CON2_IGNROV           (1 << 9)  /* Bit 9:  Ignore Receive Overflow */
-#define SPI2_CON2_SPITUREN         (1 << 10) /* Bit 10: Enable Interrupt Events via SPITUR */
+#define SPI_CON2_SPITUREN         (1 << 10) /* Bit 10: Enable Interrupt Events via SPITUR */
-#define SPI2_CON2_SPIROVEN         (1 << 11) /* Bit 11: Enable Interrupt Events via SPIROV */
+#define SPI_CON2_SPIROVEN         (1 << 11) /* Bit 11: Enable Interrupt Events via SPIROV */
-#define SPI2_CON2_FRMERREN         (1 << 12) /* Bit 12: Enable Interrupt Events via FRMERR */
+#define SPI_CON2_FRMERREN         (1 << 12) /* Bit 12: Enable Interrupt Events via FRMERR */
                                              /* Bits 13-14: Reserved */
-#define SPI2_CON2_SPISGNEXT        (1 << 15) /* Bit 15 : Sign Extend Read Data from the RX FIFO */
+#define SPI_CON2_SPISGNEXT        (1 << 15) /* Bit 15 : Sign Extend Read Data from the RX FIFO */
                                              /* Bits 16-31: Reserved */
 
 /* SPI status register */

arch/mips/src/pic32mz/pic32mz-dma.h

@@ -110,7 +110,7 @@ enum pic32mz_dma_chmode_e
 
 /* Interrupt type arguments for pic32mz_dma_intctrl. */
 
-enum pic32Mz_dma_event_e
+enum pic32mz_dma_event_e
 {
   PIC32MZ_DMA_INT_DISABLE   = 0U,
   PIC32MZ_DMA_INT_ADDRERR   = 1 << 0U,  /* Address error interrupt */