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Merged nuttx/nuttx into master

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Aleksandr Vyhovanec
2017-01-25 13:58:30 +03:00
parent 30163af89e ff61d8f69d
commit cb64d4954b
615 changed files with 8056 additions and 1520 deletions
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arch/arm/Kconfig
+9
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@@ -302,6 +302,10 @@ config ARCH_CORTEXM0
select ARCH_HAVE_IRQPRIO select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_RESET select ARCH_HAVE_RESET
config ARCH_CORTEXM23
bool
default n
config ARCH_CORTEXM3 config ARCH_CORTEXM3
bool bool
default n default n
@@ -310,6 +314,10 @@ config ARCH_CORTEXM3
select ARCH_HAVE_HIPRI_INTERRUPT select ARCH_HAVE_HIPRI_INTERRUPT
select ARCH_HAVE_RESET select ARCH_HAVE_RESET
config ARCH_CORTEXM33
bool
default n
config ARCH_CORTEXM4 config ARCH_CORTEXM4
bool bool
default n default n
@@ -325,6 +333,7 @@ config ARCH_CORTEXM7
select ARCH_HAVE_IRQPRIO select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_RAMVECTORS select ARCH_HAVE_RAMVECTORS
select ARCH_HAVE_HIPRI_INTERRUPT select ARCH_HAVE_HIPRI_INTERRUPT
select ARCH_HAVE_RESET
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEXA5 config ARCH_CORTEXA5
arch/arm/include/sam34/chip.h
+35 -15
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@@ -543,21 +543,21 @@
/* AT91SAM4S Family *****************************************************************/ /* AT91SAM4S Family *****************************************************************/
/* /*
* FEATURE SAM4SD32C SAM4SD32B SAM4SD16C SAM4SD16B SAM4SA16C SAM4SA16B SAM4S16C SAM4S16B SAM4S8C SAM4S8B * FEATURE SAM4SD32C SAM4SD32B SAM4SD16C SAM4SD16B SAM4SA16C SAM4SA16B SAM4S16C SAM4S16B SAM4S8C SAM4S8B SAM4S4C
* ------------- --------- --------- --------- --------- --------- --------- -------- -------- ------- ------- * ------------- --------- --------- --------- --------- --------- --------- -------- -------- ------- ------- -------
* Flash 2x1MB 2x1MB 2x512KB 1x1MB 1x1MB 1x1MB 1x1MB 1x1MB 1x512KB 1x512KB * Flash 2x1MB 2x1MB 2x512KB 1x1MB 1x1MB 1x1MB 1x1MB 1x1MB 1x512KB 1x512KB 1x256KB
* SRAM 160KB 160KB 160KB 160KB 160KB 160KB 128KB 128KB 128KB 128KB * SRAM 160KB 160KB 160KB 160KB 160KB 160KB 128KB 128KB 128KB 128KB 64KB
* HCACHE 2KB 2KB 2KB 2KB 2KB 2KB - - - - * HCACHE 2KB 2KB 2KB 2KB 2KB 2KB - - - - -
* Pins 100 64 100 64 100 64 100 64 100 64 * Pins 100 64 100 64 100 64 100 64 100 64 100
* No. PIOs 79 47 79 47 79 47 79 47 79 47 * No. PIOs 79 47 79 47 79 47 79 47 79 47 79
* Ext. BUS Yes No Yes No Yes No Yes No Yes No * Ext. BUS Yes No Yes No Yes No Yes No Yes No Yes
* 12-bit ADC 16 ch 11 ch 16 ch 11 ch 16 ch 11 ch 16 ch 11 ch 16 ch 11 ch * 12-bit ADC 16 ch 11 ch 16 ch 11 ch 16 ch 11 ch 16 ch 11 ch 16 ch 11 ch 16 ch
* 12-bit DAC 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch * 12-bit DAC 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch
* Timer Counter 6 ch 3 ch 6 ch 3 ch 6 ch 3 ch 6 ch 3 ch 6 ch 3 ch * Timer Counter 6 ch 3 ch 6 ch 3 ch 6 ch 3 ch 6 ch 3 ch 6 ch 3 ch 6 ch
* PDC 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch * PDC 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch
* USART 2 2 2 2 2 2 2 2 2 2 * USART 2 2 2 2 2 2 2 2 2 2 2
* UART 2 2 2 2 2 2 2 2 2 2 * UART 2 2 2 2 2 2 2 2 2 2 2
* HSMCI Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes * HSMCI Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
*/ */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4SD32C) #elif defined(CONFIG_ARCH_CHIP_ATSAM4SD32C)
@@ -760,6 +760,26 @@
# define SAM34_NUDPFS 1 /* 1 USB full speed device */ # define SAM34_NUDPFS 1 /* 1 USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */ # define SAM34_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4S4C)
/* Internal memory */
# define SAM34_FLASH_SIZE (256*1024) /* 256KB */
# define SAM34_SRAM0_SIZE (64*1024) /* 64KB */
# define SAM34_SRAM1_SIZE 0 /* None */
# define SAM34_NFCSRAM_SIZE 0 /* None */
/* Peripherals */
# define SAM34_NDMACHAN 0 /* No DMAC Channels */
# define SAM34_NPDCCHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM34_NSLCD 0 /* No segment LCD interface */
# define SAM34_NAESA 0 /* No advanced encryption standard */
# define SAM34_NUDPHS 0 /* No USB high speed device */
# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
# define SAM34_NUDPFS 1 /* 1 USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
/* AT91SAM4E Family *****************************************************************/ /* AT91SAM4E Family *****************************************************************/
/* FEATURE SAM4E16E SAM4E8E SAM4E16C SAM4E8C /* FEATURE SAM4E16E SAM4E8E SAM4E16C SAM4E8C
* ----------- --------- -------- -------- -------- * ----------- --------- -------- -------- --------
arch/arm/src/a1x/Make.defs
+2 -6
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@@ -59,10 +59,6 @@ CMN_ASRCS += arm_testset.S
CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S
CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S
ifeq ($(CONFIG_ARCH_MEMCPY),y)
CMN_ASRCS += arm_memcpy.S
endif
# Common C source files # Common C source files
CMN_CSRCS = up_initialize.c up_idle.c up_interruptcontext.c up_exit.c CMN_CSRCS = up_initialize.c up_idle.c up_interruptcontext.c up_exit.c
@@ -112,9 +108,9 @@ endif
endif endif
ifeq ($(CONFIG_ELF),y) ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += arm_elf.c arm_coherent_dcache.c CMN_CSRCS += arm_coherent_dcache.c
else ifeq ($(CONFIG_MODULE),y) else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += arm_elf.c arm_coherent_dcache.c CMN_CSRCS += arm_coherent_dcache.c
endif endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
arch/arm/src/armv7-a/Kconfig
+7
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@@ -133,10 +133,12 @@ choice
config ARMV7A_TOOLCHAIN_BUILDROOT config ARMV7A_TOOLCHAIN_BUILDROOT
bool "Buildroot (Cygwin or Linux)" bool "Buildroot (Cygwin or Linux)"
select ARM_TOOLCHAIN_GNU
depends on !WINDOWS_NATIVE depends on !WINDOWS_NATIVE
config ARMV7A_TOOLCHAIN_CODESOURCERYL config ARMV7A_TOOLCHAIN_CODESOURCERYL
bool "CodeSourcery GNU toolchain under Linux" bool "CodeSourcery GNU toolchain under Linux"
select ARM_TOOLCHAIN_GNU
depends on HOST_LINUX depends on HOST_LINUX
---help--- ---help---
For use with the GNU toolchain built with the NuttX buildroot package. For use with the GNU toolchain built with the NuttX buildroot package.
@@ -145,20 +147,24 @@ config ARMV7A_TOOLCHAIN_CODESOURCERYL
config ARMV7A_TOOLCHAIN_CODESOURCERYW config ARMV7A_TOOLCHAIN_CODESOURCERYW
bool "CodeSourcery GNU toolchain under Windows" bool "CodeSourcery GNU toolchain under Windows"
select ARM_TOOLCHAIN_GNU
depends on TOOLCHAIN_WINDOWS depends on TOOLCHAIN_WINDOWS
config ARMV7A_TOOLCHAIN_DEVKITARM config ARMV7A_TOOLCHAIN_DEVKITARM
bool "devkitARM GNU toolchain" bool "devkitARM GNU toolchain"
select ARM_TOOLCHAIN_GNU
depends on TOOLCHAIN_WINDOWS depends on TOOLCHAIN_WINDOWS
config ARMV7A_TOOLCHAIN_GNU_EABIL config ARMV7A_TOOLCHAIN_GNU_EABIL
bool "Generic GNU EABI toolchain under Linux (or other POSIX environment)" bool "Generic GNU EABI toolchain under Linux (or other POSIX environment)"
select ARM_TOOLCHAIN_GNU
---help--- ---help---
This option should work for any modern GNU toolchain (GCC 4.5 or newer) This option should work for any modern GNU toolchain (GCC 4.5 or newer)
configured for arm-none-eabi-. configured for arm-none-eabi-.
config ARMV7A_TOOLCHAIN_GNU_EABIW config ARMV7A_TOOLCHAIN_GNU_EABIW
bool "Generic GNU EABI toolchain under Windows" bool "Generic GNU EABI toolchain under Windows"
select ARM_TOOLCHAIN_GNU
depends on TOOLCHAIN_WINDOWS depends on TOOLCHAIN_WINDOWS
---help--- ---help---
This option should work for any modern GNU toolchain (GCC 4.5 or newer) This option should work for any modern GNU toolchain (GCC 4.5 or newer)
@@ -166,6 +172,7 @@ config ARMV7A_TOOLCHAIN_GNU_EABIW
config ARMV7A_TOOLCHAIN_GNU_OABI config ARMV7A_TOOLCHAIN_GNU_OABI
bool "Generic GNU OABI toolchain" bool "Generic GNU OABI toolchain"
select ARM_TOOLCHAIN_GNU
---help--- ---help---
This option should work for any GNU toolchain configured for arm-elf-. This option should work for any GNU toolchain configured for arm-elf-.
arch/arm/src/armv7-a/arm_cpupause.c
+4 -4
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@@ -244,14 +244,14 @@ int up_cpu_pause(int cpu)
{ {
int ret; int ret;
DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());
#ifdef CONFIG_SCHED_INSTRUMENTATION #ifdef CONFIG_SCHED_INSTRUMENTATION
/* Notify of the pause event */ /* Notify of the pause event */
sched_note_cpu_pause(this_task(), cpu); sched_note_cpu_pause(this_task(), cpu);
#endif #endif
DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());
/* Take the both spinlocks. The g_cpu_wait spinlock will prevent the SGI2 /* Take the both spinlocks. The g_cpu_wait spinlock will prevent the SGI2
* handler from returning until up_cpu_resume() is called; g_cpu_paused * handler from returning until up_cpu_resume() is called; g_cpu_paused
* is a handshake that will prefent this function from returning until * is a handshake that will prefent this function from returning until
@@ -313,14 +313,14 @@ int up_cpu_pause(int cpu)
int up_cpu_resume(int cpu) int up_cpu_resume(int cpu)
{ {
DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());
#ifdef CONFIG_SCHED_INSTRUMENTATION #ifdef CONFIG_SCHED_INSTRUMENTATION
/* Notify of the resume event */ /* Notify of the resume event */
sched_note_cpu_resume(this_task(), cpu); sched_note_cpu_resume(this_task(), cpu);
#endif #endif
DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());
/* Release the spinlock. Releasing the spinlock will cause the SGI2 /* Release the spinlock. Releasing the spinlock will cause the SGI2
* handler on 'cpu' to continue and return from interrupt to the newly * handler on 'cpu' to continue and return from interrupt to the newly
* established thread. * established thread.
arch/arm/src/armv7-a/arm_schedulesigaction.c
+1 -1
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@@ -320,7 +320,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
if (cpu != me) if (cpu != me)
{ {
up_cpu_pause(cpu); up_cpu_resume(cpu);
} }
} }
} }
arch/arm/src/armv7-m/up_coherent_dcache.c
-12
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@@ -46,18 +46,6 @@
#include <nuttx/arch.h> #include <nuttx/arch.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/**************************************************************************** /****************************************************************************
* Public Functions * Public Functions
****************************************************************************/ ****************************************************************************/
arch/arm/src/armv7-m/up_copyarmstate.c
-12
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@@ -48,18 +48,6 @@
#if defined(CONFIG_ARCH_FPU) && \ #if defined(CONFIG_ARCH_FPU) && \
(!defined(CONFIG_ARMV7M_CMNVECTOR) || defined(CONFIG_ARMV7M_LAZYFPU)) (!defined(CONFIG_ARMV7M_CMNVECTOR) || defined(CONFIG_ARMV7M_LAZYFPU))
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/**************************************************************************** /****************************************************************************
* Public Functions * Public Functions
****************************************************************************/ ****************************************************************************/
arch/arm/src/armv7-m/up_copyfullstate.c
-12
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@@ -44,18 +44,6 @@
#include "up_internal.h" #include "up_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/**************************************************************************** /****************************************************************************
* Public Functions * Public Functions
****************************************************************************/ ****************************************************************************/
arch/arm/src/armv7-m/up_initialstate.c
-12
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@@ -51,18 +51,6 @@
#include "psr.h" #include "psr.h"
#include "exc_return.h" #include "exc_return.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/**************************************************************************** /****************************************************************************
* Public Functions * Public Functions
****************************************************************************/ ****************************************************************************/
arch/arm/src/armv7-m/up_ramvec_initialize.c
-8
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@@ -90,14 +90,6 @@
up_vector_t g_ram_vectors[ARMV7M_VECTAB_SIZE] up_vector_t g_ram_vectors[ARMV7M_VECTAB_SIZE]
__attribute__ ((section (".ram_vectors"), aligned (RAMVEC_ALIGN))); __attribute__ ((section (".ram_vectors"), aligned (RAMVEC_ALIGN)));
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/**************************************************************************** /****************************************************************************
* Public Functions * Public Functions
****************************************************************************/ ****************************************************************************/
arch/arm/src/armv7-m/up_schedulesigaction.c
+1 -1
View File
@@ -372,7 +372,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
if (cpu != me) if (cpu != me)
{ {
up_cpu_pause(cpu); up_cpu_resume(cpu);
} }
} }
} }
arch/arm/src/armv7-r/Kconfig
+7
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@@ -149,10 +149,12 @@ choice
config ARMV7R_TOOLCHAIN_BUILDROOT config ARMV7R_TOOLCHAIN_BUILDROOT
bool "Buildroot (Cygwin or Linux)" bool "Buildroot (Cygwin or Linux)"
select ARM_TOOLCHAIN_GNU
depends on !WINDOWS_NATIVE depends on !WINDOWS_NATIVE
config ARMV7R_TOOLCHAIN_CODESOURCERYL config ARMV7R_TOOLCHAIN_CODESOURCERYL
bool "CodeSourcery GNU toolchain under Linux" bool "CodeSourcery GNU toolchain under Linux"
select ARM_TOOLCHAIN_GNU
depends on HOST_LINUX depends on HOST_LINUX
---help--- ---help---
For use with the GNU toolchain built with the NuttX buildroot package. For use with the GNU toolchain built with the NuttX buildroot package.
@@ -161,20 +163,24 @@ config ARMV7R_TOOLCHAIN_CODESOURCERYL
config ARMV7R_TOOLCHAIN_CODESOURCERYW config ARMV7R_TOOLCHAIN_CODESOURCERYW
bool "CodeSourcery GNU toolchain under Windows" bool "CodeSourcery GNU toolchain under Windows"
select ARM_TOOLCHAIN_GNU
depends on TOOLCHAIN_WINDOWS depends on TOOLCHAIN_WINDOWS
config ARMV7R_TOOLCHAIN_DEVKITARM config ARMV7R_TOOLCHAIN_DEVKITARM
bool "devkitARM GNU toolchain" bool "devkitARM GNU toolchain"
select ARM_TOOLCHAIN_GNU
depends on TOOLCHAIN_WINDOWS depends on TOOLCHAIN_WINDOWS
config ARMV7R_TOOLCHAIN_GNU_EABIL config ARMV7R_TOOLCHAIN_GNU_EABIL
bool "Generic GNU EABI toolchain under Linux (or other POSIX environment)" bool "Generic GNU EABI toolchain under Linux (or other POSIX environment)"
select ARM_TOOLCHAIN_GNU
---help--- ---help---
This option should work for any modern GNU toolchain (GCC 4.5 or newer) This option should work for any modern GNU toolchain (GCC 4.5 or newer)
configured for arm-none-eabi-. configured for arm-none-eabi-.
config ARMV7R_TOOLCHAIN_GNU_EABIW config ARMV7R_TOOLCHAIN_GNU_EABIW
bool "Generic GNU EABI toolchain under Windows" bool "Generic GNU EABI toolchain under Windows"
select ARM_TOOLCHAIN_GNU
depends on TOOLCHAIN_WINDOWS depends on TOOLCHAIN_WINDOWS
---help--- ---help---
This option should work for any modern GNU toolchain (GCC 4.5 or newer) This option should work for any modern GNU toolchain (GCC 4.5 or newer)
@@ -182,6 +188,7 @@ config ARMV7R_TOOLCHAIN_GNU_EABIW
config ARMV7R_TOOLCHAIN_GNU_OABI config ARMV7R_TOOLCHAIN_GNU_OABI
bool "Generic GNU OABI toolchain" bool "Generic GNU OABI toolchain"
select ARM_TOOLCHAIN_GNU
---help--- ---help---
This option should work for any GNU toolchain configured for arm-elf-. This option should work for any GNU toolchain configured for arm-elf-.
arch/arm/src/c5471/Make.defs
-6
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@@ -45,12 +45,6 @@ CMN_CSRCS += up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c
CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_syscall.c up_unblocktask.c CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_syscall.c up_unblocktask.c
CMN_CSRCS += up_undefinedinsn.c up_usestack.c up_vfork.c CMN_CSRCS += up_undefinedinsn.c up_usestack.c up_vfork.c
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y) ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c CMN_CSRCS += up_checkstack.c
endif endif
arch/arm/src/dm320/Make.defs
-6
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@@ -46,12 +46,6 @@ CMN_CSRCS += up_reprioritizertr.c up_schedulesigaction.c
CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_syscall.c up_unblocktask.c CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_syscall.c up_unblocktask.c
CMN_CSRCS += up_undefinedinsn.c up_usestack.c up_vfork.c CMN_CSRCS += up_undefinedinsn.c up_usestack.c up_vfork.c
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y) ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c CMN_CSRCS += up_checkstack.c
endif endif
arch/arm/src/efm32/Make.defs
-10
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@@ -63,10 +63,6 @@ ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
endif endif
ifeq ($(CONFIG_ARCH_MEMCPY),y)
CMN_ASRCS += up_memcpy.S
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y) ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
ifneq ($(CONFIG_DISABLE_SIGNALS),y) ifneq ($(CONFIG_DISABLE_SIGNALS),y)
@@ -79,12 +75,6 @@ ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c CMN_CSRCS += up_checkstack.c
endif endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c
endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y) ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
arch/arm/src/imx1/Make.defs
-6
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@@ -45,12 +45,6 @@ CMN_CSRCS += up_reprioritizertr.c up_schedulesigaction.c
CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_syscall.c up_unblocktask.c CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_syscall.c up_unblocktask.c
CMN_CSRCS += up_undefinedinsn.c up_usestack.c up_vfork.c CMN_CSRCS += up_undefinedinsn.c up_usestack.c up_vfork.c
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y) ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c CMN_CSRCS += up_checkstack.c
endif endif
arch/arm/src/imx6/Make.defs
+2 -6
View File
@@ -62,10 +62,6 @@ CMN_ASRCS += arm_testset.S
CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S
CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S
ifeq ($(CONFIG_ARCH_MEMCPY),y)
CMN_ASRCS += arm_memcpy.S
endif
# Common C source files # Common C source files
CMN_CSRCS = up_initialize.c up_idle.c up_interruptcontext.c up_exit.c CMN_CSRCS = up_initialize.c up_idle.c up_interruptcontext.c up_exit.c
@@ -124,9 +120,9 @@ endif
endif endif
ifeq ($(CONFIG_ELF),y) ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += arm_elf.c arm_coherent_dcache.c CMN_CSRCS += arm_coherent_dcache.c
else ifeq ($(CONFIG_MODULE),y) else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += arm_elf.c arm_coherent_dcache.c CMN_CSRCS += arm_coherent_dcache.c
endif endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
arch/arm/src/kinetis/Make.defs
+4 -11
View File
@@ -1,7 +1,7 @@
############################################################################ ############################################################################
# arch/arm/src/kinetis/Make.defs # arch/arm/src/kinetis/Make.defs
# #
# Copyright (C) 2011, 2013-2016 Gregory Nutt. All rights reserved. # Copyright (C) 2011, 2013-2017 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org> # Author: Gregory Nutt <gnutt@nuttx.org>
# #
# Redistribution and use in source and binary forms, with or without # Redistribution and use in source and binary forms, with or without
@@ -71,10 +71,6 @@ ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
endif endif
ifeq ($(CONFIG_ARCH_MEMCPY),y)
CMN_ASRCS += up_memcpy.S
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y) ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
ifneq ($(CONFIG_DISABLE_SIGNALS),y) ifneq ($(CONFIG_DISABLE_SIGNALS),y)
@@ -97,12 +93,6 @@ CMN_CSRCS += up_etherstub.c
endif endif
endif endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c
endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y) ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
@@ -174,6 +164,9 @@ endif
ifeq ($(CONFIG_RTC),y) ifeq ($(CONFIG_RTC),y)
CHIP_CSRCS += kinetis_rtc.c CHIP_CSRCS += kinetis_rtc.c
ifeq ($(CONFIG_RTC_DRIVER),y)
CHIP_CSRCS += kinetis_rtc_lowerhalf.c
endif
endif endif
ifeq ($(CONFIG_NET),y) ifeq ($(CONFIG_NET),y)
arch/arm/src/kinetis/chip/kinetis_rtc.h
+93 -23
View File
@@ -1,7 +1,7 @@
/************************************************************************************ /************************************************************************************
* arch/arm/src/kinetis/chip/kinetis_rtc.h * arch/arm/src/kinetis/chip/kinetis_rtc.h
* *
* Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Copyright (C) 2011, 2016-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@@ -52,6 +52,27 @@
/* Register Offsets *****************************************************************/ /* Register Offsets *****************************************************************/
/* NXP/Freescale has familes and technology generations (sometimes seen as processor
* speed). These are organized into feature families, and faster speeds sometimes
* have extended features. Families are K02 K10 K20 K22 K24 K30 K40 K50 K60 K64 K65
* K66 K70 K80
*
* So far only two variations/generations on the RTC have been discovered.
* GEN1 RTC_TSR TPR TAR TCR CR SR LR IER WAR RAR
* GEN2 RTC_TSR TPR TAR TCR CR SR LR IER TTSR MER MCLR MCHR WAR RAR
*
* KINETIS RTC_GEN1 K20P32-->K20P81M K22 K40 K50 K60@100Mhz K64 120MHz
* Assumed K10 K11
*
* KINETIS_RTC_GEN2 K02 K20P144M K26P169 K60@120Mhz K65x K66x
*
* Note current naming doesn't allow GEN1:MK60FN...Q10 & GEN2:MK60FN...Q12
*/
#if defined(KINETIS_K26) || defined(KINETIS_K65) || defined(KINETIS_K66)
# define KINETIS_RTC_GEN2
#endif
#define KINETIS_RTC_TSR_OFFSET 0x0000 /* RTC Time Seconds Register */ #define KINETIS_RTC_TSR_OFFSET 0x0000 /* RTC Time Seconds Register */
#define KINETIS_RTC_TPR_OFFSET 0x0004 /* RTC Time Prescaler Register */ #define KINETIS_RTC_TPR_OFFSET 0x0004 /* RTC Time Prescaler Register */
#define KINETIS_RTC_TAR_OFFSET 0x0008 /* RTC Time Alarm Register */ #define KINETIS_RTC_TAR_OFFSET 0x0008 /* RTC Time Alarm Register */
@@ -59,12 +80,23 @@
#define KINETIS_RTC_CR_OFFSET 0x0010 /* RTC Control Register */ #define KINETIS_RTC_CR_OFFSET 0x0010 /* RTC Control Register */
#define KINETIS_RTC_SR_OFFSET 0x0014 /* RTC Status Register */ #define KINETIS_RTC_SR_OFFSET 0x0014 /* RTC Status Register */
#define KINETIS_RTC_LR_OFFSET 0x0018 /* RTC Lock Register */ #define KINETIS_RTC_LR_OFFSET 0x0018 /* RTC Lock Register */
#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K64) #define KINETIS_RTC_IER_OFFSET 0x001c /* RTC Interrupt Enable Register (K40) */
# define KINETIS_RTC_IER_OFFSET 0x001c /* RTC Interrupt Enable Register (K40) */
#endif
#ifdef KINETIS_K60 #ifdef KINETIS_K60
/* Haven't found a processor or nuttx file where KINETIS_RTC_CCR is in it
* from K60P100M100SF2V2RM this would be called KINETIS_RTC_IER_OFFSET.
*/
# define KINETIS_RTC_CCR_OFFSET 0x001c /* RTC Chip Configuration Register (K60) */ # define KINETIS_RTC_CCR_OFFSET 0x001c /* RTC Chip Configuration Register (K60) */
#endif #endif
#ifdef KINETIS_RTC_GEN2
# define KINETIS_RTC_TTSR_OFFSET 0x0020 /* RTC Tamper Times Seconds Register */
# define KINETIS_RTC_MR_OFFSET 0x0024 /* RTC Monotonic Enable Register */
# define KINETIS_RTC_MCLR_OFFSET 0x0028 /* RTC Monotonic Counter Low Register */
# define KINETIS_RTC_MCHR_OFFSET 0x002c /* RTC Monotonic Counter High Register */
#endif
#define KINETIS_RTC_WAR_OFFSET 0x0800 /* RTC Write Access Register */ #define KINETIS_RTC_WAR_OFFSET 0x0800 /* RTC Write Access Register */
#define KINETIS_RTC_RAR_OFFSET 0x0804 /* RTC Read Access Register */ #define KINETIS_RTC_RAR_OFFSET 0x0804 /* RTC Read Access Register */
@@ -77,12 +109,21 @@
#define KINETIS_RTC_CR (KINETIS_RTC_BASE+KINETIS_RTC_CR_OFFSET) #define KINETIS_RTC_CR (KINETIS_RTC_BASE+KINETIS_RTC_CR_OFFSET)
#define KINETIS_RTC_SR (KINETIS_RTC_BASE+KINETIS_RTC_SR_OFFSET) #define KINETIS_RTC_SR (KINETIS_RTC_BASE+KINETIS_RTC_SR_OFFSET)
#define KINETIS_RTC_LR (KINETIS_RTC_BASE+KINETIS_RTC_LR_OFFSET) #define KINETIS_RTC_LR (KINETIS_RTC_BASE+KINETIS_RTC_LR_OFFSET)
#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K64) #define KINETIS_RTC_IER (KINETIS_RTC_BASE+KINETIS_RTC_IER_OFFSET)
# define KINETIS_RTC_IER (KINETIS_RTC_BASE+KINETIS_RTC_IER_OFFSET)
#endif
#ifdef KINETIS_K60 #ifdef KINETIS_K60
/* From K60P100M100SF2V2RM this would be called KINETIS_RTC_IER */
# define KINETIS_CCR_IER (KINETIS_RTC_BASE+KINETIS_RTC_CCR_OFFSET) # define KINETIS_CCR_IER (KINETIS_RTC_BASE+KINETIS_RTC_CCR_OFFSET)
#endif #endif
#ifdef KINETIS_RTC_GEN2
# define KINETIS_RTC_TTSR (KINETIS_RTC_BASE+KINETIS_RTC_TTSR_OFFSET)
# define KINETIS_RTC_MER (KINETIS_RTC_BASE+KINETIS_RTC_MER_OFFSET)
# define KINETIS_RTC_MCLR (KINETIS_RTC_BASE+KINETIS_RTC_MCLR_OFFSET)
# define KINETIS_RTC_MCHR (KINETIS_RTC_BASE+KINETIS_RTC_MCHR_OFFSET)
#endif
#define KINETIS_RTC_WAR (KINETIS_RTC_BASE+KINETIS_RTC_WAR_OFFSET) #define KINETIS_RTC_WAR (KINETIS_RTC_BASE+KINETIS_RTC_WAR_OFFSET)
#define KINETIS_RTC_RAR (KINETIS_RTC_BASE+KINETIS_RTC_RAR_OFFSET) #define KINETIS_RTC_RAR (KINETIS_RTC_BASE+KINETIS_RTC_RAR_OFFSET)
@@ -126,8 +167,12 @@
#define RTC_SR_TIF (1 << 0) /* Bit 0: Time Invalid Flag */ #define RTC_SR_TIF (1 << 0) /* Bit 0: Time Invalid Flag */
#define RTC_SR_TOF (1 << 1) /* Bit 1: Time Overflow Flag */ #define RTC_SR_TOF (1 << 1) /* Bit 1: Time Overflow Flag */
/* Bit 3: Reserved */
#define RTC_SR_TAF (1 << 2) /* Bit 2: Time Alarm Flag */ #define RTC_SR_TAF (1 << 2) /* Bit 2: Time Alarm Flag */
#ifdef KINETIS_RTC_GEN2
# define RTC_SR_MOF (1 << 3) /* Bit 3: Time Monotonic overflow Flag */
#endif
/* Bit 3: Reserved RTC_GEN1 */
#define RTC_SR_TCE (1 << 4) /* Bit 4: Time Counter Enable */ #define RTC_SR_TCE (1 << 4) /* Bit 4: Time Counter Enable */
/* Bits 5-31: Reserved */ /* Bits 5-31: Reserved */
/* RTC Lock Register (32-bits) */ /* RTC Lock Register (32-bits) */
@@ -135,24 +180,33 @@
#define RTC_LR_TCL (1 << 3) /* Bit 3: Time Compensation Lock */ #define RTC_LR_TCL (1 << 3) /* Bit 3: Time Compensation Lock */
#define RTC_LR_CRL (1 << 4) /* Bit 4: Control Register Lock */ #define RTC_LR_CRL (1 << 4) /* Bit 4: Control Register Lock */
#define RTC_LR_SRL (1 << 5) /* Bit 5: Status Register Lock */ #define RTC_LR_SRL (1 << 5) /* Bit 5: Status Register Lock */
#if defined(KINETIS_K20) || defined(KINETIS_K40) #define RTC_LR_LRL (1 << 6) /* Bit 6: Lock Register Lock */
# define RTC_LR_LRL (1 << 6) /* Bit 6: Lock Register Lock (K40) */ /* Bit 7: Reserved */
#ifdef KINETIS_RTC_GEN2
# define RTC_LR_TTSL (1 << 8) /* Bit 8: Tamper Time Seconds Lock */
# define RTC_LR_MEL (1 << 9) /* Bit 9: Monotonic Enable lock */
# define RTC_LR_MCLL (1 << 10) /* Bit 10: Monotoic Counter Low Lock */
# define RTC_LR_MCHL (1 << 11) /* Bit 10: Monotoic Counter High Lock */
#endif #endif
/* Bits 7-31: Reserved */ /* Bits 12-31: Reserved */
/* RTC Interrupt Enable Register (32-bits, K40) */ /* RTC Interrupt Enable Register (32-bits, K40) */
#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K64)
# define RTC_IER_TIIE (1 << 0) /* Bit 0: Time Invalid Interrupt Enable */ # define RTC_IER_TIIE (1 << 0) /* Bit 0: Time Invalid Interrupt Enable */
# define RTC_IER_TOIE (1 << 1) /* Bit 1: Time Overflow Interrupt Enable */ # define RTC_IER_TOIE (1 << 1) /* Bit 1: Time Overflow Interrupt Enable */
# define RTC_IER_TAIE (1 << 2) /* Bit 2: Time Alarm Interrupt Enable */ # define RTC_IER_TAIE (1 << 2) /* Bit 2: Time Alarm Interrupt Enable */
/* Bit 3: Reserved */
# define RTC_IER_TSIE (1 << 4) /* Bit 4: Time Seconds Interrupt Enable */ #ifdef KINETIS_RTC_GEN2
/* Bits 5-31: Reserved */ # define RTC_IER_MOIE (1 << 3) /* Bit 3: Monotonic Overflow Interrupt Enable */
#endif #endif
/* RTC Chip Configuration Register (32-bits,K60) */ # define RTC_IER_TSIE (1 << 4) /* Bit 4: Time Seconds Interrupt Enable */
/* Bits 5-6: Reserved */
# define RTC_IER_WPON (1 << 7) /* Bit 7: Wakeup Pin On */
#ifdef KINETIS_K60 #ifdef KINETIS_K60
/* RTC Chip Configuration Register (32-bits,K60) */
/* Haven't found this in K60P100M100SF2V2RM */
# define RTC_CCR_CONFIG_SHIFT (0) /* Bits 0-7: Chip Configuration */ # define RTC_CCR_CONFIG_SHIFT (0) /* Bits 0-7: Chip Configuration */
# define RTC_CCR_CONFIG_MASK (0xff << RTC_CCR_CONFIG_SHIFT) # define RTC_CCR_CONFIG_MASK (0xff << RTC_CCR_CONFIG_SHIFT)
/* Bits 8-31: Reserved */ /* Bits 8-31: Reserved */
@@ -167,10 +221,11 @@
#define RTC_WAR_CRW (1 << 4) /* Bit 4: Control Register Write */ #define RTC_WAR_CRW (1 << 4) /* Bit 4: Control Register Write */
#define RTC_WAR_SRW (1 << 5) /* Bit 5: Status Register Write */ #define RTC_WAR_SRW (1 << 5) /* Bit 5: Status Register Write */
#define RTC_WAR_LRW (1 << 6) /* Bit 6: Lock Register Write */ #define RTC_WAR_LRW (1 << 6) /* Bit 6: Lock Register Write */
#if defined(KINETIS_K40) || defined(KINETIS_K64) #define RTC_WAR_IERW (1 << 7) /* Bit 7: Interrupt Enable Register Write */
# define RTC_WAR_IERW (1 << 7) /* Bit 7: Interrupt Enable Register Write */
#endif
#ifdef KINETIS_K60 #ifdef KINETIS_K60
/* This looks like old name, from K60P100M100SF2V2RM bit 7 would be called RTC_RAR_IERW */
# define RTC_WAR_CCRW (1 << 7) /* Bit 7: Chip Config Register Write */ # define RTC_WAR_CCRW (1 << 7) /* Bit 7: Chip Config Register Write */
#endif #endif
/* Bits 8-31: Reserved */ /* Bits 8-31: Reserved */
@@ -183,13 +238,28 @@
#define RTC_RAR_CRR (1 << 4) /* Bit 4: Control Register Read */ #define RTC_RAR_CRR (1 << 4) /* Bit 4: Control Register Read */
#define RTC_RAR_SRR (1 << 5) /* Bit 5: Status Register Read */ #define RTC_RAR_SRR (1 << 5) /* Bit 5: Status Register Read */
#define RTC_RAR_LRR (1 << 6) /* Bit 6: Lock Register Read */ #define RTC_RAR_LRR (1 << 6) /* Bit 6: Lock Register Read */
#if defined(KINETIS_K40) || defined(KINETIS_K64) #define RTC_RAR_IERR (1 << 7) /* Bit 7: Interrupt Enable Register Read */
# define RTC_RAR_IERR (1 << 7) /* Bit 7: Interrupt Enable Register Read */
#endif
#ifdef KINETIS_K60 #ifdef KINETIS_K60
/* This is possibly an old name, from K60P100M100SF2V2RM bit 7 would be called
* RTC_RAR_IERR.
*/
# define RTC_RAR_CCRR (1 << 7) /* Bit 7: Chip Config Register Read */ # define RTC_RAR_CCRR (1 << 7) /* Bit 7: Chip Config Register Read */
#endif #endif
/* Bits 8-31: Reserved */
#ifdef KINETIS_RTC_GEN2
# define RTC_RAR_TTSR (1 << 8) /* Bit 8: Tamper Time Seconds Read */
# define RTC_RAR_MERR (1 << 9) /* Bit 9: Monotonic Enable Read */
# define RTC_RAR_MCLR (1 << 10) /* Bit 10: Monotoic Counter Low Register Read */
# define RTC_RAR_MCHR (1 << 11) /* Bit 10: Monotoic Counter High Register Read */
#endif
/* Bits 11-31: Reserved */
#if defined(KINETIS_RTC_GEN2)/* && defined(CONFIG_RTC_MAGIC) */
# define CONFIG_RTC_MAGICL 0xfacefee0
# define CONFIG_RTC_MAGICH 0xef32a141
#endif
/************************************************************************************ /************************************************************************************
* Public Types * Public Types
arch/arm/src/kinetis/kinetis_alarm.h
+53 -2
View File
@@ -1,7 +1,7 @@
/**************************************************************************** /****************************************************************************
* arch/arm/src/kinetis/kinetis_alarm.h * arch/arm/src/kinetis/kinetis_alarm.h
* *
* Copyright (C) 2016 Gregory Nutt. All rights reserved. * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
* Author: Matias v01d <phreakuencies@gmail.com> * Author: Matias v01d <phreakuencies@gmail.com>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@@ -56,6 +56,34 @@
typedef CODE void (*alarmcb_t)(void); typedef CODE void (*alarmcb_t)(void);
/* These features are in KinetisK 1st generation
* Time Alarm Interrupt
* Time Overflow Interrupt
* Time Seconds Interrupt
*
* For KinetisK 2nd Generation devices
* 64bit Monotonic register.
*/
enum alm_id_e
{
/* Used for indexing - must be sequential */
RTC_ALARMA = 0, /* RTC ALARM A */
RTC_ALARMM, /* FUT: RTC Monotonic */
RTC_ALARM_LAST
};
/* Structure used to pass parmaters to set an alarm */
struct alm_setalarm_s
{
int as_id; /* enum alm_id_e */
struct tm as_time; /* Alarm expiration time */
alarmcb_t as_cb; /* Callback (if non-NULL) */
FAR void *as_arg; /* Argument for callback */
};
/**************************************************************************** /****************************************************************************
* Public Functions * Public Functions
****************************************************************************/ ****************************************************************************/
@@ -84,7 +112,6 @@ extern "C"
* *
****************************************************************************/ ****************************************************************************/
struct timespec;
int kinetis_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback); int kinetis_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback);
/**************************************************************************** /****************************************************************************
@@ -103,6 +130,30 @@ int kinetis_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback);
int kinetis_rtc_cancelalarm(void); int kinetis_rtc_cancelalarm(void);
/****************************************************************************
* Name: kinetis_rtc_lowerhalf
*
* Description:
* Instantiate the RTC lower half driver for the Kinetis. General usage:
*
* #include <nuttx/timers/rtc.h>
* #include "kinetis_rtc.h>
*
* struct rtc_lowerhalf_s *lower;
* lower = kinetis_rtc_lowerhalf();
* rtc_initialize(0, lower);
*
* Input Parameters:
* None
*
* Returned Value:
* On success, a non-NULL RTC lower interface is returned.
* NULL is returned on any failure.
*
****************************************************************************/
FAR struct rtc_lowerhalf_s *kinetis_rtc_lowerhalf(void);
#undef EXTERN #undef EXTERN
#if defined(__cplusplus) #if defined(__cplusplus)
} }
arch/arm/src/kinetis/kinetis_rtc.c
+231 -17
View File
@@ -60,12 +60,23 @@
#if defined(CONFIG_RTC) #if defined(CONFIG_RTC)
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if !defined(BOARD_RTC_CAP)
/* Capacitance values 8pF if not already defined */
# define BOARD_RTC_CAP RTC_CR_SC8P | RTC_CR_SC4P
#endif
/**************************************************************************** /****************************************************************************
* Private Data * Private Data
****************************************************************************/ ****************************************************************************/
#ifdef CONFIG_RTC_ALARM #ifdef CONFIG_RTC_ALARM
static alarmcb_t g_alarmcb; static alarmcb_t g_alarmcb;
static bool rtc_irq_state = false;
#endif #endif
/**************************************************************************** /****************************************************************************
@@ -78,6 +89,73 @@ volatile bool g_rtc_enabled = false;
* Private Functions * Private Functions
****************************************************************************/ ****************************************************************************/
/****************************************************************************
* Name: rtc_dumpregs
*
* Description:
* Disable RTC write protection
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_DEBUG_RTC_INFO
static void rtc_dumpregs(FAR const char *msg)
{
rtcinfo("%s:\n", msg);
rtcinfo(" TSR: %08x\n", getreg32(KINETIS_RTC_TSR));
rtcinfo(" TPR: %08x\n", getreg32(KINETIS_RTC_TPR));
rtcinfo(" TAR: %08x\n", getreg32(KINETIS_RTC_TAR));
rtcinfo(" CR: %08x\n", getreg32(KINETIS_RTC_CR));
rtcinfo(" SR: %08x\n", getreg32(KINETIS_RTC_SR));
rtcinfo(" LR: %08x\n", getreg32(KINETIS_RTC_LR));
rtcinfo(" IER: %08x\n", getreg32(KINETIS_RTC_IER));
#if defined(KINETIS_RTC_GEN2)
rtcinfo(" TTSR: %08x\n", getreg32(KINETIS_RTC_TTSR));
rtcinfo(" MER: %08x\n", getreg32(KINETIS_RTC_MER));
rtcinfo(" MCLR: %08x\n", getreg32(KINETIS_RTC_MCLR));
rtcinfo(" MCHR: %08x\n", getreg32(KINETIS_RTC_MCHR));
rtcinfo(" WAR: %08x\n", getreg32(KINETIS_RTC_WAR));
rtcinfo(" RAR: %08x\n", getreg32(KINETIS_RTC_RAR));
#endif
}
#else
# define rtc_dumpregs(msg)
#endif
/****************************************************************************
* Name: rtc_dumptime
*
* Description:
* Disable RTC write protection
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_DEBUG_RTC_INFO
static void rtc_dumptime(FAR struct tm *tp, FAR const char *msg)
{
rtcinfo("%s:\n", msg);
rtcinfo(" tm_sec: %08x\n", tp->tm_sec);
rtcinfo(" tm_min: %08x\n", tp->tm_min);
rtcinfo(" tm_hour: %08x\n", tp->tm_hour);
rtcinfo(" tm_mday: %08x\n", tp->tm_mday);
rtcinfo(" tm_mon: %08x\n", tp->tm_mon);
rtcinfo(" tm_year: %08x\n", tp->tm_year);
}
#else
# define rtc_dumptime(tp, msg)
#endif
/**************************************************************************** /****************************************************************************
* Name: kinetis_rtc_interrupt * Name: kinetis_rtc_interrupt
* *
@@ -96,6 +174,12 @@ volatile bool g_rtc_enabled = false;
#if defined(CONFIG_RTC_ALARM) #if defined(CONFIG_RTC_ALARM)
static int kinetis_rtc_interrupt(int irq, void *context) static int kinetis_rtc_interrupt(int irq, void *context)
{ {
uint16_t rtc_sr;
/* if alarm */
rtc_sr = getreg32( KINETIS_RTC_SR);
if (rtc_sr & RTC_SR_TAF )
{
if (g_alarmcb != NULL) if (g_alarmcb != NULL)
{ {
/* Alarm callback */ /* Alarm callback */
@@ -103,20 +187,106 @@ static int kinetis_rtc_interrupt(int irq, void *context)
g_alarmcb(); g_alarmcb();
g_alarmcb = NULL; g_alarmcb = NULL;
} }
}
else
{
/* other interrupts are serious and should leave a turd
*
* RTC_SR_TIF _TOF _MOF
*/
rtcwarn("unexp int src=0x%x, num=", rtc_sr);
}
/* Clear pending flags, disable alarm */ /* Clear pending flags, disable alarm */
putreg32(0, KINETIS_RTC_TAR); /* unset alarm (resets flags) */ putreg32(0, KINETIS_RTC_TAR); /* Unset alarm (resets flags) */
putreg32(0, KINETIS_RTC_IER); /* disable alarm interrupt */ putreg32(0, KINETIS_RTC_IER); /* Disable alarm interrupt */
return 0; return 0;
} }
#endif #endif
/****************************************************************************
* Name: RTC_Reset
*
* Description:
* Reset the RTC to known state
*
* Input Parameters:
* none
*
* Returned Value:
* none
*
****************************************************************************/
static inline void RTC_Reset(void)
{
putreg32(( RTC_CR_SWR | getreg32(KINETIS_RTC_CR)),KINETIS_RTC_CR);
putreg32((~RTC_CR_SWR & getreg32(KINETIS_RTC_CR)),KINETIS_RTC_CR);
/* Set TSR register to 0x1 to avoid the timer invalid (TIF) bit being
* set in the SR register
*/
putreg32(1,KINETIS_RTC_TSR);
}
/**************************************************************************** /****************************************************************************
* Public Functions * Public Functions
****************************************************************************/ ****************************************************************************/
/****************************************************************************
* Name: up_rtc_irqinit
*
* Description:
* Initialize the hardware RTC irq.
* This only needs to be called once when first used.
*
* Input Parameters:
* None
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
#if defined(CONFIG_RTC_ALARM)
int up_rtc_irq_attach(void)
{
uint32_t rtc_sr;
if (!rtc_irq_state)
{
rtc_irq_state=true;
/* Clear TAF if pending */
rtc_sr = getreg32( KINETIS_RTC_SR);
if (rtc_sr & RTC_SR_TAF )
{
putreg32(0, KINETIS_RTC_TAR);
}
/* Enable alarm interrupts.
* This will not work if part of up_rtc_initialize()
* as it is called very early in initialization BEFORE the interrupt
* system will be enabled. All interrupts will disabled later when
* the interrupt system is disabled. This must be done later when the
* alarm is first set.
*
* KINETIS_IRQ_RTCS is a separate interrupt for seconds if needed
*/
irq_attach(KINETIS_IRQ_RTC, kinetis_rtc_interrupt);
up_enable_irq(KINETIS_IRQ_RTC);
}
return OK;
}
#endif
/**************************************************************************** /****************************************************************************
* Name: up_rtc_initialize * Name: up_rtc_initialize
* *
@@ -134,7 +304,8 @@ static int kinetis_rtc_interrupt(int irq, void *context)
int up_rtc_initialize(void) int up_rtc_initialize(void)
{ {
int regval; uint32_t regval;
bool rtc_valid = false;
/* Enable RTC module */ /* Enable RTC module */
@@ -142,16 +313,64 @@ int up_rtc_initialize(void)
regval |= SIM_SCGC6_RTC; regval |= SIM_SCGC6_RTC;
putreg32(regval, KINETIS_SIM_SCGC6); putreg32(regval, KINETIS_SIM_SCGC6);
regval = getreg32(KINETIS_RTC_SR);
if (!(regval & RTC_SR_TIF))
{
#ifdef KINETIS_RTC_GEN2
/* Check if the one-time initialization of the RTC has already been
* performed. We can determine this by checking if the magic number
* has been writing to to back-up date register DR0.
*/
regval = getreg32(KINETIS_RTC_MCLR);
if ((CONFIG_RTC_MAGICL == regval ) &&
(CONFIG_RTC_MAGICH == getreg32(KINETIS_RTC_MCHR)) )
#endif
{
rtc_valid = true;
}
}
if (rtc_valid)
{
rtcinfo("Do resume\n");
/* RTC already set-up, just resume normal operation */
rtc_dumpregs("Did resume");
}
else
{
rtcinfo("Do setup\n");
RTC_Reset();
#ifdef KINETIS_RTC_GEN2
/* Configure the RTC to be initialized */
putreg32(CONFIG_RTC_MAGICL, KINETIS_RTC_MCLR);
putreg32(CONFIG_RTC_MAGICH, KINETIS_RTC_MCHR);
#endif
/* Setup the update mode and supervisor access mode */
putreg32((~(RTC_CR_UM|RTC_CR_SUP) & getreg32(KINETIS_RTC_CR)),
KINETIS_RTC_CR);
/* Disable counters (just in case) */ /* Disable counters (just in case) */
putreg32(0, KINETIS_RTC_SR); putreg32(0, KINETIS_RTC_SR);
/* Enable oscilator */ /* Enable oscilator - must have Vbat else hard fault */
/* capacitance values from teensyduino */
putreg32(RTC_CR_SC16P | RTC_CR_SC4P | RTC_CR_OSCE, KINETIS_RTC_CR); putreg32((BOARD_RTC_CAP | RTC_CR_OSCE ), KINETIS_RTC_CR);
/* TODO - add capability to accurately tune RTC
* This is a per individual board customization and requires
* parameters to be configurable and stored in non-volatile eg flash.
*/
/* TODO: delay some time (1024 cycles? would be 30ms) */ /* TODO: delay some time (1024 cycles? would be 30ms) */
}
/* Disable interrupts */ /* Disable interrupts */
@@ -163,17 +382,6 @@ int up_rtc_initialize(void)
putreg32(getreg32(KINETIS_RTC_TSR), KINETIS_RTC_TSR); putreg32(getreg32(KINETIS_RTC_TSR), KINETIS_RTC_TSR);
#if defined(CONFIG_RTC_ALARM)
/* Enable alarm interrupts. REVISIT: This will not work. up_rtc_initialize()
* is called very early in initialization BEFORE the interrupt system will be
* enabled. All interrupts will disabled later when the interrupt system is
* disabled. This must be done later when the alarm is first set.
*/
irq_attach(KINETIS_IRQ_RTC, kinetis_rtc_interrupt);
up_enable_irq(KINETIS_IRQ_RTC);
#endif
/* Enable counters */ /* Enable counters */
putreg32(RTC_SR_TCE, KINETIS_RTC_SR); putreg32(RTC_SR_TCE, KINETIS_RTC_SR);
@@ -319,12 +527,18 @@ int kinetis_rtc_setalarm(FAR const struct timespec *tp, alarmcb_t callback)
g_alarmcb = callback; g_alarmcb = callback;
/* ensure irq is attached */
up_rtc_irq_attach();
/* Enable and set RTC alarm */ /* Enable and set RTC alarm */
putreg32(tp->tv_sec, KINETIS_RTC_TAR); /* Set alarm (also resets putreg32(tp->tv_sec, KINETIS_RTC_TAR); /* Set alarm (also resets
* flags) */ * flags) */
putreg32(RTC_IER_TAIE, KINETIS_RTC_IER); /* Enable alarm interrupt */ putreg32(RTC_IER_TAIE, KINETIS_RTC_IER); /* Enable alarm interrupt */
rtc_dumpregs("set alarmtime");
return OK; return OK;
} }
else else
arch/arm/src/kinetis/kinetis_rtc_if.h
+150
View File
@@ -0,0 +1,150 @@
/****************************************************************************
* arch/arm/src/kinetis/kinetis_rtc_if.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Neil Hancock
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_RTC_IF_H
#define __ARCH_ARM_SRC_KINETIS_KINETIS_RTC_IF_H
#include <nuttx/config.h>
#include "chip.h"
/* Kinetis parts all have a simple battery-backed 32bit counter for its RTC
* KINETIS_RTC_GEN2 have
* a Tamper Time seconds - 32bibt
* a MONOTONC seconds which is used is 2*32bit registers
*
*/
#include "kinetis_alarm.h"
/****************************************************************************
* Public Functions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: KINETIS_rtc_getdatetime_with_subseconds
*
* Description:
* Get the current date and time from the date/time RTC. This interface
* is only supported by the date/time RTC hardware implementation.
* It is used to replace the system timer. It is only used by the RTOS
* during initialization to set up the system time when CONFIG_RTC and
* CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not).
*
* NOTE: Some date/time RTC hardware is capability of sub-second accuracy.
* Thatsub-second accuracy is returned through 'nsec'.
*
* Input Parameters:
* tp - The location to return the high resolution time value.
* nsec - The location to return the subsecond time value.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_KINETIS_HAVE_RTC_SUBSECONDS
int KINETIS_rtc_getdatetime_with_subseconds(FAR struct tm *tp, FAR long *nsec);
#endif
/****************************************************************************
* Name: KINETIS_rtc_setdatetime
*
* Description:
* Set the RTC to the provided time. RTC implementations which provide
* up_rtc_getdatetime() (CONFIG_RTC_DATETIME is selected) should provide
* this function.
*
* Input Parameters:
* tp - the time to use
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_RTC_DATETIME
struct tm;
int kinetis_rtc_setdatetime(FAR const struct tm *tp);
#endif
/****************************************************************************
* Name: KINETIS_rtc_lowerhalf
*
* Description:
* Instantiate the RTC lower half driver for the KINETIS. General usage:
*
* #include <nuttx/timers/rtc.h>
* #include "KINETIS_rtc.h>
*
* struct rtc_lowerhalf_s *lower;
* lower = KINETIS_rtc_lowerhalf();
* rtc_initialize(0, lower);
*
* Input Parameters:
* None
*
* Returned Value:
* On success, a non-NULL RTC lower interface is returned. NULL is
* returned on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_DRIVER
FAR struct rtc_lowerhalf_s *kinetis_rtc_lowerhalf(void);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_RTC_IF_H */
arch/arm/src/kinetis/kinetis_rtc_lowerhalf.c
+525
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/kl/Make.defs
-6
View File
@@ -59,12 +59,6 @@ ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c CMN_CSRCS += up_checkstack.c
endif endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c
endif
ifeq ($(CONFIG_DEBUG_FEATURES),y) ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += up_dumpnvic.c CMN_CSRCS += up_dumpnvic.c
endif endif
arch/arm/src/lpc11xx/Make.defs
-6
View File
@@ -59,12 +59,6 @@ ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c CMN_CSRCS += up_checkstack.c
endif endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c
endif
ifeq ($(CONFIG_DEBUG_FEATURES),y) ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += up_dumpnvic.c CMN_CSRCS += up_dumpnvic.c
endif endif
arch/arm/src/lpc17xx/Make.defs
-10
View File
@@ -70,10 +70,6 @@ ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
endif endif
ifeq ($(CONFIG_ARCH_MEMCPY),y)
CMN_ASRCS += up_memcpy.S
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y) ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
ifneq ($(CONFIG_DISABLE_SIGNALS),y) ifneq ($(CONFIG_DISABLE_SIGNALS),y)
@@ -92,12 +88,6 @@ CMN_CSRCS += up_etherstub.c
endif endif
endif endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c
endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y) ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
arch/arm/src/lpc214x/Make.defs
-6
View File
@@ -50,12 +50,6 @@ ifneq ($(CONFIG_DISABLE_SIGNALS),y)
CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c
endif endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y) ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c CMN_CSRCS += up_checkstack.c
endif endif
arch/arm/src/lpc2378/Make.defs
-6
View File
@@ -54,12 +54,6 @@ ifneq ($(CONFIG_DISABLE_SIGNALS),y)
CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c
endif endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y) ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c CMN_CSRCS += up_checkstack.c
endif endif
arch/arm/src/lpc31xx/Make.defs
-6
View File
@@ -51,12 +51,6 @@ ifeq ($(CONFIG_PAGING),y)
CMN_CSRCS += up_pginitialize.c up_checkmapping.c up_allocpage.c up_va2pte.c CMN_CSRCS += up_pginitialize.c up_checkmapping.c up_allocpage.c up_va2pte.c
endif endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c
endif
ifeq ($(CONFIG_STACK_COLORATION),y) ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c CMN_CSRCS += up_checkstack.c
endif endif
arch/arm/src/lpc43xx/Make.defs
-10
View File
@@ -60,10 +60,6 @@ ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
endif endif
ifeq ($(CONFIG_ARCH_MEMCPY),y)
CMN_ASRCS += up_memcpy.S
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y) ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
ifneq ($(CONFIG_DISABLE_SIGNALS),y) ifneq ($(CONFIG_DISABLE_SIGNALS),y)
@@ -76,12 +72,6 @@ ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c CMN_CSRCS += up_checkstack.c
endif endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c
endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y) ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
arch/arm/src/moxart/Make.defs
-6
View File
@@ -48,12 +48,6 @@ CMN_CSRCS += up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c
CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_syscall.c up_unblocktask.c CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_syscall.c up_unblocktask.c
CMN_CSRCS += up_undefinedinsn.c up_usestack.c up_vfork.c up_etherstub.c CMN_CSRCS += up_undefinedinsn.c up_usestack.c up_vfork.c up_etherstub.c
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c
endif
CHIP_ASRCS = moxart_lowputc.S CHIP_ASRCS = moxart_lowputc.S
CHIP_CSRCS = moxart_16550.c moxart_irq.c moxart_timer.c moxart_idle.c CHIP_CSRCS = moxart_16550.c moxart_irq.c moxart_timer.c moxart_idle.c
arch/arm/src/nuc1xx/Make.defs
-6
View File
@@ -59,12 +59,6 @@ ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c CMN_CSRCS += up_checkstack.c
endif endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c
endif
ifeq ($(CONFIG_DEBUG_FEATURES),y) ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += up_dumpnvic.c CMN_CSRCS += up_dumpnvic.c
endif endif
arch/arm/src/sam34/Kconfig
+5
View File
@@ -193,6 +193,11 @@ config ARCH_CHIP_ATSAM4S8B
select ARCH_CORTEXM4 select ARCH_CORTEXM4
select ARCH_CHIP_SAM4S select ARCH_CHIP_SAM4S
config ARCH_CHIP_ATSAM4S4C
bool "ATSAM4S4C"
select ARCH_CORTEXM4
select ARCH_CHIP_SAM4S
config ARCH_CHIP_ATSAM4E16E config ARCH_CHIP_ATSAM4E16E
bool "ATSAM4E16E" bool "ATSAM4E16E"
select ARCH_CORTEXM4 select ARCH_CORTEXM4
arch/arm/src/sam34/Make.defs
-10
View File
@@ -76,10 +76,6 @@ ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
endif endif
ifeq ($(CONFIG_ARCH_MEMCPY),y)
CMN_ASRCS += up_memcpy.S
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y) ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
ifneq ($(CONFIG_DISABLE_SIGNALS),y) ifneq ($(CONFIG_DISABLE_SIGNALS),y)
@@ -88,12 +84,6 @@ CMN_UASRCS += up_signal_handler.S
endif endif
endif endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c
endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y) ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
arch/arm/src/sam34/sam4cm_cpupause.c
+31 -8
View File
@@ -47,6 +47,7 @@
#include <nuttx/arch.h> #include <nuttx/arch.h>
#include <nuttx/spinlock.h> #include <nuttx/spinlock.h>
#include <nuttx/sched_note.h>
#include "up_arch.h" #include "up_arch.h"
#include "sched/sched.h" #include "sched/sched.h"
@@ -145,6 +146,12 @@ int up_cpu_paused(int cpu)
sched_suspend_scheduler(tcb); sched_suspend_scheduler(tcb);
#ifdef CONFIG_SCHED_INSTRUMENTATION
/* Notify that we are paused */
sched_note_cpu_paused(tcb);
#endif
/* Save the current context at CURRENT_REGS into the TCB at the head /* Save the current context at CURRENT_REGS into the TCB at the head
* of the assigned task list for this CPU. * of the assigned task list for this CPU.
*/ */
@@ -162,6 +169,12 @@ int up_cpu_paused(int cpu)
tcb = this_task(); tcb = this_task();
#ifdef CONFIG_SCHED_INSTRUMENTATION
/* Notify that we have resumed */
sched_note_cpu_resumed(tcb);
#endif
/* Reset scheduler parameters */ /* Reset scheduler parameters */
sched_resume_scheduler(tcb); sched_resume_scheduler(tcb);
@@ -247,18 +260,24 @@ int up_cpu_pause(int cpu)
DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu()); DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());
/* Take the both spinlocks. The g_cpu_wait spinlock will prevent the SGI2 #ifdef CONFIG_SCHED_INSTRUMENTATION
/* Notify of the pause event */
sched_note_cpu_pause(this_task(), cpu);
#endif
/* Take the both spinlocks. The g_cpu_wait spinlock will prevent the interrupt
* handler from returning until up_cpu_resume() is called; g_cpu_paused * handler from returning until up_cpu_resume() is called; g_cpu_paused
* is a handshake that will prefent this function from returning until * is a handshake that will prefent this function from returning until
* the CPU is actually paused. * the CPU is actually paused.
*/ */
DEBUGASSERT(!spin_islocked(&g_cpu_wait[cpu]) &&
!spin_islocked(&g_cpu_paused[cpu]));
spin_lock(&g_cpu_wait[cpu]); spin_lock(&g_cpu_wait[cpu]);
spin_lock(&g_cpu_paused[cpu]); spin_lock(&g_cpu_paused[cpu]);
DEBUGASSERT(spin_islocked(&g_cpu_wait[cpu]) &&
spin_islocked(&g_cpu_paused[cpu]));
/* Execute Pause IRQ to CPU(cpu) */ /* Execute Pause IRQ to CPU(cpu) */
/* Set IPC Interrupt (IRQ0) (write-only) */ /* Set IPC Interrupt (IRQ0) (write-only) */
@@ -276,7 +295,6 @@ int up_cpu_pause(int cpu)
*/ */
spin_lock(&g_cpu_paused[cpu]); spin_lock(&g_cpu_paused[cpu]);
spin_unlock(&g_cpu_paused[cpu]); spin_unlock(&g_cpu_paused[cpu]);
/* On successful return g_cpu_wait will be locked, the other CPU will be /* On successful return g_cpu_wait will be locked, the other CPU will be
@@ -284,7 +302,7 @@ int up_cpu_pause(int cpu)
* called. g_cpu_paused will be unlocked in any case. * called. g_cpu_paused will be unlocked in any case.
*/ */
return 0; return OK;
} }
/**************************************************************************** /****************************************************************************
@@ -312,6 +330,12 @@ int up_cpu_resume(int cpu)
DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu()); DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());
#ifdef CONFIG_SCHED_INSTRUMENTATION
/* Notify of the resume event */
sched_note_cpu_resume(this_task(), cpu);
#endif
/* Release the spinlock. Releasing the spinlock will cause the SGI2 /* Release the spinlock. Releasing the spinlock will cause the SGI2
* handler on 'cpu' to continue and return from interrupt to the newly * handler on 'cpu' to continue and return from interrupt to the newly
* established thread. * established thread.
@@ -321,8 +345,7 @@ int up_cpu_resume(int cpu)
!spin_islocked(&g_cpu_paused[cpu])); !spin_islocked(&g_cpu_paused[cpu]));
spin_unlock(&g_cpu_wait[cpu]); spin_unlock(&g_cpu_wait[cpu]);
return OK;
return 0;
} }
#endif /* CONFIG_SMP */ #endif /* CONFIG_SMP */
arch/arm/src/sama5/Make.defs
+2 -6
View File
@@ -61,10 +61,6 @@ CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.
# Configuration dependent assembly language files # Configuration dependent assembly language files
ifeq ($(CONFIG_ARCH_MEMCPY),y)
CMN_ASRCS += arm_memcpy.S
endif
# Common C source files # Common C source files
CMN_CSRCS = up_initialize.c up_idle.c up_interruptcontext.c up_exit.c CMN_CSRCS = up_initialize.c up_idle.c up_interruptcontext.c up_exit.c
@@ -114,9 +110,9 @@ endif
endif endif
ifeq ($(CONFIG_ELF),y) ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += arm_elf.c arm_coherent_dcache.c CMN_CSRCS += arm_coherent_dcache.c
else ifeq ($(CONFIG_MODULE),y) else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += arm_elf.c arm_coherent_dcache.c CMN_CSRCS += arm_coherent_dcache.c
endif endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
arch/arm/src/samdl/Make.defs
-6
View File
@@ -59,12 +59,6 @@ ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c CMN_CSRCS += up_checkstack.c
endif endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c
endif
ifeq ($(CONFIG_DEBUG_FEATURES),y) ifeq ($(CONFIG_DEBUG_FEATURES),y)
CMN_CSRCS += up_dumpnvic.c CMN_CSRCS += up_dumpnvic.c
endif endif
arch/arm/src/samv7/Make.defs
+2 -6
View File
@@ -90,10 +90,6 @@ ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
endif endif
ifeq ($(CONFIG_ARCH_MEMCPY),y)
CMN_ASRCS += up_memcpy.S
endif
ifeq ($(CONFIG_ARM_MPU),y) ifeq ($(CONFIG_ARM_MPU),y)
CMN_CSRCS += up_mpu.c CMN_CSRCS += up_mpu.c
ifeq ($(CONFIG_BUILD_PROTECTED),y) ifeq ($(CONFIG_BUILD_PROTECTED),y)
@@ -106,9 +102,9 @@ endif
endif endif
ifeq ($(CONFIG_ELF),y) ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c up_coherent_dcache.c CMN_CSRCS += up_coherent_dcache.c
else ifeq ($(CONFIG_MODULE),y) else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c up_coherent_dcache.c CMN_CSRCS += up_coherent_dcache.c
endif endif
ifeq ($(CONFIG_STACK_COLORATION),y) ifeq ($(CONFIG_STACK_COLORATION),y)
arch/arm/src/stm32/Kconfig
+26 -15
View File
@@ -2624,6 +2624,24 @@ config STM32_FREERUN
bool bool
default y default y
config STM32_TICKLESS_ONESHOT
int "Tickless one-shot timer channel"
default 2
range 1 14
depends on STM32_ONESHOT
---help---
If the Tickless OS feature is enabled, the one clock must be
assigned to provided the one-shot timer needed by the OS.
config STM32_TICKLESS_FREERUN
int "Tickless free-running timer channel"
default 5
range 1 14
depends on STM32_FREERUN
---help---
If the Tickless OS feature is enabled, the one clock must be
assigned to provided the free-running timer needed by the OS.
endif # SCHED_TICKLESS endif # SCHED_TICKLESS
if !SCHED_TICKLESS if !SCHED_TICKLESS
@@ -2644,23 +2662,16 @@ config STM32_FREERUN
endif # !SCHED_TICKLESS endif # !SCHED_TICKLESS
config STM32_TICKLESS_ONESHOT config STM32_ONESHOT_MAXTIMERS
int "Tickless one-shot timer channel" int "Maximum number of oneshot timers"
default 2 default 1
range 1 14 range 1 8
depends on STM32_ONESHOT depends on STM32_ONESHOT
---help--- ---help---
If the Tickless OS feature is enabled, the one clock must be Determines the maximum number of oneshot timers that can be
assigned to provided the one-shot timer needed by the OS. supported. This setting pre-allocates some minimal support for each
of the timers and places an upper limit on the number of oneshot
config STM32_TICKLESS_FREERUN timers that you can use.
int "Tickless free-running timer channel"
default 5
range 1 14
depends on STM32_FREERUN
---help---
If the Tickless OS feature is enabled, the one clock must be
assigned to provided the free-running timer needed by the OS.
config STM32_TIM1_PWM config STM32_TIM1_PWM
bool "TIM1 PWM" bool "TIM1 PWM"
arch/arm/src/stm32/Make.defs
-10
View File
@@ -71,10 +71,6 @@ ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
endif endif
ifeq ($(CONFIG_ARCH_MEMCPY),y)
CMN_ASRCS += up_memcpy.S
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y) ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
ifneq ($(CONFIG_DISABLE_SIGNALS),y) ifneq ($(CONFIG_DISABLE_SIGNALS),y)
@@ -87,12 +83,6 @@ ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c CMN_CSRCS += up_checkstack.c
endif endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c
endif
ifeq ($(CONFIG_ARCH_FPU),y) ifeq ($(CONFIG_ARCH_FPU),y)
CMN_ASRCS += up_fpu.S CMN_ASRCS += up_fpu.S
ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y) ifneq ($(CONFIG_ARMV7M_CMNVECTOR),y)
arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h
+1
View File
@@ -93,6 +93,7 @@
#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */ #define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */
#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */ #define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */ #define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */
#define STM32_BKP_BASE 0x40002850 /* 0x40002850-0x4000288c BKP */
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */ #define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */ #define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */
#define STM32_I2S2EXT_BASE 0x40003400 /* 0x40003400-0x400037ff I2S2ext */ #define STM32_I2S2EXT_BASE 0x40003400 /* 0x40003400-0x400037ff I2S2ext */
arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h
+1
View File
@@ -94,6 +94,7 @@
#define STM32_TIM13_BASE 0x40001c00 /* 0x40001c00-0x40001fff TIM13 */ #define STM32_TIM13_BASE 0x40001c00 /* 0x40001c00-0x40001fff TIM13 */
#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff TIM14 */ #define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff TIM14 */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */ #define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */
#define STM32_BKP_BASE 0x40002850 /* 0x40002850-0x400028cc BKP */
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */ #define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */ #define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */
#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff SPI2, or */ #define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff SPI2, or */
arch/arm/src/stm32/stm32_oneshot.c
+205 -18
View File
@@ -42,6 +42,7 @@
#include <sys/types.h> #include <sys/types.h>
#include <stdint.h> #include <stdint.h>
#include <stdbool.h> #include <stdbool.h>
#include <sched.h>
#include <assert.h> #include <assert.h>
#include <errno.h> #include <errno.h>
#include <debug.h> #include <debug.h>
@@ -54,10 +55,66 @@
#ifdef CONFIG_STM32_ONESHOT #ifdef CONFIG_STM32_ONESHOT
/**************************************************************************** /****************************************************************************
* Private Date * Private Function Prototypes
****************************************************************************/ ****************************************************************************/
static struct stm32_oneshot_s *g_oneshot; static int stm32_oneshot_handler(struct stm32_oneshot_s *oneshot);
static int stm32_oneshot1_handler(int irq, void *context);
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1
static int stm32_oneshot2_handler(int irq, void *context);
#endif
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 2
static int stm32_oneshot3_handler(int irq, void *context);
#endif
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 3
static int stm32_oneshot4_handler(int irq, void *context);
#endif
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 4
static int stm32_oneshot5_handler(int irq, void *context);
#endif
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 5
static int stm32_oneshot6_handler(int irq, void *context);
#endif
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 6
static int stm32_oneshot7_handler(int irq, void *context);
#endif
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 7
static int stm32_oneshot8_handler(int irq, void *context);
#endif
/****************************************************************************
* Private Data
****************************************************************************/
static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS];
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1
static const xcpt_t g_callbacks[CONFIG_STM32_ONESHOT_MAXTIMERS] =
{
stm32_oneshot1_handler,
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1
stm32_oneshot2_handler,
#endif
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 2
stm32_oneshot3_handler,
#endif
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 3
stm32_oneshot4_handler,
#endif
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 4
stm32_oneshot5_handler,
#endif
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 5
stm32_oneshot6_handler,
#endif
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 6
stm32_oneshot7_handler,
#endif
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 7
stm32_oneshot8_handler,
#endif
};
#endif
/**************************************************************************** /****************************************************************************
* Private Functions * Private Functions
@@ -67,24 +124,20 @@ static struct stm32_oneshot_s *g_oneshot;
* Name: stm32_oneshot_handler * Name: stm32_oneshot_handler
* *
* Description: * Description:
* Timer interrupt callback. When the oneshot timer interrupt expires, * Common timer interrupt callback. When any oneshot timer interrupt
* this function will be called. It will forward the call to the next * expires, this function will be called. It will forward the call to
* level up. * the next level up.
* *
* Input Parameters: * Input Parameters:
* tch - The handle that represents the timer state * oneshot - The state associated with the expired timer
* arg - An opaque argument provided when the interrupt was registered
* sr - The value of the timer interrupt status register at the time
* that the interrupt occurred.
* *
* Returned Value: * Returned Value:
* None * Always returns OK
* *
****************************************************************************/ ****************************************************************************/
static int stm32_oneshot_handler(int irq, void *context) static int stm32_oneshot_handler(struct stm32_oneshot_s *oneshot)
{ {
struct stm32_oneshot_s *oneshot = g_oneshot;
oneshot_handler_t oneshot_handler; oneshot_handler_t oneshot_handler;
void *oneshot_arg; void *oneshot_arg;
@@ -115,6 +168,137 @@ static int stm32_oneshot_handler(int irq, void *context)
return OK; return OK;
} }
/****************************************************************************
* Name: stm32_oneshot[N]_handler
*
* Description:
* Timer interrupt callbacks. When a oneshot timer interrupt expires,
* one of these functions will be called. These functions will forward
* the call to the nextlevel up.
*
* Input Parameters:
* Standard interrupt handler arguments.
*
* Returned Value:
* Always returns OK
*
****************************************************************************/
static int stm32_oneshot1_handler(int irq, void *context)
{
DEBUGASSERT(g_oneshot[0] != NULL);
return stm32_oneshot_handler(g_oneshot[0]);
}
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1
static int stm32_oneshot2_handler(int irq, void *context)
{
DEBUGASSERT(g_oneshot[1] != NULL);
return stm32_oneshot_handler(g_oneshot[1]);
}
#endif
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 2
static int stm32_oneshot3_handler(int irq, void *context)
{
DEBUGASSERT(g_oneshot[2] != NULL);
return stm32_oneshot_handler(g_oneshot[2]);
}
#endif
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 3
static int stm32_oneshot4_handler(int irq, void *context)
{
DEBUGASSERT(g_oneshot[3] != NULL);
return stm32_oneshot_handler(g_oneshot[3]);
}
#endif
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 4
static int stm32_oneshot5_handler(int irq, void *context)
{
DEBUGASSERT(g_oneshot[4] != NULL);
return stm32_oneshot_handler(g_oneshot[4]);
}
#endif
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 5
static int stm32_oneshot6_handler(int irq, void *context)
{
DEBUGASSERT(g_oneshot[6] != NULL);
return stm32_oneshot_handler(g_oneshot[5]);
}
#endif
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 6
static int stm32_oneshot7_handler(int irq, void *context)
{
DEBUGASSERT(g_oneshot[7] != NULL);
return stm32_oneshot_handler(g_oneshot[6]);
}
#endif
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 7
static int stm32_oneshot8_handler(int irq, void *context)
{
DEBUGASSERT(g_oneshot[0] != NULL);
return stm32_oneshot_handler(g_oneshot[7]);
}
#endif
/****************************************************************************
* Name: stm32_allocate_handler
*
* Description:
* Allocate a timer callback handler for the oneshot instance.
*
* Input Parameters:
* oneshot - The state instance the new oneshot timer
*
* Returned Value:
* Returns zero (OK) on success. This can only fail if the number of
* timers exceeds CONFIG_STM32_ONESHOT_MAXTIMERS.
*
****************************************************************************/
static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot)
{
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1
int ret = -EBUSY;
int i;
/* Search for an unused handler */
sched_lock();
for (i = 0; i < CONFIG_STM32_ONESHOT_MAXTIMERS; i++)
{
/* Is this handler available? */
if (g_oneshot[i] == NULL)
{
/* Yes... assign it to this oneshot */
g_oneshot[i] = oneshot;
oneshot->cbndx = i;
ret = OK;
break;
}
}
sched_unlock();
return ret;
#else
if (g_oneshot[0] == NULL)
{
g_oneshot[0] = oneshot;
return OK;
}
return -EBUSY;
#endif
}
/**************************************************************************** /****************************************************************************
* Public Functions * Public Functions
****************************************************************************/ ****************************************************************************/
@@ -160,17 +344,16 @@ int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan,
STM32_TIM_SETCLOCK(oneshot->tch, frequency); STM32_TIM_SETCLOCK(oneshot->tch, frequency);
/* Initialize the remaining fields in the state structure and return /* Initialize the remaining fields in the state structure. */
* success.
*/
oneshot->chan = chan; oneshot->chan = chan;
oneshot->running = false; oneshot->running = false;
oneshot->handler = NULL; oneshot->handler = NULL;
oneshot->arg = NULL; oneshot->arg = NULL;
g_oneshot = oneshot; /* Assign a callback handler to the oneshot */
return OK;
return stm32_allocate_handler(oneshot);
} }
/**************************************************************************** /****************************************************************************
@@ -259,7 +442,11 @@ int stm32_oneshot_start(struct stm32_oneshot_s *oneshot,
/* Set up to receive the callback when the interrupt occurs */ /* Set up to receive the callback when the interrupt occurs */
STM32_TIM_SETISR(oneshot->tch, stm32_oneshot_handler, 0); #if CONFIG_STM32_ONESHOT_MAXTIMERS > 1
STM32_TIM_SETISR(oneshot->tch, g_callbacks[oneshot->cbndx], 0);
#else
STM32_TIM_SETISR(oneshot->tch, stm32_oneshot1_handler, 0);
#endif
/* Set timer period */ /* Set timer period */
arch/arm/src/stm32/stm32_oneshot.h
+21
View File
@@ -45,10 +45,28 @@
#include <stdint.h> #include <stdint.h>
#include <time.h> #include <time.h>
#include <nuttx/irq.h>
#include "stm32_tim.h" #include "stm32_tim.h"
#ifdef CONFIG_STM32_ONESHOT #ifdef CONFIG_STM32_ONESHOT
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \
CONFIG_STM32_ONESHOT_MAXTIMERS < 1
# undef CONFIG_STM32_ONESHOT_MAXTIMERS
# define CONFIG_STM32_ONESHOT_MAXTIMERS 1
#endif
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8
# warning Additional logic required to handle more than 8 timers
# undef CONFIG_STM32_ONESHOT_MAXTIMERS
# define CONFIG_STM32_ONESHOT_MAXTIMERS 8
#endif
/**************************************************************************** /****************************************************************************
* Public Types * Public Types
****************************************************************************/ ****************************************************************************/
@@ -70,6 +88,9 @@ typedef void (*oneshot_handler_t)(void *arg);
struct stm32_oneshot_s struct stm32_oneshot_s
{ {
uint8_t chan; /* The timer/counter in use */ uint8_t chan; /* The timer/counter in use */
#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1
uint8_t cbndx; /* Timer callback handler index */
#endif
volatile bool running; /* True: the timer is running */ volatile bool running; /* True: the timer is running */
FAR struct stm32_tim_dev_s *tch; /* Pointer returned by FAR struct stm32_tim_dev_s *tch; /* Pointer returned by
* stm32_tim_init() */ * stm32_tim_init() */
arch/arm/src/stm32f7/Make.defs
+2 -6
View File
@@ -87,10 +87,6 @@ ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
endif endif
ifeq ($(CONFIG_ARCH_MEMCPY),y)
CMN_ASRCS += up_memcpy.S
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y) ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
ifneq ($(CONFIG_DISABLE_SIGNALS),y) ifneq ($(CONFIG_DISABLE_SIGNALS),y)
@@ -100,9 +96,9 @@ endif
endif endif
ifeq ($(CONFIG_ELF),y) ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c up_coherent_dcache.c CMN_CSRCS += up_coherent_dcache.c
else ifeq ($(CONFIG_MODULE),y) else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c up_coherent_dcache.c CMN_CSRCS += up_coherent_dcache.c
endif endif
ifeq ($(CONFIG_STACK_COLORATION),y) ifeq ($(CONFIG_STACK_COLORATION),y)
arch/arm/src/stm32l4/Kconfig
+25 -14
View File
@@ -659,6 +659,24 @@ config STM32L4_FREERUN
bool bool
default y default y
config STM32L4_TICKLESS_ONESHOT
int "Tickless one-shot timer channel"
default 2
range 1 8
depends on STM32L4_ONESHOT
---help---
If the Tickless OS feature is enabled, then one clock must be
assigned to provide the one-shot timer needed by the OS.
config STM32L4_TICKLESS_FREERUN
int "Tickless free-running timer channel"
default 5
range 1 8
depends on STM32L4_FREERUN
---help---
If the Tickless OS feature is enabled, then one clock must be
assigned to provide the free-running timer needed by the OS.
endif # SCHED_TICKLESS endif # SCHED_TICKLESS
if !SCHED_TICKLESS if !SCHED_TICKLESS
@@ -679,23 +697,16 @@ config STM32L4_FREERUN
endif # !SCHED_TICKLESS endif # !SCHED_TICKLESS
config STM32L4_TICKLESS_ONESHOT config STM32L4_ONESHOT_MAXTIMERS
int "Tickless one-shot timer channel" int "Maximum number of oneshot timers"
default 2 default 1
range 1 8 range 1 8
depends on STM32L4_ONESHOT depends on STM32L4_ONESHOT
---help--- ---help---
If the Tickless OS feature is enabled, then one clock must be Determines the maximum number of oneshot timers that can be
assigned to provide the one-shot timer needed by the OS. supported. This setting pre-allocates some minimal support for each
of the timers and places an upper limit on the number of oneshot
config STM32L4_TICKLESS_FREERUN timers that you can use.
int "Tickless free-running timer channel"
default 5
range 1 8
depends on STM32L4_FREERUN
---help---
If the Tickless OS feature is enabled, then one clock must be
assigned to provide the free-running timer needed by the OS.
config STM32L4_TIM1_PWM config STM32L4_TIM1_PWM
bool "TIM1 PWM" bool "TIM1 PWM"
arch/arm/src/stm32l4/Make.defs
-10
View File
@@ -83,10 +83,6 @@ ifeq ($(CONFIG_ARCH_RAMVECTORS),y)
CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c CMN_CSRCS += up_ramvec_initialize.c up_ramvec_attach.c
endif endif
ifeq ($(CONFIG_ARCH_MEMCPY),y)
CMN_ASRCS += up_memcpy.S
endif
ifeq ($(CONFIG_BUILD_PROTECTED),y) ifeq ($(CONFIG_BUILD_PROTECTED),y)
CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c CMN_CSRCS += up_mpu.c up_task_start.c up_pthread_start.c
ifneq ($(CONFIG_DISABLE_SIGNALS),y) ifneq ($(CONFIG_DISABLE_SIGNALS),y)
@@ -99,12 +95,6 @@ ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c CMN_CSRCS += up_checkstack.c
endif endif
ifeq ($(CONFIG_ELF),y)
CMN_CSRCS += up_elf.c up_coherent_dcache.c
else ifeq ($(CONFIG_MODULE),y)
CMN_CSRCS += up_elf.c up_coherent_dcache.c
endif
# Required STM32L4 files # Required STM32L4 files
CHIP_ASRCS = CHIP_ASRCS =
arch/arm/src/stm32l4/stm32l4_oneshot.c
+208 -21
View File
@@ -1,7 +1,7 @@
/**************************************************************************** /****************************************************************************
* arch/arm/src/stm32l4/stm32l4_oneshot.c * arch/arm/src/stm32l4/stm32l4_oneshot.c
* *
* Copyright (C) 2016 Gregory Nutt. All rights reserved. * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* dev@ziggurat29.com * dev@ziggurat29.com
* *
@@ -43,6 +43,7 @@
#include <sys/types.h> #include <sys/types.h>
#include <stdint.h> #include <stdint.h>
#include <stdbool.h> #include <stdbool.h>
#include <sched.h>
#include <assert.h> #include <assert.h>
#include <errno.h> #include <errno.h>
#include <debug.h> #include <debug.h>
@@ -55,10 +56,66 @@
#ifdef CONFIG_STM32L4_ONESHOT #ifdef CONFIG_STM32L4_ONESHOT
/**************************************************************************** /****************************************************************************
* Private Date * Private Function Prototypes
****************************************************************************/ ****************************************************************************/
static struct stm32l4_oneshot_s *g_oneshot; static int stm32l4_oneshot_handler(struct stm32l4_oneshot_s *oneshot);
static int stm32l4_oneshot1_handler(int irq, void *context);
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 1
static int stm32l4_oneshot2_handler(int irq, void *context);
#endif
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 2
static int stm32l4_oneshot3_handler(int irq, void *context);
#endif
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 3
static int stm32l4_oneshot4_handler(int irq, void *context);
#endif
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 4
static int stm32l4_oneshot5_handler(int irq, void *context);
#endif
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 5
static int stm32l4_oneshot6_handler(int irq, void *context);
#endif
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 6
static int stm32l4_oneshot7_handler(int irq, void *context);
#endif
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 7
static int stm32l4_oneshot8_handler(int irq, void *context);
#endif
/****************************************************************************
* Private Data
****************************************************************************/
static struct stm32l4_oneshot_s *g_oneshot[CONFIG_STM32L4_ONESHOT_MAXTIMERS];
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 1
static const xcpt_t g_callbacks[CONFIG_STM32L4_ONESHOT_MAXTIMERS] =
{
stm32l4_oneshot1_handler,
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 1
stm32l4_oneshot2_handler,
#endif
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 2
stm32l4_oneshot3_handler,
#endif
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 3
stm32l4_oneshot4_handler,
#endif
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 4
stm32l4_oneshot5_handler,
#endif
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 5
stm32l4_oneshot6_handler,
#endif
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 6
stm32l4_oneshot7_handler,
#endif
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 7
stm32l4_oneshot8_handler,
#endif
};
#endif
/**************************************************************************** /****************************************************************************
* Private Functions * Private Functions
@@ -68,24 +125,20 @@ static struct stm32l4_oneshot_s *g_oneshot;
* Name: stm32l4_oneshot_handler * Name: stm32l4_oneshot_handler
* *
* Description: * Description:
* Timer interrupt callback. When the oneshot timer interrupt expires, * Common timer interrupt callback. When any oneshot timer interrupt
* this function will be called. It will forward the call to the next * expires, this function will be called. It will forward the call to
* level up. * the next level up.
* *
* Input Parameters: * Input Parameters:
* tch - The handle that represents the timer state * oneshot - The state associated with the expired timer
* arg - An opaque argument provided when the interrupt was registered
* sr - The value of the timer interrupt status register at the time
* that the interrupt occurred.
* *
* Returned Value: * Returned Value:
* None * Always returns OK
* *
****************************************************************************/ ****************************************************************************/
static int stm32l4_oneshot_handler(int irq, FAR void *context) static int stm32l4_oneshot_handler(struct stm32l4_oneshot_s *oneshot)
{ {
FAR struct stm32l4_oneshot_s *oneshot = g_oneshot;
oneshot_handler_t oneshot_handler; oneshot_handler_t oneshot_handler;
FAR void *oneshot_arg; FAR void *oneshot_arg;
@@ -116,6 +169,137 @@ static int stm32l4_oneshot_handler(int irq, FAR void *context)
return OK; return OK;
} }
/****************************************************************************
* Name: stm32l4_oneshot[N]_handler
*
* Description:
* Timer interrupt callbacks. When a oneshot timer interrupt expires,
* one of these functions will be called. These functions will forward
* the call to the nextlevel up.
*
* Input Parameters:
* Standard interrupt handler arguments.
*
* Returned Value:
* Always returns OK
*
****************************************************************************/
static int stm32l4_oneshot1_handler(int irq, void *context)
{
DEBUGASSERT(g_oneshot[0] != NULL);
return stm32l4_oneshot_handler(g_oneshot[0]);
}
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 1
static int stm32l4_oneshot2_handler(int irq, void *context)
{
DEBUGASSERT(g_oneshot[1] != NULL);
return stm32l4_oneshot_handler(g_oneshot[1]);
}
#endif
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 2
static int stm32l4_oneshot3_handler(int irq, void *context)
{
DEBUGASSERT(g_oneshot[2] != NULL);
return stm32l4_oneshot_handler(g_oneshot[2]);
}
#endif
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 3
static int stm32l4_oneshot4_handler(int irq, void *context)
{
DEBUGASSERT(g_oneshot[3] != NULL);
return stm32l4_oneshot_handler(g_oneshot[3]);
}
#endif
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 4
static int stm32l4_oneshot5_handler(int irq, void *context)
{
DEBUGASSERT(g_oneshot[4] != NULL);
return stm32l4_oneshot_handler(g_oneshot[4]);
}
#endif
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 5
static int stm32l4_oneshot6_handler(int irq, void *context)
{
DEBUGASSERT(g_oneshot[6] != NULL);
return stm32l4_oneshot_handler(g_oneshot[5]);
}
#endif
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 6
static int stm32l4_oneshot7_handler(int irq, void *context)
{
DEBUGASSERT(g_oneshot[7] != NULL);
return stm32l4_oneshot_handler(g_oneshot[6]);
}
#endif
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 7
static int stm32l4_oneshot8_handler(int irq, void *context)
{
DEBUGASSERT(g_oneshot[0] != NULL);
return stm32l4_oneshot_handler(g_oneshot[7]);
}
#endif
/****************************************************************************
* Name: stm32l4_allocate_handler
*
* Description:
* Allocate a timer callback handler for the oneshot instance.
*
* Input Parameters:
* oneshot - The state instance the new oneshot timer
*
* Returned Value:
* Returns zero (OK) on success. This can only fail if the number of
* timers exceeds CONFIG_STM32L4_ONESHOT_MAXTIMERS.
*
****************************************************************************/
static inline int stm32l4_allocate_handler(struct stm32l4_oneshot_s *oneshot)
{
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 1
int ret = -EBUSY;
int i;
/* Search for an unused handler */
sched_lock();
for (i = 0; i < CONFIG_STM32L4_ONESHOT_MAXTIMERS; i++)
{
/* Is this handler available? */
if (g_oneshot[i] == NULL)
{
/* Yes... assign it to this oneshot */
g_oneshot[i] = oneshot;
oneshot->cbndx = i;
ret = OK;
break;
}
}
sched_unlock();
return ret;
#else
if (g_oneshot[0] == NULL)
{
g_oneshot[0] = oneshot;
return OK;
}
return -EBUSY;
#endif
}
/**************************************************************************** /****************************************************************************
* Public Functions * Public Functions
****************************************************************************/ ****************************************************************************/
@@ -139,8 +323,8 @@ static int stm32l4_oneshot_handler(int irq, FAR void *context)
* *
****************************************************************************/ ****************************************************************************/
int stm32l4_oneshot_initialize(FAR struct stm32l4_oneshot_s *oneshot, int chan, int stm32l4_oneshot_initialize(FAR struct stm32l4_oneshot_s *oneshot,
uint16_t resolution) int chan, uint16_t resolution)
{ {
uint32_t frequency; uint32_t frequency;
@@ -161,17 +345,16 @@ int stm32l4_oneshot_initialize(FAR struct stm32l4_oneshot_s *oneshot, int chan,
STM32L4_TIM_SETCLOCK(oneshot->tch, frequency); STM32L4_TIM_SETCLOCK(oneshot->tch, frequency);
/* Initialize the remaining fields in the state structure and return /* Initialize the remaining fields in the state structure. */
* success.
*/
oneshot->chan = chan; oneshot->chan = chan;
oneshot->running = false; oneshot->running = false;
oneshot->handler = NULL; oneshot->handler = NULL;
oneshot->arg = NULL; oneshot->arg = NULL;
g_oneshot = oneshot; /* Assign a callback handler to the oneshot */
return OK;
return stm32l4_allocate_handler(oneshot);
} }
/**************************************************************************** /****************************************************************************
@@ -261,7 +444,11 @@ int stm32l4_oneshot_start(FAR struct stm32l4_oneshot_s *oneshot,
/* Set up to receive the callback when the interrupt occurs */ /* Set up to receive the callback when the interrupt occurs */
STM32L4_TIM_SETISR(oneshot->tch, stm32l4_oneshot_handler, 0); #if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 1
STM32L4_TIM_SETISR(oneshot->tch, g_callbacks[oneshot->cbndx], 0);
#else
STM32L4_TIM_SETISR(oneshot->tch, stm32l4_oneshot1_handler, 0);
#endif
/* Set timer period */ /* Set timer period */
arch/arm/src/stm32l4/stm32l4_oneshot.h
+22 -1
View File
@@ -1,7 +1,7 @@
/**************************************************************************** /****************************************************************************
* arch/arm/src/stm32l4/stm32l4_oneshot.h * arch/arm/src/stm32l4/stm32l4_oneshot.h
* *
* Copyright (C) 2016 Gregory Nutt. All rights reserved. * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* dev@ziggurat29.com * dev@ziggurat29.com
* *
@@ -46,10 +46,28 @@
#include <stdint.h> #include <stdint.h>
#include <time.h> #include <time.h>
#include <nuttx/irq.h>
#include "stm32l4_tim.h" #include "stm32l4_tim.h"
#ifdef CONFIG_STM32L4_ONESHOT #ifdef CONFIG_STM32L4_ONESHOT
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if !defined(CONFIG_STM32L4_ONESHOT_MAXTIMERS) || \
CONFIG_STM32L4_ONESHOT_MAXTIMERS < 1
# undef CONFIG_STM32L4_ONESHOT_MAXTIMERS
# define CONFIG_STM32L4_ONESHOT_MAXTIMERS 1
#endif
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 8
# warning Additional logic required to handle more than 8 timers
# undef CONFIG_STM32L4_ONESHOT_MAXTIMERS
# define CONFIG_STM32L4_ONESHOT_MAXTIMERS 8
#endif
/**************************************************************************** /****************************************************************************
* Public Types * Public Types
****************************************************************************/ ****************************************************************************/
@@ -71,6 +89,9 @@ typedef void (*oneshot_handler_t)(void *arg);
struct stm32l4_oneshot_s struct stm32l4_oneshot_s
{ {
uint8_t chan; /* The timer/counter in use */ uint8_t chan; /* The timer/counter in use */
#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 1
uint8_t cbndx; /* Timer callback handler index */
#endif
volatile bool running; /* True: the timer is running */ volatile bool running; /* True: the timer is running */
FAR struct stm32l4_tim_dev_s *tch; /* Pointer returned by FAR struct stm32l4_tim_dev_s *tch; /* Pointer returned by
* stm32l4_tim_init() */ * stm32l4_tim_init() */

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