mirror of
https://github.com/apache/nuttx.git
synced 2026-06-04 14:53:47 +08:00
Rename all lpc313x to lpc31xx
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3644 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -1771,4 +1771,6 @@
|
|||||||
* drivers/net/e1000.c/h: A PCI-based E1000 ethernet driver submitted
|
* drivers/net/e1000.c/h: A PCI-based E1000 ethernet driver submitted
|
||||||
by Yu Qiang.
|
by Yu Qiang.
|
||||||
* lib/net/lib_inetaddr.c: An implementatino of the inet_addr() function
|
* lib/net/lib_inetaddr.c: An implementatino of the inet_addr() function
|
||||||
submitted y Yu Qiang.
|
submitted y Yu Qiang.
|
||||||
|
* arch/arm/src/lpc31xx and arch/arm/include/lpc31xx: Renamed from lpc313x
|
||||||
|
to make name space for other famiy members.
|
||||||
|
|||||||
@@ -1,7 +1,7 @@
|
|||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* arch/arm/include/lpc313x/irq.h
|
* arch/arm/include/lpc31xx/irq.h
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
@@ -37,8 +37,8 @@
|
|||||||
* only indirectly through nuttx/irq.h
|
* only indirectly through nuttx/irq.h
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef __ARCH_ARM_INCLUDE_LPC313X_IRQ_H
|
#ifndef __ARCH_ARM_INCLUDE_LPC31XX_IRQ_H
|
||||||
#define __ARCH_ARM_INCLUDE_LPC313X_IRQ_H
|
#define __ARCH_ARM_INCLUDE_LPC31XX_IRQ_H
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Included Files
|
* Included Files
|
||||||
@@ -48,41 +48,41 @@
|
|||||||
* Definitions
|
* Definitions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
/* LPC313X Interrupts */
|
/* LPC31XX Interrupts */
|
||||||
|
|
||||||
/* IRQ0: Reserved */
|
/* IRQ0: Reserved */
|
||||||
#define LPC313X_IRQ_IRQ0 0 /* IRQ1: Event router cascaded IRQ0 */
|
#define LPC31_IRQ_IRQ0 0 /* IRQ1: Event router cascaded IRQ0 */
|
||||||
#define LPC313X_IRQ_IRQ1 1 /* IRQ2: Event router cascaded IRQ1 */
|
#define LPC31_IRQ_IRQ1 1 /* IRQ2: Event router cascaded IRQ1 */
|
||||||
#define LPC313X_IRQ_IRQ2 2 /* IRQ3: Event router cascaded IRQ2 */
|
#define LPC31_IRQ_IRQ2 2 /* IRQ3: Event router cascaded IRQ2 */
|
||||||
#define LPC313X_IRQ_IRQ3 3 /* IRQ4: Event router cascaded IRQ3 */
|
#define LPC31_IRQ_IRQ3 3 /* IRQ4: Event router cascaded IRQ3 */
|
||||||
#define LPC313X_IRQ_TMR0 4 /* IRQ5: Timer 0 Interrupt */
|
#define LPC31_IRQ_TMR0 4 /* IRQ5: Timer 0 Interrupt */
|
||||||
#define LPC313X_IRQ_TMR1 5 /* IRQ6: Timer 1 Interrupt */
|
#define LPC31_IRQ_TMR1 5 /* IRQ6: Timer 1 Interrupt */
|
||||||
#define LPC313X_IRQ_TMR2 6 /* IRQ7: Timer 2 Interrupt */
|
#define LPC31_IRQ_TMR2 6 /* IRQ7: Timer 2 Interrupt */
|
||||||
#define LPC313X_IRQ_TMR3 7 /* IRQ8: Timer 3 Interrupt */
|
#define LPC31_IRQ_TMR3 7 /* IRQ8: Timer 3 Interrupt */
|
||||||
#define LPC313X_IRQ_ADC 8 /* IRQ9: ADC 10-bit */
|
#define LPC31_IRQ_ADC 8 /* IRQ9: ADC 10-bit */
|
||||||
#define LPC313X_IRQ_UART 9 /* IRQ10: UART */
|
#define LPC31_IRQ_UART 9 /* IRQ10: UART */
|
||||||
#define LPC313X_IRQ_I2C0 10 /* IRQ11: I2C0 */
|
#define LPC31_IRQ_I2C0 10 /* IRQ11: I2C0 */
|
||||||
#define LPC313X_IRQ_I2C1 11 /* IRQ12: I2C1 */
|
#define LPC31_IRQ_I2C1 11 /* IRQ12: I2C1 */
|
||||||
#define LPC313X_IRQ_I2STX0 12 /* IRQ13: I2S0 Transmit */
|
#define LPC31_IRQ_I2STX0 12 /* IRQ13: I2S0 Transmit */
|
||||||
#define LPC313X_IRQ_I2STX1 13 /* IRQ14: I2S1 Transmit */
|
#define LPC31_IRQ_I2STX1 13 /* IRQ14: I2S1 Transmit */
|
||||||
#define LPC313X_IRQ_I2SRX0 14 /* IRQ15: I2S0 Receive */
|
#define LPC31_IRQ_I2SRX0 14 /* IRQ15: I2S0 Receive */
|
||||||
#define LPC313X_IRQ_I2SRX1 15 /* IRQ16: I2S1 Receive */
|
#define LPC31_IRQ_I2SRX1 15 /* IRQ16: I2S1 Receive */
|
||||||
/* IRQ17: Reserved */
|
/* IRQ17: Reserved */
|
||||||
#define LPC313X_IRQ_LCD 17 /* IRQ18: LCD Interface */
|
#define LPC31_IRQ_LCD 17 /* IRQ18: LCD Interface */
|
||||||
#define LPC313X_IRQ_SPISMS 18 /* IRQ19: SPI SMS */
|
#define LPC31_IRQ_SPISMS 18 /* IRQ19: SPI SMS */
|
||||||
#define LPC313X_IRQ_SPITX 19 /* IRQ20: SPI Transmit */
|
#define LPC31_IRQ_SPITX 19 /* IRQ20: SPI Transmit */
|
||||||
#define LPC313X_IRQ_SPIRX 20 /* IRQ21: SPI Receive */
|
#define LPC31_IRQ_SPIRX 20 /* IRQ21: SPI Receive */
|
||||||
#define LPC313X_IRQ_SPIOVF 21 /* IRQ22: SPI Overflow */
|
#define LPC31_IRQ_SPIOVF 21 /* IRQ22: SPI Overflow */
|
||||||
#define LPC313X_IRQ_SPI 22 /* IRQ23: SPI */
|
#define LPC31_IRQ_SPI 22 /* IRQ23: SPI */
|
||||||
#define LPC313X_IRQ_DMA 23 /* IRQ24: DMA */
|
#define LPC31_IRQ_DMA 23 /* IRQ24: DMA */
|
||||||
#define LPC313X_IRQ_NAND 24 /* IRQ25: NAND FLASH Controller */
|
#define LPC31_IRQ_NAND 24 /* IRQ25: NAND FLASH Controller */
|
||||||
#define LPC313X_IRQ_MCI 25 /* IRQ26: MCI */
|
#define LPC31_IRQ_MCI 25 /* IRQ26: MCI */
|
||||||
#define LPC313X_IRQ_USBOTG 26 /* IRQ27: USB OTG */
|
#define LPC31_IRQ_USBOTG 26 /* IRQ27: USB OTG */
|
||||||
#define LPC313X_IRQ_ISRAM0 27 /* IRQ28: ISRAM0 MRC Finished */
|
#define LPC31_IRQ_ISRAM0 27 /* IRQ28: ISRAM0 MRC Finished */
|
||||||
#define LPC313X_IRQ_ISRAM1 28 /* IRQ29: ISRAM1 MRC Finished */
|
#define LPC31_IRQ_ISRAM1 28 /* IRQ29: ISRAM1 MRC Finished */
|
||||||
|
|
||||||
#define LPC313X_IRQ_SYSTIMER LPC313X_IRQ_TMR0
|
#define LPC31_IRQ_SYSTIMER LPC31_IRQ_TMR0
|
||||||
#define NR_IRQS (LPC313X_IRQ_ISRAM1+1)
|
#define NR_IRQS (LPC31_IRQ_ISRAM1+1)
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Public Types
|
* Public Types
|
||||||
@@ -114,5 +114,5 @@ extern "C" {
|
|||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif /* __ARCH_ARM_INCLUDE_LPC313X_IRQ_H */
|
#endif /* __ARCH_ARM_INCLUDE_LPC31XX_IRQ_H */
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -1,423 +0,0 @@
|
|||||||
/************************************************************************************************
|
|
||||||
* arch/arm/src/lpc313x/lpc313x_dma.h
|
|
||||||
*
|
|
||||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions
|
|
||||||
* are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in
|
|
||||||
* the documentation and/or other materials provided with the
|
|
||||||
* distribution.
|
|
||||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
|
||||||
* used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
|
||||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
|
||||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
|
||||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
|
||||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
|
||||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
||||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|
||||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
#ifndef __ARCH_ARM_SRC_LPC313X_DMA_H
|
|
||||||
#define __ARCH_ARM_SRC_LPC313X_DMA_H
|
|
||||||
|
|
||||||
/************************************************************************************************
|
|
||||||
* Included Files
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
#include <nuttx/config.h>
|
|
||||||
#include "lpc313x_memorymap.h"
|
|
||||||
|
|
||||||
/************************************************************************************************
|
|
||||||
* Pre-processor Definitions
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
/* DMA register base address offset into the APB4 domain ****************************************/
|
|
||||||
|
|
||||||
#define LPC313X_DMA_VBASE (LPC313X_APB4_VADDR+LPC313X_APB4_DMA_OFFSET)
|
|
||||||
#define LPC313X_DMA_PBASE (LPC313X_APB4_PADDR+LPC313X_APB4_DMA_OFFSET)
|
|
||||||
|
|
||||||
/* DMA channel offsets (with respect to the DMA register base address) **************************/
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN_OFFSET(n) ((n)*0x020)
|
|
||||||
#define LPC313X_DMACHAN0_OFFSET 0x000
|
|
||||||
#define LPC313X_DMACHAN1_OFFSET 0x020
|
|
||||||
#define LPC313X_DMACHAN2_OFFSET 0x040
|
|
||||||
#define LPC313X_DMACHAN3_OFFSET 0x060
|
|
||||||
#define LPC313X_DMACHAN4_OFFSET 0x080
|
|
||||||
#define LPC313X_DMACHAN5_OFFSET 0x0a0
|
|
||||||
#define LPC313X_DMACHAN6_OFFSET 0x0c0
|
|
||||||
#define LPC313X_DMACHAN7_OFFSET 0x0e0
|
|
||||||
#define LPC313X_DMACHAN8_OFFSET 0x100
|
|
||||||
#define LPC313X_DMACHAN9_OFFSET 0x120
|
|
||||||
#define LPC313X_DMACHAN10_OFFSET 0x140
|
|
||||||
#define LPC313X_DMACHAN11_OFFSET 0x160
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN_ALT_OFFSET(n) (0x200+((n)*0x020))
|
|
||||||
#define LPC313X_DMACHAN0_ALT_OFFSET 0x200
|
|
||||||
#define LPC313X_DMACHAN1_ALT_OFFSET 0x220
|
|
||||||
#define LPC313X_DMACHAN2_ALT_OFFSET 0x240
|
|
||||||
#define LPC313X_DMACHAN3_ALT_OFFSET 0x260
|
|
||||||
#define LPC313X_DMACHAN4_ALT_OFFSET 0x280
|
|
||||||
#define LPC313X_DMACHAN5_ALT_OFFSET 0x2a0
|
|
||||||
#define LPC313X_DMACHAN6_ALT_OFFSET 0x2c0
|
|
||||||
#define LPC313X_DMACHAN7_ALT_OFFSET 0x2e0
|
|
||||||
#define LPC313X_DMACHAN8_ALT_OFFSET 0x300
|
|
||||||
#define LPC313X_DMACHAN9_ALT_OFFSET 0x320
|
|
||||||
#define LPC313X_DMACHAN10_ALT_OFFSET 0x340
|
|
||||||
#define LPC313X_DMACHAN11_ALT_OFFSET 0x360
|
|
||||||
|
|
||||||
/* DMA channel virtual base addresses ***********************************************************/
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN_VBASE(n) (LPC313X_DMA_VBASE+LPC313X_DMACHAN_OFFSET(n))
|
|
||||||
#define LPC313X_DMACHAN0_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN0_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN1_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN1_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN2_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN2_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN3_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN3_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN4_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN4_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN5_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN5_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN6_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN6_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN7_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN7_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN8_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN8_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN9_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN9_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN10_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN10_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN11_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN11_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN_ALT_VBASE(n) (LPC313X_DMA_VBASE+LPC313X_DMACHAN_ALT_OFFSET(n))
|
|
||||||
#define LPC313X_DMACHAN0_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN0_ALT_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN1_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN1_ALT_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN2_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN2_ALT_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN3_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN3_ALT_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN4_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN4_ALT_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN5_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN5_ALT_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN6_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN6_ALT_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN7_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN7_ALT_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN8_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN8_ALT_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN9_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN9_ALT_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN10_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN10_ALT_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN11_VBASE (LPC313X_DMA_VBASE+LPC313X_DMACHAN11_ALT_OFFSET)
|
|
||||||
|
|
||||||
/* DMA channel register offsets (with respect to the DMA channel register base) *****************/
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN_SRCADDR_OFFSET 0x000 /* Source address register of DMA channel */
|
|
||||||
#define LPC313X_DMACHAN_DESTADDR_OFFSET 0X004 /* Destination address register of DMA channel */
|
|
||||||
#define LPC313X_DMACHAN_XFERLEN_OFFSET 0X008 /* Transfer length register for DMA channel */
|
|
||||||
#define LPC313X_DMACHAN_CONFIG_OFFSET 0x00c /* Configuration register for DMA channel */
|
|
||||||
#define LPC313X_DMACHAN_ENABLE_OFFSET 0x010 /* Enable register for DMA channel */
|
|
||||||
#define LPC313X_DMACHAN_XFERCOUNT_OFFSET 0x01c /* Transfer counter register for DMA channel */
|
|
||||||
|
|
||||||
/* DMA global register offsets (with respect to the DMA register base) *************************/
|
|
||||||
|
|
||||||
#define LPC313X_DMA_ALTENABLE_OFFSET 0x400 /* Alternative enable register */
|
|
||||||
#define LPC313X_DMA_IRQSTATUSCLR_OFFSET 0x404 /* IRQ status clear register */
|
|
||||||
#define LPC313X_DMA_IRQMASK_OFFSET 0x408 /* IRQ mask register */
|
|
||||||
#define LPC313X_DMA_TESTSTATUS_OFFSET 0x40c /* Test FIFO response status register */
|
|
||||||
#define LPC313X_DMA_SOFTINT_OFFSET 0x410 /* Software interrupt register */
|
|
||||||
|
|
||||||
/* DMA channel register (virtual) addresses *****************************************************/
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN_SRCADDR(n) (LPC313X_DMACHAN_VBASE(n)+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN_DESTADDR(n) (LPC313X_DMACHAN_VBASE(n)+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN_XFERLEN(n) (LPC313X_DMACHAN_VBASE(n)+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN_CONFIG(n) (LPC313X_DMACHAN_VBASE(n)+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN_ENABLE(n) (LPC313X_DMACHAN_VBASE(n)+LPC313X_DMACHAN_ENABLE_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN_XFERCOUNT(n) (LPC313X_DMACHAN_VBASE(n)+LPC313X_DMACHAN_XFERCOUNT_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN0_SRCADDR (LPC313X_DMACHAN0_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN0_DESTADDR (LPC313X_DMACHAN0_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN0_XFERLEN (LPC313X_DMACHAN0_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN0_CONFIG (LPC313X_DMACHAN0_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN0_ENABLE (LPC313X_DMACHAN0_VBASE+LPC313X_DMACHAN_ENABLE_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN0_XFERCOUNT (LPC313X_DMACHAN0_VBASE+LPC313X_DMACHAN_XFERCOUNT_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN1_SRCADDR (LPC313X_DMACHAN1_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN1_DESTADDR (LPC313X_DMACHAN1_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN1_XFERLEN (LPC313X_DMACHAN1_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN1_CONFIG (LPC313X_DMACHAN1_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN1_ENABLE (LPC313X_DMACHAN1_VBASE+LPC313X_DMACHAN_ENABLE_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN1_XFERCOUNT (LPC313X_DMACHAN1_VBASE+LPC313X_DMACHAN_XFERCOUNT_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN2_SRCADDR (LPC313X_DMACHAN2_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN2_DESTADDR (LPC313X_DMACHAN2_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN2_XFERLEN (LPC313X_DMACHAN2_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN2_CONFIG (LPC313X_DMACHAN2_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN2_ENABLE (LPC313X_DMACHAN2_VBASE+LPC313X_DMACHAN_ENABLE_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN2_XFERCOUNT (LPC313X_DMACHAN2_VBASE+LPC313X_DMACHAN_XFERCOUNT_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN3_SRCADDR (LPC313X_DMACHAN3_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN3_DESTADDR (LPC313X_DMACHAN3_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN3_XFERLEN (LPC313X_DMACHAN3_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN3_CONFIG (LPC313X_DMACHAN3_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN3_ENABLE (LPC313X_DMACHAN3_VBASE+LPC313X_DMACHAN_ENABLE_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN3_XFERCOUNT (LPC313X_DMACHAN3_VBASE+LPC313X_DMACHAN_XFERCOUNT_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN4_SRCADDR (LPC313X_DMACHAN4_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN4_DESTADDR (LPC313X_DMACHAN4_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN4_XFERLEN (LPC313X_DMACHAN4_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN4_CONFIG (LPC313X_DMACHAN4_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN4_ENABLE (LPC313X_DMACHAN4_VBASE+LPC313X_DMACHAN_ENABLE_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN4_XFERCOUNT (LPC313X_DMACHAN4_VBASE+LPC313X_DMACHAN_XFERCOUNT_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN5_SRCADDR (LPC313X_DMACHAN5_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN5_DESTADDR (LPC313X_DMACHAN5_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN5_XFERLEN (LPC313X_DMACHAN5_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN5_CONFIG (LPC313X_DMACHAN5_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN5_ENABLE (LPC313X_DMACHAN5_VBASE+LPC313X_DMACHAN_ENABLE_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN5_XFERCOUNT (LPC313X_DMACHAN5_VBASE+LPC313X_DMACHAN_XFERCOUNT_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN6_SRCADDR (LPC313X_DMACHAN6_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN6_DESTADDR (LPC313X_DMACHAN6_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN6_XFERLEN (LPC313X_DMACHAN6_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN6_CONFIG (LPC313X_DMACHAN6_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN6_ENABLE (LPC313X_DMACHAN6_VBASE+LPC313X_DMACHAN_ENABLE_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN6_XFERCOUNT (LPC313X_DMACHAN6_VBASE+LPC313X_DMACHAN_XFERCOUNT_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN7_SRCADDR (LPC313X_DMACHAN7_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN7_DESTADDR (LPC313X_DMACHAN7_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN7_XFERLEN (LPC313X_DMACHAN7_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN7_CONFIG (LPC313X_DMACHAN7_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN7_ENABLE (LPC313X_DMACHAN7_VBASE+LPC313X_DMACHAN_ENABLE_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN7_XFERCOUNT (LPC313X_DMACHAN7_VBASE+LPC313X_DMACHAN_XFERCOUNT_OFFSET)7
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN8_SRCADDR (LPC313X_DMACHAN8_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN8_DESTADDR (LPC313X_DMACHAN8_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN8_XFERLEN (LPC313X_DMACHAN8_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN8_CONFIG (LPC313X_DMACHAN8_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN8_ENABLE (LPC313X_DMACHAN8_VBASE+LPC313X_DMACHAN_ENABLE_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN8_XFERCOUNT (LPC313X_DMACHAN8_VBASE+LPC313X_DMACHAN_XFERCOUNT_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN9_SRCADDR (LPC313X_DMACHAN9_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN9_DESTADDR (LPC313X_DMACHAN9_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN9_XFERLEN (LPC313X_DMACHAN9_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN9_CONFIG (LPC313X_DMACHAN9_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN9_ENABLE (LPC313X_DMACHAN9_VBASE+LPC313X_DMACHAN_ENABLE_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN9_XFERCOUNT (LPC313X_DMACHAN9_VBASE+LPC313X_DMACHAN_XFERCOUNT_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN10_SRCADDR (LPC313X_DMACHAN10_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN10_DESTADDR (LPC313X_DMACHAN10_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN10_XFERLEN (LPC313X_DMACHAN10_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN10_CONFIG (LPC313X_DMACHAN10_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN10_ENABLE (LPC313X_DMACHAN10_VBASE+LPC313X_DMACHAN_ENABLE_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN10_XFERCOUNT (LPC313X_DMACHAN10_VBASE+LPC313X_DMACHAN_XFERCOUNT_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN11_SRCADDR (LPC313X_DMACHAN11_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN11_DESTADDR (LPC313X_DMACHAN11_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN11_XFERLEN (LPC313X_DMACHAN11_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN11_CONFIG (LPC313X_DMACHAN11_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN11_ENABLE (LPC313X_DMACHAN11_VBASE+LPC313X_DMACHAN_ENABLE_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN11_XFERCOUNT (LPC313X_DMACHAN11_VBASE+LPC313X_DMACHAN_XFERCOUNT_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN_ALT_SRCADDR(n) (LPC313X_DMACHAN_ALT_VBASE(n)+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN_ALT_DESTADDR(n) (LPC313X_DMACHAN_ALT_VBASE(n)+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN_ALT_XFERLEN(n) (LPC313X_DMACHAN_ALT_VBASE(n)+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN_ALT_CONFIG(n) (LPC313X_DMACHAN_ALT_VBASE(n)+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN0_ALT_SRCADDR (LPC313X_DMACHAN0_ALT_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN0_ALT_DESTADDR (LPC313X_DMACHAN0_ALT_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN0_ALT_XFERLEN (LPC313X_DMACHAN0_ALT_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN0_ALT_CONFIG (LPC313X_DMACHAN0_ALT_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN1_ALT_SRCADDR (LPC313X_DMACHAN1_ALT_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN1_ALT_DESTADDR (LPC313X_DMACHAN1_ALT_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN1_ALT_XFERLEN (LPC313X_DMACHAN1_ALT_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN1_ALT_CONFIG (LPC313X_DMACHAN1_ALT_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN2_ALT_SRCADDR (LPC313X_DMACHAN2_ALT_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN2_ALT_DESTADDR (LPC313X_DMACHAN2_ALT_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN2_ALT_XFERLEN (LPC313X_DMACHAN2_ALT_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN2_ALT_CONFIG (LPC313X_DMACHAN2_ALT_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN3_ALT_SRCADDR (LPC313X_DMACHAN3_ALT_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN3_ALT_DESTADDR (LPC313X_DMACHAN3_ALT_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN3_ALT_XFERLEN (LPC313X_DMACHAN3_ALT_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN3_ALT_CONFIG (LPC313X_DMACHAN3_ALT_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN4_ALT_SRCADDR (LPC313X_DMACHAN4_ALT_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN4_ALT_DESTADDR (LPC313X_DMACHAN4_ALT_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN4_ALT_XFERLEN (LPC313X_DMACHAN4_ALT_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN4_ALT_CONFIG (LPC313X_DMACHAN4_ALT_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN5_ALT_SRCADDR (LPC313X_DMACHAN5_ALT_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN5_ALT_DESTADDR (LPC313X_DMACHAN5_ALT_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN5_ALT_XFERLEN (LPC313X_DMACHAN5_ALT_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN5_ALT_CONFIG (LPC313X_DMACHAN5_ALT_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN6_ALT_SRCADDR (LPC313X_DMACHAN6_ALT_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN6_ALT_DESTADDR (LPC313X_DMACHAN6_ALT_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN6_ALT_XFERLEN (LPC313X_DMACHAN6_ALT_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN6_ALT_CONFIG (LPC313X_DMACHAN6_ALT_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN7_ALT_SRCADDR (LPC313X_DMACHAN7_ALT_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN7_ALT_DESTADDR (LPC313X_DMACHAN7_ALT_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN7_ALT_XFERLEN (LPC313X_DMACHAN7_ALT_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN7_ALT_CONFIG (LPC313X_DMACHAN7_ALT_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN8_ALT_SRCADDR (LPC313X_DMACHAN8_ALT_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN8_ALT_DESTADDR (LPC313X_DMACHAN8_ALT_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN8_ALT_XFERLEN (LPC313X_DMACHAN8_ALT_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN8_ALT_CONFIG (LPC313X_DMACHAN8_ALT_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN9_ALT_SRCADDR (LPC313X_DMACHAN9_ALT_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN9_ALT_DESTADDR (LPC313X_DMACHAN9_ALT_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN9_ALT_XFERLEN (LPC313X_DMACHAN9_ALT_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN9_ALT_CONFIG (LPC313X_DMACHAN9_ALT_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN10_ALT_SRCADDR (LPC313X_DMACHAN10_ALT_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN10_ALT_DESTADDR (LPC313X_DMACHAN10_ALT_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN10_ALT_XFERLEN (LPC313X_DMACHAN10_ALT_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN10_ALT_CONFIG (LPC313X_DMACHAN10_ALT_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_DMACHAN11_ALT_SRCADDR (LPC313X_DMACHAN11_ALT_VBASE+LPC313X_DMACHAN_SRCADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN11_ALT_DESTADDR (LPC313X_DMACHAN11_ALT_VBASE+LPC313X_DMACHAN_DESTADDR_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN11_ALT_XFERLEN (LPC313X_DMACHAN11_ALT_VBASE+LPC313X_DMACHAN_XFERLEN_OFFSET)
|
|
||||||
#define LPC313X_DMACHAN11_ALT_CONFIG (LPC313X_DMACHAN11_ALT_VBASE+LPC313X_DMACHAN_CONFIG_OFFSET)
|
|
||||||
|
|
||||||
/* DMA global register (virtual) addresses ******************************************************/
|
|
||||||
|
|
||||||
#define LPC313X_DMA_ALTENABLE (LPC313X_DMA_VBASE+LPC313X_DMA_ALTENABLE_OFFSET)
|
|
||||||
#define LPC313X_DMA_IRQSTATUSCLR (LPC313X_DMA_VBASE+LPC313X_DMA_IRQSTATUSCLR_OFFSET)
|
|
||||||
#define LPC313X_DMA_IRQMASK (LPC313X_DMA_VBASE+LPC313X_DMA_IRQMASK_OFFSET)
|
|
||||||
#define LPC313X_DMA_TESTSTATUS (LPC313X_DMA_VBASE+LPC313X_DMA_TESTSTATUS_OFFSET)
|
|
||||||
#define LPC313X_DMA_SOFTINT (LPC313X_DMA_VBASE+LPC313X_DMA_SOFTINT_OFFSET)
|
|
||||||
|
|
||||||
/* DMA channel register bit definitions *********************************************************/
|
|
||||||
|
|
||||||
/* TRANSFER_LENGTH (addresses 0x17000008 (channel 0) to 0x17000168 (channel 11)) */
|
|
||||||
|
|
||||||
#define DMACHAN_XFRLEN_SHIFT (0) /* Bits 0-20: Transfer length */
|
|
||||||
#define DMACHAN_XFRLEN_MASK (0x001fffff << DMACHAN_XFRLEN_SHIFT)
|
|
||||||
|
|
||||||
/* CONFIGURATION (addresses 0x1700000c (channel 0) to 0x1700016c (channel 11)) */
|
|
||||||
|
|
||||||
#define DMACHAN_CONFIG_CIRC (1 << 18) /* Bit 18: Enable circular buffer */
|
|
||||||
#define DMACHAN_CONFIG_COMPCHENABLE (1 << 17) /* Bit 17: Enable companion channel */
|
|
||||||
#define DMACHAN_CONFIG_COMPCHNR_SHIFT (13) /* Bits 13-15: Companion channel number */
|
|
||||||
#define DMACHAN_CONFIG_COMPCHNR_MASK (7 << DMACHAN_CONFIG_COMPCHNR_SHIFT)
|
|
||||||
#define DMACHAN_CONFIG_INVENDIAN (1 << 12) /* Bit 12: Invert endian-ness */
|
|
||||||
#define DMACHAN_CONFIG_XFERSIZE_SHIFT (10) /* Bits 10-11: Transfer size */
|
|
||||||
#define DMACHAN_CONFIG_XFERSIZE_MASK (3 << DMACHAN_CONFIG_XFERSIZE_SHIFT)
|
|
||||||
# define DMACHAN_CONFIG_XFERSIZE_WORDS (0 << DMACHAN_CONFIG_XFERSIZE_SHIFT) /* Transfer words */
|
|
||||||
# define DMACHAN_CONFIG_XFERSIZE_HWORDS (1 << DMACHAN_CONFIG_XFERSIZE_SHIFT) /* Transfer half-words */
|
|
||||||
# define DMACHAN_CONFIG_XFERSIZE_BYTES (2 << DMACHAN_CONFIG_XFERSIZE_SHIFT) /* Transfer bytes */
|
|
||||||
# define DMACHAN_CONFIG_XFERSIZE_BURSTS (3 << DMACHAN_CONFIG_XFERSIZE_SHIFT) /* Transfer bursts */
|
|
||||||
#define DMACHAN_CONFIG_RDSLAVENR_SHIFT (5) /* Bits 5-9: Read slave enable */
|
|
||||||
#define DMACHAN_CONFIG_RDSLAVENR_MASK (31 << DMACHAN_CONFIG_RDSLAVENR_SHIFT)
|
|
||||||
#define DMACHAN_CONFIG_WRSLAVENR_SHIFT (0) /* Bits 0-4: Write slave enable */
|
|
||||||
#define DMACHAN_CONFIG_WRSLAVENR_MASK (31 << DMACHAN_CONFIG_WRSLAVENR_SHIFT)
|
|
||||||
|
|
||||||
/* ENABLE (addresses 0x17000010 (channel 0) to 0x17000170 (channel 11)) */
|
|
||||||
|
|
||||||
#define DMACHAN_ENABLE_BIT (1 << 0) /* Bit 0: Enable */
|
|
||||||
|
|
||||||
/* TRANSFER_COUNTER (addresses 0x1700001v (channel 0) to 0x1700017c (channel 11)) */
|
|
||||||
|
|
||||||
#define DMACHAN_XFRCOUNT_SHIFT (0) /* Bits 0-20: Transfer count */
|
|
||||||
#define DMACHAN_XFRCOUNT_MASK (0x001fffff << DMACHAN_XFRCOUNT_SHIFT)
|
|
||||||
|
|
||||||
/* DMA global register bit definitions **********************************************************/
|
|
||||||
|
|
||||||
/* ALT_ENABLE (address 0x17000400) */
|
|
||||||
|
|
||||||
#define DMA_ALTENABLE_CHAN11 (1 << 11) /* Bit 11: Enable channel 11 */
|
|
||||||
#define DMA_ALTENABLE_CHAN10 (1 << 10) /* Bit 10: Enable channel 10 */
|
|
||||||
#define DMA_ALTENABLE_CHAN9 (1 << 9) /* Bit 9: Enable channel 9 */
|
|
||||||
#define DMA_ALTENABLE_CHAN8 (1 << 8) /* Bit 8: Enable channel 8 */
|
|
||||||
#define DMA_ALTENABLE_CHAN7 (1 << 7) /* Bit 7: Enable channel 7 */
|
|
||||||
#define DMA_ALTENABLE_CHAN6 (1 << 6) /* Bit 6: Enable channel 6 */
|
|
||||||
#define DMA_ALTENABLE_CHAN5 (1 << 5) /* Bit 5: Enable channel 5 */
|
|
||||||
#define DMA_ALTENABLE_CHAN4 (1 << 4) /* Bit 4: Enable channel 4 */
|
|
||||||
#define DMA_ALTENABLE_CHAN3 (1 << 3) /* Bit 3: Enable channel 3 */
|
|
||||||
#define DMA_ALTENABLE_CHAN2 (1 << 2) /* Bit 2: Enable channel 2 */
|
|
||||||
#define DMA_ALTENABLE_CHAN1 (1 << 1) /* Bit 1: Enable channel 1 */
|
|
||||||
#define DMA_ALTENABLE_CHAN0 (1 << 0) /* Bit 0: Enable channel 0 */
|
|
||||||
|
|
||||||
/* IRQ_STATUS_CLR (address 0x17000404) */
|
|
||||||
|
|
||||||
#define DMA_IRQSTATUSCLR_DMAABORT (1 << 31) /* Bit 31: DMA abort */
|
|
||||||
#define DMA_IRQSTATUSCLR_SOFTINT (1 << 30) /* Bit 30: Soft interrupt, scatter gather */
|
|
||||||
#define DMA_IRQSTATUSCLR_HALFWAY11 (1 << 23) /* Bit 23: Chan 11 more than half finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_FINISHED11 (1 << 22) /* Bit 22: Chan 11 finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_HALFWAY10 (1 << 21) /* Bit 21: Chan 10 more than half finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_FINISHED10 (1 << 20) /* Bit 20: Chan 10 finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_HALFWAY9 (1 << 19) /* Bit 19: Chan 9 more than half finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_FINISHED9 (1 << 18) /* Bit 18: Chan 9 finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_HALFWAY8 (1 << 17) /* Bit 17: Chan 8 more than half finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_FINISHED8 (1 << 16) /* Bit 16: Chan 8 finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_HALFWAY7 (1 << 15) /* Bit 15: Chan 7 more than half finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_FINISHED7 (1 << 14) /* Bit 14: Chan 7 finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_HALFWAY6 (1 << 13) /* Bit 13: Chan 6 more than half finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_FINISHED6 (1 << 12) /* Bit 12: Chan 6 finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_HALFWAY5 (1 << 11) /* Bit 11: Chan 5 more than half finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_FINISHED5 (1 << 10) /* Bit 10: Chan 5 finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_HALFWAY4 (1 << 9) /* Bit 9: Chan 4 more than half finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_FINISHED4 (1 << 8) /* Bit 8: Chan 4 finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_HALFWAY3 (1 << 7) /* Bit 7: Chan 3 more than half finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_FINISHED3 (1 << 6) /* Bit 6: Chan 3 finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_HALFWAY2 (1 << 5) /* Bit 5: Chan 2 more than half finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_FINISHED2 (1 << 4) /* Bit 4: Chan 2 finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_HALFWAY1 (1 << 3) /* Bit 3: Chan 1 more than half finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_FINISHED1 (1 << 2) /* Bit 2: Chan 1 finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_HALFWAY0 (1 << 1) /* Bit 1: Chan 0 more than half finished */
|
|
||||||
#define DMA_IRQSTATUSCLR_FINISHED0 (1 << 0) /* Bit 0: Chan 0 finished */
|
|
||||||
|
|
||||||
/* IRQ_MASK (address 0x17000404) */
|
|
||||||
|
|
||||||
#define DMA_IRQMASK_DMAABORT (1 << 31) /* Bit 31: DMA abort */
|
|
||||||
#define DMA_IRQMASK_SOFTINT (1 << 30) /* Bit 30: Soft interrupt, scatter gather */
|
|
||||||
#define DMA_IRQMASK_HALFWAY11 (1 << 23) /* Bit 23: Chan 11 more than half finished */
|
|
||||||
#define DMA_IRQMASK_FINISHED11 (1 << 22) /* Bit 22: Chan 11 finished */
|
|
||||||
#define DMA_IRQMASK_HALFWAY10 (1 << 21) /* Bit 21: Chan 10 more than half finished */
|
|
||||||
#define DMA_IRQMASK_FINISHED10 (1 << 20) /* Bit 20: Chan 10 finished */
|
|
||||||
#define DMA_IRQMASK_HALFWAY9 (1 << 19) /* Bit 19: Chan 9 more than half finished */
|
|
||||||
#define DMA_IRQMASK_FINISHED9 (1 << 18) /* Bit 18: Chan 9 finished */
|
|
||||||
#define DMA_IRQMASK_HALFWAY8 (1 << 17) /* Bit 17: Chan 8 more than half finished */
|
|
||||||
#define DMA_IRQMASK_FINISHED8 (1 << 16) /* Bit 16: Chan 8 finished */
|
|
||||||
#define DMA_IRQMASK_HALFWAY7 (1 << 15) /* Bit 15: Chan 7 more than half finished */
|
|
||||||
#define DMA_IRQMASK_FINISHED7 (1 << 14) /* Bit 14: Chan 7 finished */
|
|
||||||
#define DMA_IRQMASK_HALFWAY6 (1 << 13) /* Bit 13: Chan 6 more than half finished */
|
|
||||||
#define DMA_IRQMASK_FINISHED6 (1 << 12) /* Bit 12: Chan 6 finished */
|
|
||||||
#define DMA_IRQMASK_HALFWAY5 (1 << 11) /* Bit 11: Chan 5 more than half finished */
|
|
||||||
#define DMA_IRQMASK_FINISHED5 (1 << 10) /* Bit 10: Chan 5 finished */
|
|
||||||
#define DMA_IRQMASK_HALFWAY4 (1 << 9) /* Bit 9: Chan 4 more than half finished */
|
|
||||||
#define DMA_IRQMASK_FINISHED4 (1 << 8) /* Bit 8: Chan 4 finished */
|
|
||||||
#define DMA_IRQMASK_HALFWAY3 (1 << 7) /* Bit 7: Chan 3 more than half finished */
|
|
||||||
#define DMA_IRQMASK_FINISHED3 (1 << 6) /* Bit 6: Chan 3 finished */
|
|
||||||
#define DMA_IRQMASK_HALFWAY2 (1 << 5) /* Bit 5: Chan 2 more than half finished */
|
|
||||||
#define DMA_IRQMASK_FINISHED2 (1 << 4) /* Bit 4: Chan 2 finished */
|
|
||||||
#define DMA_IRQMASK_HALFWAY1 (1 << 3) /* Bit 3: Chan 1 more than half finished */
|
|
||||||
#define DMA_IRQMASK_FINISHED1 (1 << 2) /* Bit 2: Chan 1 finished */
|
|
||||||
#define DMA_IRQMASK_HALFWAY0 (1 << 1) /* Bit 1: Chan 0 more than half finished */
|
|
||||||
#define DMA_IRQMASK_FINISHED0 (1 << 0) /* Bit 0: Chan 0 finished */
|
|
||||||
|
|
||||||
/* SOFT_INT (address 0x1700040c) */
|
|
||||||
|
|
||||||
#define DMA_SOFTINT_ENABLE (1 << 0) /* Bit 0: Enable soft interrupt */
|
|
||||||
|
|
||||||
/************************************************************************************************
|
|
||||||
* Public Types
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
/************************************************************************************************
|
|
||||||
* Public Data
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
/************************************************************************************************
|
|
||||||
* Public Functions
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
#endif /* __ARCH_ARM_SRC_LPC313X_DMA_H */
|
|
||||||
@@ -1,315 +0,0 @@
|
|||||||
/************************************************************************************************
|
|
||||||
* arch/arm/src/lpc313x/lpc313x_i2s.h
|
|
||||||
*
|
|
||||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions
|
|
||||||
* are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in
|
|
||||||
* the documentation and/or other materials provided with the
|
|
||||||
* distribution.
|
|
||||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
|
||||||
* used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
|
||||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
|
||||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
|
||||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
|
||||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
|
||||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
||||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|
||||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
#ifndef __ARCH_ARM_SRC_LPC313X_I2S_H
|
|
||||||
#define __ARCH_ARM_SRC_LPC313X_I2S_H
|
|
||||||
|
|
||||||
/************************************************************************************************
|
|
||||||
* Included Files
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
#include <nuttx/config.h>
|
|
||||||
#include "lpc313x_memorymap.h"
|
|
||||||
|
|
||||||
/************************************************************************************************
|
|
||||||
* Pre-processor Definitions
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
/* I2S register base address offset into the APB3 domain ****************************************/
|
|
||||||
|
|
||||||
#define LPC313X_I2SCONFIG_VBASE (LPC313X_APB3_VSECTION+LPC313X_APB3_I2SCONFIG_OFFSET)
|
|
||||||
#define LPC313X_I2SCONFIG_PBASE (LPC313X_APB3_PSECTION+LPC313X_APB3_I2SCONFIG_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_I2STX0_VBASE (LPC313X_APB3_VSECTION+LPC313X_APB3_I2STX0_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_PBASE (LPC313X_APB3_PSECTION+LPC313X_APB3_I2STX0_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_I2STX1_VBASE (LPC313X_APB3_VSECTION+LPC313X_APB3_I2STX1_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_PBASE (LPC313X_APB3_PSECTION+LPC313X_APB3_I2STX1_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_I2SRX0_VBASE (LPC313X_APB3_VSECTION+LPC313X_APB3_I2SRX0_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_PBASE (LPC313X_APB3_PSECTION+LPC313X_APB3_I2SRX0_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_I2SRX1_VBASE (LPC313X_APB3_VSECTION+LPC313X_APB3_I2SRX1_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_PBASE (LPC313X_APB3_PSECTION+LPC313X_APB3_I2SRX1_OFFSET)
|
|
||||||
|
|
||||||
/* I2S register offsets (with respect to the I2S base) ******************************************/
|
|
||||||
/* I2S configuration module offset */
|
|
||||||
|
|
||||||
#define LPC313X_I2SCONFIG_FORMAT_OFFSET 0x000 /* I2S formats */
|
|
||||||
#define LPC313X_I2SCONFIG_CFGMUX_OFFSET 0x004 /* Misc controls */
|
|
||||||
/* 0x008-0x00c: Reserved */
|
|
||||||
#define LPC313X_I2SCONFIG_NSOFCNTR_OFFSET 0x010 /* NSOF counter control */
|
|
||||||
|
|
||||||
/* I2STX0, I2STX1, I2SRX0, and I2SRX1 module offsets */
|
|
||||||
|
|
||||||
#define LPC313X_I2S_L16BIT_OFFSET 0x000 /* 16 bits left channel data */
|
|
||||||
#define LPC313X_I2S_R16BIT_OFFSET 0x004 /* 16 bits right channel data */
|
|
||||||
#define LPC313X_I2S_L24BIT_OFFSET 0x008 /* 24 bits left channel data */
|
|
||||||
#define LPC313X_I2S_R24BIT_OFFSET 0x00c /* 24 bits right channel data */
|
|
||||||
#define LPC313X_I2S_INTSTATUS_OFFSET 0x010 /* FIFO status register */
|
|
||||||
#define LPC313X_I2S_INTMASK_OFFSET 0x014 /* Interrupt Mask register */
|
|
||||||
#define LPC313X_I2S_L32BIT_OFFSET(n) (0x020+((n)<<2))
|
|
||||||
#define LPC313X_I2S_L32BIT0_OFFSET 0x020 /* 2x16 bits left channel data */
|
|
||||||
#define LPC313X_I2S_L32BIT1_OFFSET 0x024 /* " " " " " " " " " " */
|
|
||||||
#define LPC313X_I2S_L32BIT2_OFFSET 0x028 /* " " " " " " " " " " */
|
|
||||||
#define LPC313X_I2S_L32BIT3_OFFSET 0x02c /* " " " " " " " " " " */
|
|
||||||
#define LPC313X_I2S_L32BIT4_OFFSET 0x030 /* " " " " " " " " " " */
|
|
||||||
#define LPC313X_I2S_L32BIT5_OFFSET 0x034 /* " " " " " " " " " " */
|
|
||||||
#define LPC313X_I2S_L32BIT6_OFFSET 0x038 /* " " " " " " " " " " */
|
|
||||||
#define LPC313X_I2S_L32BIT7_OFFSET 0x03c /* " " " " " " " " " " */
|
|
||||||
#define LPC313X_I2S_R32BIT_OFFSET(n) (0x040+((n)<<2))
|
|
||||||
#define LPC313X_I2S_R32BIT0_OFFSET 0x040 /* 2x16 bits right channel data */
|
|
||||||
#define LPC313X_I2S_R32BIT1_OFFSET 0x044 /* " " " " " " " " " " */
|
|
||||||
#define LPC313X_I2S_R32BIT2_OFFSET 0x048 /* " " " " " " " " " " */
|
|
||||||
#define LPC313X_I2S_R32BIT3_OFFSET 0x04c /* " " " " " " " " " " */
|
|
||||||
#define LPC313X_I2S_R32BIT4_OFFSET 0x050 /* " " " " " " " " " " */
|
|
||||||
#define LPC313X_I2S_R32BIT5_OFFSET 0x054 /* " " " " " " " " " " */
|
|
||||||
#define LPC313X_I2S_R32BIT6_OFFSET 0x058 /* " " " " " " " " " " */
|
|
||||||
#define LPC313X_I2S_R32BIT7_OFFSET 0x05c /* " " " " " " " " " " */
|
|
||||||
#define LPC313X_I2S_ILVD_OFFSET(n) (0x060+((n)<<2))
|
|
||||||
#define LPC313X_I2S_ILVD0_OFFSET 0x060 /* Interleaved data */
|
|
||||||
#define LPC313X_I2S_ILVD1_OFFSET 0x064 /* " " " " */
|
|
||||||
#define LPC313X_I2S_ILVD2_OFFSET 0x068 /* " " " " */
|
|
||||||
#define LPC313X_I2S_ILVD3_OFFSET 0x06c /* " " " " */
|
|
||||||
#define LPC313X_I2S_ILVD4_OFFSET 0x070 /* " " " " */
|
|
||||||
#define LPC313X_I2S_ILVD5_OFFSET 0x074 /* " " " " */
|
|
||||||
#define LPC313X_I2S_ILVD6_OFFSET 0x078 /* " " " " */
|
|
||||||
#define LPC313X_I2S_ILVD7_OFFSET 0x07c /* " " " " */
|
|
||||||
|
|
||||||
/* I2S register (virtual) addresses *************************************************************/
|
|
||||||
/* I2S configuration module registers */
|
|
||||||
|
|
||||||
#define LPC313X_I2SCONFIG_FORMAT (LPC313X_I2SCONFIG_VBASE+lPC313X_I2SCONFIG_FORMAT_OFFSET)
|
|
||||||
#define LPC313X_I2SCONFIG_CFGMUX (LPC313X_I2SCONFIG_VBASE+LPC313X_I2SCONFIG_CFGMUX_OFFSET)
|
|
||||||
#define LPC313X_I2SCONFIG_NSOFCNTR (LPC313X_I2SCONFIG_VBASE+LPC313X_I2SCONFIG_NSOFCNTR_OFFSET)
|
|
||||||
|
|
||||||
/* I2STX0 module registers */
|
|
||||||
|
|
||||||
#define LPC313X_I2STX0_L16BIT (LPC313X_I2STX0_VBASE+LPC313X_I2S_L16BIT_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_R16BIT (LPC313X_I2STX0_VBASE+LPC313X_I2S_R16BIT_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_L24BIT (LPC313X_I2STX0_VBASE+LPC313X_I2S_L24BIT_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_R24BIT (LPC313X_I2STX0_VBASE+LPC313X_I2S_R24BIT_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_INTSTATUS (LPC313X_I2STX0_VBASE+LPC313X_I2S_INTSTATUS_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_INTMASK (LPC313X_I2STX0_VBASE+LPC313X_I2S_INTMASK_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_L32BIT(n) (LPC313X_I2STX0_VBASE+LPC313X_I2S_L32BIT_OFFSET(n))
|
|
||||||
#define LPC313X_I2STX0_L32BIT0 (LPC313X_I2STX0_VBASE+LPC313X_I2S_L32BIT0_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_L32BIT1 (LPC313X_I2STX0_VBASE+LPC313X_I2S_L32BIT1_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_L32BIT2 (LPC313X_I2STX0_VBASE+LPC313X_I2S_L32BIT2_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_L32BIT3 (LPC313X_I2STX0_VBASE+LPC313X_I2S_L32BIT3_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_L32BIT4 (LPC313X_I2STX0_VBASE+LPC313X_I2S_L32BIT4_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_L32BIT5 (LPC313X_I2STX0_VBASE+LPC313X_I2S_L32BIT5_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_L32BIT6 (LPC313X_I2STX0_VBASE+LPC313X_I2S_L32BIT6_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_L32BIT7 (LPC313X_I2STX0_VBASE+LPC313X_I2S_L32BIT7_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_R32BIT(n) (LPC313X_I2STX0_VBASE+LPC313X_I2S_R32BIT_OFFSET(n))
|
|
||||||
#define LPC313X_I2STX0_R32BIT0 (LPC313X_I2STX0_VBASE+LPC313X_I2S_R32BIT0_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_R32BIT1 (LPC313X_I2STX0_VBASE+LPC313X_I2S_R32BIT1_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_R32BIT2 (LPC313X_I2STX0_VBASE+LPC313X_I2S_R32BIT2_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_R32BIT3 (LPC313X_I2STX0_VBASE+LPC313X_I2S_R32BIT3_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_R32BIT4 (LPC313X_I2STX0_VBASE+LPC313X_I2S_R32BIT4_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_R32BIT5 (LPC313X_I2STX0_VBASE+LPC313X_I2S_R32BIT5_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_R32BIT6 (LPC313X_I2STX0_VBASE+LPC313X_I2S_R32BIT6_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_R32BIT7 (LPC313X_I2STX0_VBASE+LPC313X_I2S_R32BIT7_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_ILVD(n) (LPC313X_I2STX0_VBASE+LPC313X_I2S_ILVD_OFFSET(n))
|
|
||||||
#define LPC313X_I2STX0_ILVD0 (LPC313X_I2STX0_VBASE+LPC313X_I2S_ILVD0_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_ILVD1 (LPC313X_I2STX0_VBASE+LPC313X_I2S_ILVD1_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_ILVD2 (LPC313X_I2STX0_VBASE+LPC313X_I2S_ILVD2_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_ILVD3 (LPC313X_I2STX0_VBASE+LPC313X_I2S_ILVD3_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_ILVD4 (LPC313X_I2STX0_VBASE+LPC313X_I2S_ILVD4_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_ILVD5 (LPC313X_I2STX0_VBASE+LPC313X_I2S_ILVD5_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_ILVD6 (LPC313X_I2STX0_VBASE+LPC313X_I2S_ILVD6_OFFSET)
|
|
||||||
#define LPC313X_I2STX0_ILVD7 (LPC313X_I2STX0_VBASE+LPC313X_I2S_ILVD7_OFFSET)
|
|
||||||
|
|
||||||
/* I2STX1 module registers */
|
|
||||||
|
|
||||||
#define LPC313X_I2STX1_L16BIT (LPC313X_I2STX1_VBASE+LPC313X_I2S_L16BIT_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_R16BIT (LPC313X_I2STX1_VBASE+LPC313X_I2S_R16BIT_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_L24BIT (LPC313X_I2STX1_VBASE+LPC313X_I2S_L24BIT_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_R24BIT (LPC313X_I2STX1_VBASE+LPC313X_I2S_R24BIT_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_INTSTATUS (LPC313X_I2STX1_VBASE+LPC313X_I2S_INTSTATUS_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_INTMASK (LPC313X_I2STX1_VBASE+LPC313X_I2S_INTMASK_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_L32BIT(n) (LPC313X_I2STX1_VBASE+LPC313X_I2S_L32BIT_OFFSET(n))
|
|
||||||
#define LPC313X_I2STX1_L32BIT0 (LPC313X_I2STX1_VBASE+LPC313X_I2S_L32BIT0_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_L32BIT1 (LPC313X_I2STX1_VBASE+LPC313X_I2S_L32BIT1_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_L32BIT2 (LPC313X_I2STX1_VBASE+LPC313X_I2S_L32BIT2_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_L32BIT3 (LPC313X_I2STX1_VBASE+LPC313X_I2S_L32BIT3_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_L32BIT4 (LPC313X_I2STX1_VBASE+LPC313X_I2S_L32BIT4_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_L32BIT5 (LPC313X_I2STX1_VBASE+LPC313X_I2S_L32BIT5_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_L32BIT6 (LPC313X_I2STX1_VBASE+LPC313X_I2S_L32BIT6_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_L32BIT7 (LPC313X_I2STX1_VBASE+LPC313X_I2S_L32BIT7_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_R32BIT(n) (LPC313X_I2STX1_VBASE+LPC313X_I2S_R32BIT_OFFSET(n))
|
|
||||||
#define LPC313X_I2STX1_R32BIT0 (LPC313X_I2STX1_VBASE+LPC313X_I2S_R32BIT0_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_R32BIT1 (LPC313X_I2STX1_VBASE+LPC313X_I2S_R32BIT1_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_R32BIT2 (LPC313X_I2STX1_VBASE+LPC313X_I2S_R32BIT2_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_R32BIT3 (LPC313X_I2STX1_VBASE+LPC313X_I2S_R32BIT3_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_R32BIT4 (LPC313X_I2STX1_VBASE+LPC313X_I2S_R32BIT4_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_R32BIT5 (LPC313X_I2STX1_VBASE+LPC313X_I2S_R32BIT5_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_R32BIT6 (LPC313X_I2STX1_VBASE+LPC313X_I2S_R32BIT6_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_R32BIT7 (LPC313X_I2STX1_VBASE+LPC313X_I2S_R32BIT7_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_ILVD(n) (LPC313X_I2STX1_VBASE+LPC313X_I2S_ILVD_OFFSET(n))
|
|
||||||
#define LPC313X_I2STX1_ILVD0 (LPC313X_I2STX1_VBASE+LPC313X_I2S_ILVD0_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_ILVD1 (LPC313X_I2STX1_VBASE+LPC313X_I2S_ILVD1_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_ILVD2 (LPC313X_I2STX1_VBASE+LPC313X_I2S_ILVD2_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_ILVD3 (LPC313X_I2STX1_VBASE+LPC313X_I2S_ILVD3_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_ILVD4 (LPC313X_I2STX1_VBASE+LPC313X_I2S_ILVD4_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_ILVD5 (LPC313X_I2STX1_VBASE+LPC313X_I2S_ILVD5_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_ILVD6 (LPC313X_I2STX1_VBASE+LPC313X_I2S_ILVD6_OFFSET)
|
|
||||||
#define LPC313X_I2STX1_ILVD7 (LPC313X_I2STX1_VBASE+LPC313X_I2S_ILVD7_OFFSET)
|
|
||||||
|
|
||||||
/* I2SRX0 module registers */
|
|
||||||
|
|
||||||
#define LPC313X_I2SRX0_L16BIT (LPC313X_I2SRX0_VBASE+LPC313X_I2S_L16BIT_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_R16BIT (LPC313X_I2SRX0_VBASE+LPC313X_I2S_R16BIT_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_L24BIT (LPC313X_I2SRX0_VBASE+LPC313X_I2S_L24BIT_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_R24BIT (LPC313X_I2SRX0_VBASE+LPC313X_I2S_R24BIT_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_INTSTATUS (LPC313X_I2SRX0_VBASE+LPC313X_I2S_INTSTATUS_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_INTMASK (LPC313X_I2SRX0_VBASE+LPC313X_I2S_INTMASK_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_L32BIT(n) (LPC313X_I2SRX0_VBASE+LPC313X_I2S_L32BIT_OFFSET(n))
|
|
||||||
#define LPC313X_I2SRX0_L32BIT0 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_L32BIT0_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_L32BIT1 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_L32BIT1_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_L32BIT2 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_L32BIT2_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_L32BIT3 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_L32BIT3_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_L32BIT4 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_L32BIT4_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_L32BIT5 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_L32BIT5_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_L32BIT6 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_L32BIT6_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_L32BIT7 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_L32BIT7_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_R32BIT(n) (LPC313X_I2SRX0_VBASE+LPC313X_I2S_R32BIT_OFFSET(n))
|
|
||||||
#define LPC313X_I2SRX0_R32BIT0 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_R32BIT0_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_R32BIT1 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_R32BIT1_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_R32BIT2 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_R32BIT2_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_R32BIT3 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_R32BIT3_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_R32BIT4 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_R32BIT4_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_R32BIT5 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_R32BIT5_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_R32BIT6 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_R32BIT6_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_R32BIT7 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_R32BIT7_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_ILVD(n) (LPC313X_I2SRX0_VBASE+LPC313X_I2S_ILVD_OFFSET(n))
|
|
||||||
#define LPC313X_I2SRX0_ILVD0 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_ILVD0_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_ILVD1 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_ILVD1_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_ILVD2 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_ILVD2_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_ILVD3 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_ILVD3_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_ILVD4 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_ILVD4_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_ILVD5 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_ILVD5_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_ILVD6 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_ILVD6_OFFSET)
|
|
||||||
#define LPC313X_I2SRX0_ILVD7 (LPC313X_I2SRX0_VBASE+LPC313X_I2S_ILVD7_OFFSET)
|
|
||||||
|
|
||||||
/* I2SRX1 module registers */
|
|
||||||
|
|
||||||
#define LPC313X_I2SRX1_L16BIT (LPC313X_I2SRX1_VBASE+LPC313X_I2S_L16BIT_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_R16BIT (LPC313X_I2SRX1_VBASE+LPC313X_I2S_R16BIT_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_L24BIT (LPC313X_I2SRX1_VBASE+LPC313X_I2S_L24BIT_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_R24BIT (LPC313X_I2SRX1_VBASE+LPC313X_I2S_R24BIT_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_INTSTATUS (LPC313X_I2SRX1_VBASE+LPC313X_I2S_INTSTATUS_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_INTMASK (LPC313X_I2SRX1_VBASE+LPC313X_I2S_INTMASK_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_L32BIT(n) (LPC313X_I2SRX1_VBASE+LPC313X_I2S_L32BIT_OFFSET(n))
|
|
||||||
#define LPC313X_I2SRX1_L32BIT0 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_L32BIT0_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_L32BIT1 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_L32BIT1_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_L32BIT2 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_L32BIT2_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_L32BIT3 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_L32BIT3_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_L32BIT4 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_L32BIT4_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_L32BIT5 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_L32BIT5_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_L32BIT6 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_L32BIT6_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_L32BIT7 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_L32BIT7_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_R32BIT(n) (LPC313X_I2SRX1_VBASE+LPC313X_I2S_R32BIT_OFFSET(n))
|
|
||||||
#define LPC313X_I2SRX1_R32BIT0 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_R32BIT0_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_R32BIT1 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_R32BIT1_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_R32BIT2 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_R32BIT2_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_R32BIT3 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_R32BIT3_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_R32BIT4 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_R32BIT4_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_R32BIT5 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_R32BIT5_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_R32BIT6 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_R32BIT6_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_R32BIT7 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_R32BIT7_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_ILVD(n) (LPC313X_I2SRX1_VBASE+LPC313X_I2S_ILVD_OFFSET(n))
|
|
||||||
#define LPC313X_I2SRX1_ILVD0 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_ILVD0_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_ILVD1 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_ILVD1_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_ILVD2 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_ILVD2_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_ILVD3 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_ILVD3_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_ILVD4 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_ILVD4_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_ILVD5 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_ILVD5_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_ILVD6 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_ILVD6_OFFSET)
|
|
||||||
#define LPC313X_I2SRX1_ILVD7 (LPC313X_I2SRX1_VBASE+LPC313X_I2S_ILVD7_OFFSET)
|
|
||||||
|
|
||||||
/* I2S register bit definitions *****************************************************************/
|
|
||||||
/* I2S configuration module offset */
|
|
||||||
|
|
||||||
/* I2SCONFIG_FORMAT address 0x16000000 */
|
|
||||||
|
|
||||||
#define I2SCONFIG_FORMAT_I2SRX1_SHIFT (9) /* Bits 9-11: I2SRX1 I2S output format */
|
|
||||||
#define I2SCONFIG_FORMAT_I2SRX1_MASK (7 << I2SCONFIG_FORMAT_I2SRX1_SHIFT)
|
|
||||||
# define I2SCONFIG_FORMAT_I2SRX1_I2S (3 << I2SCONFIG_FORMAT_I2SRX1_SHIFT) /* I2S */
|
|
||||||
# define I2SCONFIG_FORMAT_I2SRX1_16BIT (4 << I2SCONFIG_FORMAT_I2SRX1_SHIFT) /* LSB justified 16 bits */
|
|
||||||
# define I2SCONFIG_FORMAT_I2SRX1_18BIT (5 << I2SCONFIG_FORMAT_I2SRX1_SHIFT) /* LSB justified 18 bits */
|
|
||||||
# define I2SCONFIG_FORMAT_I2SRX1_20BIT (6 << I2SCONFIG_FORMAT_I2SRX1_SHIFT) /* LSB justified 20 bits */
|
|
||||||
# define I2SCONFIG_FORMAT_I2SRX1_24BIT (7 << I2SCONFIG_FORMAT_I2SRX1_SHIFT) /* LSB justified 24 bits */
|
|
||||||
#define I2SCONFIG_FORMAT_I2SRX0_SHIFT (6) /* Bits 6-8: I2SRX0 I2S output format */
|
|
||||||
#define I2SCONFIG_FORMAT_I2SRX0_MASK (7 << I2SCONFIG_FORMAT_I2SRX0_SHIFT)
|
|
||||||
# define I2SCONFIG_FORMAT_I2SRX0_I2S (3 << I2SCONFIG_FORMAT_I2SRX0_SHIFT) /* I2S */
|
|
||||||
# define I2SCONFIG_FORMAT_I2SRX0_16BIT (4 << I2SCONFIG_FORMAT_I2SRX0_SHIFT) /* LSB justified 16 bits */
|
|
||||||
# define I2SCONFIG_FORMAT_I2SRX0_18BIT (5 << I2SCONFIG_FORMAT_I2SRX0_SHIFT) /* LSB justified 18 bits */
|
|
||||||
# define I2SCONFIG_FORMAT_I2SRX0_20BIT (6 << I2SCONFIG_FORMAT_I2SRX0_SHIFT) /* LSB justified 20 bits */
|
|
||||||
# define I2SCONFIG_FORMAT_I2SRX0_24BIT (7 << I2SCONFIG_FORMAT_I2SRX0_SHIFT) /* LSB justified 24 bits */
|
|
||||||
#define I2SCONFIG_FORMAT_I2STX1_SHIFT (3) /* Bits 3-5: 2STX1 I2S input format */
|
|
||||||
#define I2SCONFIG_FORMAT_I2STX1_MASK (7 << I2SCONFIG_FORMAT_I2STX1_SHIFT)
|
|
||||||
# define I2SCONFIG_FORMAT_I2STX1_I2S (3 << I2SCONFIG_FORMAT_I2STX1_SHIFT) /* I2S */
|
|
||||||
# define I2SCONFIG_FORMAT_I2STX1_16BIT (4 << I2SCONFIG_FORMAT_I2STX1_SHIFT) /* LSB justified 16 bits */
|
|
||||||
# define I2SCONFIG_FORMAT_I2STX1_18BIT (5 << I2SCONFIG_FORMAT_I2STX1_SHIFT) /* LSB justified 18 bits */
|
|
||||||
# define I2SCONFIG_FORMAT_I2STX1_20BIT (6 << I2SCONFIG_FORMAT_I2STX1_SHIFT) /* LSB justified 20 bits */
|
|
||||||
# define I2SCONFIG_FORMAT_I2STX1_24BIT (7 << I2SCONFIG_FORMAT_I2STX1_SHIFT) /* LSB justified 24 bits */
|
|
||||||
#define I2SCONFIG_FORMAT_I2STX0_SHIFT (0) /* Bits 0-2: I2STX0 I2S input format */
|
|
||||||
#define I2SCONFIG_FORMAT_I2STX0_MASK (7 << I2SCONFIG_FORMAT_I2STX0_SHIFT)
|
|
||||||
# define I2SCONFIG_FORMAT_I2STX0_I2S (3 << I2SCONFIG_FORMAT_I2STX0_SHIFT) /* I2S */
|
|
||||||
# define I2SCONFIG_FORMAT_I2STX0_16BIT (4 << I2SCONFIG_FORMAT_I2STX0_SHIFT) /* LSB justified 16 bits */
|
|
||||||
# define I2SCONFIG_FORMAT_I2STX0_18BIT (5 << I2SCONFIG_FORMAT_I2STX0_SHIFT) /* LSB justified 18 bits */
|
|
||||||
# define I2SCONFIG_FORMAT_I2STX0_20BIT (6 << I2SCONFIG_FORMAT_I2STX0_SHIFT) /* LSB justified 20 bits */
|
|
||||||
# define I2SCONFIG_FORMAT_I2STX0_24BIT (7 << I2SCONFIG_FORMAT_I2STX0_SHIFT) /* LSB justified 24 bits */
|
|
||||||
|
|
||||||
/* II2SCONFIG_CFGMUX address 0x16000004 */
|
|
||||||
|
|
||||||
#define I2SCONFIG_CFGMUX_I2SRX1OEN (1 << 2) /* Bit 2: Selects faster mode for I2SRX1 */
|
|
||||||
#define I2SCONFIG_CFGMUX_I2SRX0OEN (1 << 1) /* Bit 1: Slects master mode for I2SRX0 */
|
|
||||||
|
|
||||||
/* I2SCONFIG_NSOFCNT address 0x16000010 */
|
|
||||||
|
|
||||||
/************************************************************************************************
|
|
||||||
* Public Types
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
/************************************************************************************************
|
|
||||||
* Public Data
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
/************************************************************************************************
|
|
||||||
* Public Functions
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
#endif /* __ARCH_ARM_SRC_LPC313X_I2S_H */
|
|
||||||
@@ -1,198 +0,0 @@
|
|||||||
/************************************************************************************************
|
|
||||||
* arch/arm/src/lpc313x/lpc313x_intc.h
|
|
||||||
*
|
|
||||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions
|
|
||||||
* are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in
|
|
||||||
* the documentation and/or other materials provided with the
|
|
||||||
* distribution.
|
|
||||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
|
||||||
* used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
|
||||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
|
||||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
|
||||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
|
||||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
|
||||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
||||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|
||||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
#ifndef __ARCH_ARM_SRC_LPC313X_INTC_H
|
|
||||||
#define __ARCH_ARM_SRC_LPC313X_INTC_H
|
|
||||||
|
|
||||||
/************************************************************************************************
|
|
||||||
* Included Files
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
#include <nuttx/config.h>
|
|
||||||
#include "lpc313x_memorymap.h"
|
|
||||||
|
|
||||||
/************************************************************************************************
|
|
||||||
* Pre-processor Definitions
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
/* INTC register base address *******************************************************************/
|
|
||||||
|
|
||||||
#define LPC313X_INTC_VBASE (LPC313X_INTC_VSECTION)
|
|
||||||
#define LPC313X_INTC_PBASE (LPC313X_INTC_PSECTION)
|
|
||||||
|
|
||||||
/* INTC register offsets (with respect to the base of the INTC domain) **************************/
|
|
||||||
|
|
||||||
#define LPC313X_INTC_PRIORITYMASK0_OFFSET 0x000 /* Interrupt target 0 priority threshold */
|
|
||||||
#define LPC313X_INTC_PRIORITYMASK1_OFFSET 0x004 /* Interrupt target 0 priority threshold */
|
|
||||||
#define LPC313X_INTC_VECTOR0_OFFSET 0x100 /* Vector register for target 0 => nIRQ */
|
|
||||||
#define LPC313X_INTC_VECTOR1_OFFSET 0x104 /* Vector register for target 1 => nFIQ */
|
|
||||||
#define LPC313X_INTC_PENDING_OFFSET 0x200 /* Status of interrupt request 1..29 */
|
|
||||||
#define LPC313X_INTC_FEATURES_OFFSET 0x300 /* Interrupt controller configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST_OFFSET(n) (0x400+((n) << 2))
|
|
||||||
#define LPC313X_INTC_REQUEST1_OFFSET 0x404 /* Interrupt request 1 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST2_OFFSET 0x408 /* Interrupt request 2 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST3_OFFSET 0x40c /* Interrupt request 3 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST4_OFFSET 0x410 /* Interrupt request 4 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST5_OFFSET 0x414 /* Interrupt request 5 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST6_OFFSET 0x418 /* Interrupt request 6 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST7_OFFSET 0x41c /* Interrupt request 7 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST8_OFFSET 0x420 /* Interrupt request 8 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST9_OFFSET 0x424 /* Interrupt request 9 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST10_OFFSET 0x428 /* Interrupt request 10 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST11_OFFSET 0x42c /* Interrupt request 11 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST12_OFFSET 0x430 /* Interrupt request 12 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST13_OFFSET 0x434 /* Interrupt request 13 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST14_OFFSET 0x438 /* Interrupt request 14 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST15_OFFSET 0x43c /* Interrupt request 15 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST16_OFFSET 0x440 /* Interrupt request 16 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST17_OFFSET 0x444 /* Interrupt request 17 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST18_OFFSET 0x448 /* Interrupt request 18 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST19_OFFSET 0x44c /* Interrupt request 19 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST20_OFFSET 0x450 /* Interrupt request 20 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST21_OFFSET 0x454 /* Interrupt request 21 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST22_OFFSET 0x458 /* Interrupt request 22 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST23_OFFSET 0x45c /* Interrupt request 23 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST24_OFFSET 0x460 /* Interrupt request 24 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST25_OFFSET 0x464 /* Interrupt request 25 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST26_OFFSET 0x468 /* Interrupt request 26 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST27_OFFSET 0x46c /* Interrupt request 27 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST28_OFFSET 0x470 /* Interrupt request 28 configuration */
|
|
||||||
#define LPC313X_INTC_REQUEST29_OFFSET 0x474 /* Interrupt request 29 configuration */
|
|
||||||
|
|
||||||
/* INTC register (virtual) addresses ************************************************************/
|
|
||||||
|
|
||||||
#define LPC313X_INTC_PRIORITYMASK0 (LPC313X_INTC_VBASE+LPC313X_INTC_PRIORITYMASK0_OFFSET)
|
|
||||||
#define LPC313X_INTC_PRIORITYMASK1 (LPC313X_INTC_VBASE+LPC313X_INTC_PRIORITYMASK1_OFFSET)
|
|
||||||
#define LPC313X_INTC_VECTOR0 (LPC313X_INTC_VBASE+LPC313X_INTC_VECTOR0_OFFSET)
|
|
||||||
#define LPC313X_INTC_VECTOR1 (LPC313X_INTC_VBASE+LPC313X_INTC_VECTOR1_OFFSET)
|
|
||||||
#define LPC313X_INTC_PENDING (LPC313X_INTC_VBASE+LPC313X_INTC_PENDING_OFFSET)
|
|
||||||
#define LPC313X_INTC_FEATURES (LPC313X_INTC_VBASE+LPC313X_INTC_FEATURES_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST(n) (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST_OFFSET(n))
|
|
||||||
#define LPC313X_INTC_REQUEST1 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST1_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST2 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST2_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST3 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST3_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST4 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST4_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST5 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST5_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST6 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST6_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST7 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST7_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST8 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST8_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST9 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST9_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST10 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST10_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST11 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST11_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST12 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST12_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST13 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST13_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST14 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST14_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST15 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST15_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST16 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST16_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST17 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST17_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST18 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST18_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST19 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST19_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST20 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST20_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST21 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST21_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST22 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST22_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST23 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST23_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST24 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST24_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST25 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST25_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST26 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST26_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST27 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST27_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST28 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST28_OFFSET)
|
|
||||||
#define LPC313X_INTC_REQUEST29 (LPC313X_INTC_VBASE+LPC313X_INTC_REQUEST29_OFFSET)
|
|
||||||
|
|
||||||
/* INTC register bit definitions ****************************************************************/
|
|
||||||
|
|
||||||
/* Interrupt priority mask register (INT_PRIORITYMASK0 address 0x60000000 and
|
|
||||||
* INTC_PRIORITYMASK1 address 0x60000004)
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define INTC_PRIORITYMASK_PRIOLIMIT_SHIFT (0) /* Bits 0-7: Priority threshold for interrupts */
|
|
||||||
#define INTC_PRIORITYMASK_PRIOLIMIT_MASK (255 << INTC_PRIORITYMASK_PRIOLIMIT_MASK)
|
|
||||||
|
|
||||||
/* Interrupt vector registers (INTC_VECTOR0 address 0x60000100 and INTC_VECTOR1 address
|
|
||||||
* 0x60000104)
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define INTC_VECTOR_TABLEADDR_SHIFT (11) /* Bits 11-31: Table start address */
|
|
||||||
#define INTC_VECTOR_TABLEADDR_MASK (0x001fffff << INTC_VECTOR_TABLEADDR_SHIFT)
|
|
||||||
#define INTC_VECTOR_INDEX_SHIFT (3) /* Bits 3-10: IRQ number of interrupt */
|
|
||||||
#define INTC_VECTOR_INDEX_MASK (255 << INTC_VECTOR_INDEX_SHIFT)
|
|
||||||
|
|
||||||
/* Interrupt pending register (INT_PENDING1_31, address 0x60000200) */
|
|
||||||
|
|
||||||
#define INTC_PENDING_SHIFT (1) /* Bits 1-29: Pending interrupt request */
|
|
||||||
#define INTC_PENDING_MASK (0x1fffffff << INTC_PENDING_SHIFT)
|
|
||||||
|
|
||||||
/* Interrupt controller features register (INT_FEATURES, address 0x60000300) */
|
|
||||||
|
|
||||||
#define INTC_FEATURES_T_SHIFT (16) /* Bits 16-21: Number interrupt targets supported (+1) */
|
|
||||||
#define INTC_FEATURES_T_MASK (63 << INTC_FEATURES_T_SHIFT)
|
|
||||||
#define INTC_FEATURES_P_SHIFT (8) /* Bits 8-15: Number priority levels supported */
|
|
||||||
#define INTC_FEATURES_P_MASK (255 << INTC_FEATURES_P_SHIFT)
|
|
||||||
#define INTC_FEATURES_N_SHIFT (0) /* Bits 0-7: Number interrupt request inputs */
|
|
||||||
#define INTC_FEATURES_N_MASK (255 << INTC_FEATURES_N_SHIFT)
|
|
||||||
|
|
||||||
/* Interrupt request registers (INT_REQUEST1 address 0x60000404 to INTC_REQUEST29 address
|
|
||||||
* 0x60000474)
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define INTC_REQUEST_PENDING (1 << 31) /* Bit 31: Pending interrupt request */
|
|
||||||
#define INTC_REQUEST_SETSWINT (1 << 30) /* Bit 30: Set software interrupt request */
|
|
||||||
#define INTC_REQUEST_CLRSWINT (1 << 29) /* Bit 29: Clear software interrupt request */
|
|
||||||
#define INTC_REQUEST_WEPRIO (1 << 28) /* Bit 28: Write Enable PRIORITY_LEVEL */
|
|
||||||
#define INTC_REQUEST_WETARGET (1 << 27) /* Bit 27: Write Enable TARGET */
|
|
||||||
#define INTC_REQUEST_WEENABLE (1 << 26) /* Bit 26: Write Enable ENABLE */
|
|
||||||
#define INTC_REQUEST_WEACTLOW (1 << 25) /* Bit 25: Write Enable ACTIVE_LOW */
|
|
||||||
#define INTC_REQUEST_ACTLOW (1 << 17) /* Bit 17: Active Low */
|
|
||||||
#define INTC_REQUEST_ENABLE (1 << 16) /* Bit 16: Enable interrupt request */
|
|
||||||
#define INTC_REQUEST_TARGET_SHIFT (8) /* Bits 8-13: Interrupt target */
|
|
||||||
#define INTC_REQUEST_TARGET_MASK (63 << INTC_REQUEST_TARGET_SHIFT)
|
|
||||||
# define INTC_REQUEST_TARGET_IRQ (INTC_REQUEST_WETARGET | (0 << INTC_REQUEST_TARGET_SHIFT)) /* Proc interrupt request 0: IRQ */
|
|
||||||
# define INTC_REQUEST_TARGET_FIQ (INTC_REQUEST_WETARGET | (1 << INTC_REQUEST_TARGET_SHIFT)) /* Proc interrupt request 1: FIQ */
|
|
||||||
#define INTC_REQUEST_PRIOLEVEL_SHIFT (0) /* Bits 0-7: Priority level */
|
|
||||||
#define INTC_REQUEST_PRIOLEVEL_MASK (255 << INTC_REQUEST_PRIOLEVEL_SHIFT)
|
|
||||||
# define INTC_REQUEST_PRIOLEVEL(n) (((n) << INTC_REQUEST_PRIOLEVEL_SHIFT) & INTC_REQUEST_PRIOLEVEL_MASK)
|
|
||||||
|
|
||||||
/************************************************************************************************
|
|
||||||
* Public Types
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
/************************************************************************************************
|
|
||||||
* Public Data
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
/************************************************************************************************
|
|
||||||
* Public Functions
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
#endif /* __ARCH_ARM_SRC_LPC313X_INTC_H */
|
|
||||||
@@ -1,357 +0,0 @@
|
|||||||
/************************************************************************************************
|
|
||||||
* arch/arm/src/lpc313x/lpc313x_ioconfig.h
|
|
||||||
*
|
|
||||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions
|
|
||||||
* are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in
|
|
||||||
* the documentation and/or other materials provided with the
|
|
||||||
* distribution.
|
|
||||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
|
||||||
* used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
|
||||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
|
||||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
|
||||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
|
||||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
|
||||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
||||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|
||||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
#ifndef __ARCH_ARM_SRC_LPC313X_IOCONFIG_H
|
|
||||||
#define __ARCH_ARM_SRC_LPC313X_IOCONFIG_H
|
|
||||||
|
|
||||||
/************************************************************************************************
|
|
||||||
* Included Files
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
#include <nuttx/config.h>
|
|
||||||
#include "lpc313x_memorymap.h"
|
|
||||||
|
|
||||||
/************************************************************************************************
|
|
||||||
* Pre-processor Definitions
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
/* IOCONFIG register base address offset into the APB0 domain ***********************************/
|
|
||||||
|
|
||||||
#define LPC313X_IOCONFIG_VBASE (LPC313X_APB0_VADDR+LPC313X_APB0_IOCONFIG_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_PBASE (LPC313X_APB0_PADDR+LPC313X_APB0_IOCONFIG_OFFSET)
|
|
||||||
|
|
||||||
/* IOCONFIG function block offsets (with respect to the IOCONFIG register base address) *********/
|
|
||||||
|
|
||||||
#define LPC313X_IOCONFIG_EBIMCI_OFFSET 0x000 /* First set of 32 multiplexed pads */
|
|
||||||
#define LPC313X_IOCONFIG_EBII2STX0_OFFSET 0X040 /* Second set of 32 of multiplexed pads */
|
|
||||||
#define LPC313X_IOCONFIG_CGU_OFFSET 0X080 /* Clock Generation Unit function block */
|
|
||||||
#define LPC313X_IOCONFIG_I2SRX0_OFFSET 0x0c0 /* I2SRX function block 0 */
|
|
||||||
#define LPC313X_IOCONFIG_I2SRX1_OFFSET 0x100 /* I2SRX function block 1 */
|
|
||||||
#define LPC313X_IOCONFIG_I2STX1_OFFSET 0x140 /* I2STX function block 1 */
|
|
||||||
#define LPC313X_IOCONFIG_EBI_OFFSET 0x180 /* External Bus Interface function block */
|
|
||||||
#define LPC313X_IOCONFIG_GPIO_OFFSET 0x1c0 /* General purpose IO */
|
|
||||||
#define LPC313X_IOCONFIG_I2C1_OFFSET 0x200 /* I2C function block */
|
|
||||||
#define LPC313X_IOCONFIG_SPI_OFFSET 0x240 /* SPI function block */
|
|
||||||
#define LPC313X_IOCONFIG_NAND_OFFSET 0x280 /* NANDFLASH function block */
|
|
||||||
#define LPC313X_IOCONFIG_PWM_OFFSET 0x2c0 /* PWM function block */
|
|
||||||
#define LPC313X_IOCONFIG_UART_OFFSET 0x300 /* UART function block */
|
|
||||||
|
|
||||||
/* IOCONFIG register offsets (with respect to any funcion block base address) *******************/
|
|
||||||
|
|
||||||
#define LPC313X_IOCONFIG_PINS_OFFSET 0x000 /* WR: RD: Input pin state */
|
|
||||||
/* 0x004-0x00c: Reserved */
|
|
||||||
#define LPC313X_IOCONFIG_MODE0_OFFSET 0x010 /* WR:Load RD: */
|
|
||||||
#define LPC313X_IOCONFIG_MODE0SET_OFFSET 0x014 /* WR:Set Bits RD:Read Mode 0 */
|
|
||||||
#define LPC313X_IOCONFIG_MODE0RESET_OFFSET 0x018 /* WR:Reset Bits RD: */
|
|
||||||
/* 0x01c: Reserved */
|
|
||||||
#define LPC313X_IOCONFIG_MODE1_OFFSET 0x020 /* WR:Load RD: */
|
|
||||||
#define LPC313X_IOCONFIG_MODE1SET_OFFSET 0x024 /* WR:Set Bits RD:Read Mode 1 */
|
|
||||||
#define LPC313X_IOCONFIG_MODE1RESET_OFFSET 0x028 /* WR:Reset Bits RD: */
|
|
||||||
/* 0x02c-0x3c: Reserved */
|
|
||||||
|
|
||||||
/* IOCONFIG function block (virtual) base addresses *********************************************/
|
|
||||||
|
|
||||||
#define LPC313X_IOCONFIG_EBIMCI (LPC313X_IOCONFIG_VBASE+LPC313X_IOCONFIG_EBIMCI_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_EBII2STX0 (LPC313X_IOCONFIG_VBASE+LPC313X_IOCONFIG_EBII2STX0_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_CGU (LPC313X_IOCONFIG_VBASE+LPC313X_IOCONFIG_CGU_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2SRX0 (LPC313X_IOCONFIG_VBASE+LPC313X_IOCONFIG_I2SRX0_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2SRX1 (LPC313X_IOCONFIG_VBASE+LPC313X_IOCONFIG_I2SRX1_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2STX1 (LPC313X_IOCONFIG_VBASE+LPC313X_IOCONFIG_I2STX1_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_EBI (LPC313X_IOCONFIG_VBASE+LPC313X_IOCONFIG_EBI_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_GPIO (LPC313X_IOCONFIG_VBASE+LPC313X_IOCONFIG_GPIO_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2C1 (LPC313X_IOCONFIG_VBASE+LPC313X_IOCONFIG_I2C1_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_SPI (LPC313X_IOCONFIG_VBASE+LPC313X_IOCONFIG_SPI_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_NAND (LPC313X_IOCONFIG_VBASE+LPC313X_IOCONFIG_NAND_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_PWM (LPC313X_IOCONFIG_VBASE+LPC313X_IOCONFIG_PWM_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_UART (LPC313X_IOCONFIG_VBASE+LPC313X_IOCONFIG_UART_OFFSET)
|
|
||||||
|
|
||||||
/* IOCONFIG register (virtual) addresses ********************************************************/
|
|
||||||
|
|
||||||
#define LPC313X_IOCONFIG_EBIMCI_PINS (LPC313X_IOCONFIG_EBIMCI+LPC313X_IOCONFIG_PINS_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_EBIMCI_MODE0 (LPC313X_IOCONFIG_EBIMCI+LPC313X_IOCONFIG_MODE0_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_EBIMCI_MODE0SET (LPC313X_IOCONFIG_EBIMCI+LPC313X_IOCONFIG_MODE0SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_EBIMCI_MODE0RESET (LPC313X_IOCONFIG_EBIMCI+LPC313X_IOCONFIG_MODE0RESET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_EBIMCI_MODE1 (LPC313X_IOCONFIG_EBIMCI+LPC313X_IOCONFIG_MODE1_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_EBIMCI_MODE1SET (LPC313X_IOCONFIG_EBIMCI+LPC313X_IOCONFIG_MODE1SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_EBIMCI_MODE1RESET (LPC313X_IOCONFIG_EBIMCI+LPC313X_IOCONFIG_MODE1RESET_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_IOCONFIG_EBII2STX0_PINS (LPC313X_IOCONFIG_EBII2STX0+LPC313X_IOCONFIG_PINS_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_EBII2STX0_MODE0 (LPC313X_IOCONFIG_EBII2STX0+LPC313X_IOCONFIG_MODE0_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_EBII2STX0_MODE0SET (LPC313X_IOCONFIG_EBII2STX0+LPC313X_IOCONFIG_MODE0SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_EBII2STX0_MODE0RESET (LPC313X_IOCONFIG_EBII2STX0+LPC313X_IOCONFIG_MODE0RESET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_EBII2STX0_MODE1 (LPC313X_IOCONFIG_EBII2STX0+LPC313X_IOCONFIG_MODE1_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_EBII2STX0_MODE1SET (LPC313X_IOCONFIG_EBII2STX0+LPC313X_IOCONFIG_MODE1SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_EBII2STX0_MODE1RESET (LPC313X_IOCONFIG_EBII2STX0+LPC313X_IOCONFIG_MODE1RESET_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_IOCONFIG_CGU_PINS (LPC313X_IOCONFIG_CGU+LPC313X_IOCONFIG_PINS_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_CGU_MODE0 (LPC313X_IOCONFIG_CGU+LPC313X_IOCONFIG_MODE0_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_CGU_MODE0SET (LPC313X_IOCONFIG_CGU+LPC313X_IOCONFIG_MODE0SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_CGU_MODE0RESET (LPC313X_IOCONFIG_CGU+LPC313X_IOCONFIG_MODE0RESET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_CGU_MODE1 (LPC313X_IOCONFIG_CGU+LPC313X_IOCONFIG_MODE1_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_CGU_MODE1SET (LPC313X_IOCONFIG_CGU+LPC313X_IOCONFIG_MODE1SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_CGU_MODE1RESET (LPC313X_IOCONFIG_CGU+LPC313X_IOCONFIG_MODE1RESET_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_IOCONFIG_I2SRX0_PINS (LPC313X_IOCONFIG_I2SRX0+LPC313X_IOCONFIG_PINS_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2SRX0_MODE0 (LPC313X_IOCONFIG_I2SRX0+LPC313X_IOCONFIG_MODE0_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2SRX0_MODE0SET (LPC313X_IOCONFIG_I2SRX0+LPC313X_IOCONFIG_MODE0SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2SRX0_MODE0RESET (LPC313X_IOCONFIG_I2SRX0+LPC313X_IOCONFIG_MODE0RESET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2SRX0_MODE1 (LPC313X_IOCONFIG_I2SRX0+LPC313X_IOCONFIG_MODE1_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2SRX0_MODE1SET (LPC313X_IOCONFIG_I2SRX0+LPC313X_IOCONFIG_MODE1SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2SRX0_MODE1RESET (LPC313X_IOCONFIG_I2SRX0+LPC313X_IOCONFIG_MODE1RESET_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_IOCONFIG_I2SRX1_PINS (LPC313X_IOCONFIG_I2SRX1+LPC313X_IOCONFIG_PINS_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2SRX1_MODE0 (LPC313X_IOCONFIG_I2SRX1+LPC313X_IOCONFIG_MODE0_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2SRX1_MODE0SET (LPC313X_IOCONFIG_I2SRX1+LPC313X_IOCONFIG_MODE0SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2SRX1_MODE0RESET (LPC313X_IOCONFIG_I2SRX1+LPC313X_IOCONFIG_MODE0RESET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2SRX1_MODE1 (LPC313X_IOCONFIG_I2SRX1+LPC313X_IOCONFIG_MODE1_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2SRX1_MODE1SET (LPC313X_IOCONFIG_I2SRX1+LPC313X_IOCONFIG_MODE1SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2SRX1_MODE1RESET (LPC313X_IOCONFIG_I2SRX1+LPC313X_IOCONFIG_MODE1RESET_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_IOCONFIG_I2STX1_PINS (LPC313X_IOCONFIG_I2STX1+LPC313X_IOCONFIG_PINS_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2STX1_MODE0 (LPC313X_IOCONFIG_I2STX1+LPC313X_IOCONFIG_MODE0_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2STX1_MODE0SET (LPC313X_IOCONFIG_I2STX1+LPC313X_IOCONFIG_MODE0SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2STX1_MODE0RESET (LPC313X_IOCONFIG_I2STX1+LPC313X_IOCONFIG_MODE0RESET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2STX1_MODE1 (LPC313X_IOCONFIG_I2STX1+LPC313X_IOCONFIG_MODE1_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2STX1_MODE1SET (LPC313X_IOCONFIG_I2STX1+LPC313X_IOCONFIG_MODE1SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2STX1_MODE1RESET (LPC313X_IOCONFIG_I2STX1+LPC313X_IOCONFIG_MODE1RESET_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_IOCONFIG_EBI_PINS (LPC313X_IOCONFIG_EBI+LPC313X_IOCONFIG_PINS_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_EBI_MODE0 (LPC313X_IOCONFIG_EBI+LPC313X_IOCONFIG_MODE0_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_EBI_MODE0SET (LPC313X_IOCONFIG_EBI+LPC313X_IOCONFIG_MODE0SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_EBI_MODE0RESET (LPC313X_IOCONFIG_EBI+LPC313X_IOCONFIG_MODE0RESET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_EBI_MODE1 (LPC313X_IOCONFIG_EBI+LPC313X_IOCONFIG_MODE1_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_EBI_MODE1SET (LPC313X_IOCONFIG_EBI+LPC313X_IOCONFIG_MODE1SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_EBI_MODE1RESET (LPC313X_IOCONFIG_EBI+LPC313X_IOCONFIG_MODE1RESET_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_IOCONFIG_GPIO_PINS (LPC313X_IOCONFIG_GPIO+LPC313X_IOCONFIG_PINS_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_GPIO_MODE0 (LPC313X_IOCONFIG_GPIO+LPC313X_IOCONFIG_MODE0_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_GPIO_MODE0SET (LPC313X_IOCONFIG_GPIO+LPC313X_IOCONFIG_MODE0SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_GPIO_MODE0RESET (LPC313X_IOCONFIG_GPIO+LPC313X_IOCONFIG_MODE0RESET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_GPIO_MODE1 (LPC313X_IOCONFIG_GPIO+LPC313X_IOCONFIG_MODE1_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_GPIO_MODE1SET (LPC313X_IOCONFIG_GPIO+LPC313X_IOCONFIG_MODE1SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_GPIO_MODE1RESET (LPC313X_IOCONFIG_GPIO+LPC313X_IOCONFIG_MODE1RESET_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_IOCONFIG_I2C1_PINS (LPC313X_IOCONFIG_I2C1+LPC313X_IOCONFIG_PINS_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2C1_MODE0 (LPC313X_IOCONFIG_I2C1+LPC313X_IOCONFIG_MODE0_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2C1_MODE0SET (LPC313X_IOCONFIG_I2C1+LPC313X_IOCONFIG_MODE0SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2C1_MODE0RESET (LPC313X_IOCONFIG_I2C1+LPC313X_IOCONFIG_MODE0RESET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2C1_MODE1 (LPC313X_IOCONFIG_I2C1+LPC313X_IOCONFIG_MODE1_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2C1_MODE1SET (LPC313X_IOCONFIG_I2C1+LPC313X_IOCONFIG_MODE1SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_I2C1_MODE1RESET (LPC313X_IOCONFIG_I2C1+LPC313X_IOCONFIG_MODE1RESET_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_IOCONFIG_SPI_PINS (LPC313X_IOCONFIG_SPI+LPC313X_IOCONFIG_PINS_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_SPI_MODE0 (LPC313X_IOCONFIG_SPI+LPC313X_IOCONFIG_MODE0_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_SPI_MODE0SET (LPC313X_IOCONFIG_SPI+LPC313X_IOCONFIG_MODE0SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_SPI_MODE0RESET (LPC313X_IOCONFIG_SPI+LPC313X_IOCONFIG_MODE0RESET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_SPI_MODE1 (LPC313X_IOCONFIG_SPI+LPC313X_IOCONFIG_MODE1_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_SPI_MODE1SET (LPC313X_IOCONFIG_SPI+LPC313X_IOCONFIG_MODE1SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_SPI_MODE1RESET (LPC313X_IOCONFIG_SPI+LPC313X_IOCONFIG_MODE1RESET_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_IOCONFIG_NAND_PINS (LPC313X_IOCONFIG_NAND+LPC313X_IOCONFIG_PINS_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_NAND_MODE0 (LPC313X_IOCONFIG_NAND+LPC313X_IOCONFIG_MODE0_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_NAND_MODE0SET (LPC313X_IOCONFIG_NAND+LPC313X_IOCONFIG_MODE0SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_NAND_MODE0RESET (LPC313X_IOCONFIG_NAND+LPC313X_IOCONFIG_MODE0RESET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_NAND_MODE1 (LPC313X_IOCONFIG_NAND+LPC313X_IOCONFIG_MODE1_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_NAND_MODE1SET (LPC313X_IOCONFIG_NAND+LPC313X_IOCONFIG_MODE1SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_NAND_MODE1RESET (LPC313X_IOCONFIG_NAND+LPC313X_IOCONFIG_MODE1RESET_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_IOCONFIG_PWM_PINS (LPC313X_IOCONFIG_PWM+LPC313X_IOCONFIG_PINS_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_PWM_MODE0 (LPC313X_IOCONFIG_PWM+LPC313X_IOCONFIG_MODE0_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_PWM_MODE0SET (LPC313X_IOCONFIG_PWM+LPC313X_IOCONFIG_MODE0SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_PWM_MODE0RESET (LPC313X_IOCONFIG_PWM+LPC313X_IOCONFIG_MODE0RESET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_PWM_MODE1 (LPC313X_IOCONFIG_PWM+LPC313X_IOCONFIG_MODE1_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_PWM_MODE1SET (LPC313X_IOCONFIG_PWM+LPC313X_IOCONFIG_MODE1SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_PWM_MODE1RESET (LPC313X_IOCONFIG_PWM+LPC313X_IOCONFIG_MODE1RESET_OFFSET)
|
|
||||||
|
|
||||||
#define LPC313X_IOCONFIG_UART_PINS (LPC313X_IOCONFIG_UART+LPC313X_IOCONFIG_PINS_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_UART_MODE0 (LPC313X_IOCONFIG_UART+LPC313X_IOCONFIG_MODE0_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_UART_MODE0SET (LPC313X_IOCONFIG_UART+LPC313X_IOCONFIG_MODE0SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_UART_MODE0RESET (LPC313X_IOCONFIG_UART+LPC313X_IOCONFIG_MODE0RESET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_UART_MODE1 (LPC313X_IOCONFIG_UART+LPC313X_IOCONFIG_MODE1_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_UART_MODE1SET (LPC313X_IOCONFIG_UART+LPC313X_IOCONFIG_MODE1SET_OFFSET)
|
|
||||||
#define LPC313X_IOCONFIG_UART_MODE1RESET (LPC313X_IOCONFIG_UART+LPC313X_IOCONFIG_MODE1RESET_OFFSET)
|
|
||||||
|
|
||||||
/* IOCONFIG register bit definitions ************************************************************/
|
|
||||||
/* EBI_MCI register bit definitions (all registers) */
|
|
||||||
|
|
||||||
|
|
||||||
#define IOCONFIG_EBIMCI_MGPIO9 (1 << 0)
|
|
||||||
#define IOCONFIG_EBIMCI_MGPIO6 (1 << 1)
|
|
||||||
#define IOCONFIG_EBIMCI_MLCDDB7 (1 << 2)
|
|
||||||
#define IOCONFIG_EBIMCI_MLCDDB4 (1 << 3)
|
|
||||||
#define IOCONFIG_EBIMCI_MLCDDB2 (1 << 4)
|
|
||||||
#define IOCONFIG_EBIMCI_MNANDRYBN0 (1 << 5)
|
|
||||||
#define IOCONFIG_EBIMCI_MI2STXCLK0 (1 << 6)
|
|
||||||
#define IOCONFIG_EBIMCI_MI2STXBCK0 (1 << 7)
|
|
||||||
#define IOCONFIG_EBIMCI_EBIA1CLE (1 << 8)
|
|
||||||
#define IOCONFIG_EBIMCI_EBINCASBLOUT0 (1 << 9)
|
|
||||||
#define IOCONFIG_EBIMCI_MLCDDB0 (1 << 10)
|
|
||||||
#define IOCONFIG_EBIMCI_EBIDQM0NOE (1 << 11)
|
|
||||||
#define IOCONFIG_EBIMCI_MLCDCSB (1 << 12)
|
|
||||||
#define IOCONFIG_EBIMCI_MLCDDB1 (1 << 13)
|
|
||||||
#define IOCONFIG_EBIMCI_MLCDERD (1 << 14)
|
|
||||||
#define IOCONFIG_EBIMCI_MLCDRS (1 << 15)
|
|
||||||
#define IOCONFIG_EBIMCI_MLCDRWWR (1 << 16)
|
|
||||||
#define IOCONFIG_EBIMCI_MLCDDB3 (1 << 17)
|
|
||||||
#define IOCONFIG_EBIMCI_MLCDDB5 (1 << 18)
|
|
||||||
#define IOCONFIG_EBIMCI_MLCDDB6 (1 << 19)
|
|
||||||
#define IOCONFIG_EBIMCI_MLCDDB8 (1 << 20)
|
|
||||||
#define IOCONFIG_EBIMCI_MLCDDB9 (1 << 21)
|
|
||||||
#define IOCONFIG_EBIMCI_MLCDDB10 (1 << 22)
|
|
||||||
#define IOCONFIG_EBIMCI_MLCDDB11 (1 << 23)
|
|
||||||
#define IOCONFIG_EBIMCI_MLCDDB12 (1 << 24)
|
|
||||||
#define IOCONFIG_EBIMCI_MLCDDB13 (1 << 25)
|
|
||||||
#define IOCONFIG_EBIMCI_MLCDDB14 (1 << 26)
|
|
||||||
#define IOCONFIG_EBIMCI_MLCDDB15 (1 << 27)
|
|
||||||
#define IOCONFIG_EBIMCI_MGPIO5 (1 << 28)
|
|
||||||
#define IOCONFIG_EBIMCI_MGPIO7 (1 << 29)
|
|
||||||
#define IOCONFIG_EBIMCI_MGPIO8 (1 << 30)
|
|
||||||
#define IOCONFIG_EBIMCI_MGPIO10 (1 << 31)
|
|
||||||
|
|
||||||
/* EBI_I2STX_0 register bit definitions (all registers) */
|
|
||||||
|
|
||||||
#define IOCONFIG_EBII2STX0_MNANDRYBN1 (1 << 0)
|
|
||||||
#define IOCONFIG_EBII2STX0_MNANDRYBN2 (1 << 1)
|
|
||||||
#define IOCONFIG_EBII2STX0_MNANDRYBN3 (1 << 2)
|
|
||||||
#define IOCONFIG_EBII2STX0_MUARTCTSN (1 << 3)
|
|
||||||
#define IOCONFIG_EBII2STX0_MUARTRTSN (1 << 4)
|
|
||||||
#define IOCONFIG_EBII2STX0_MI2STXDATA0 (1 << 5)
|
|
||||||
#define IOCONFIG_EBII2STX0_MI2STXWS0 (1 << 6)
|
|
||||||
#define IOCONFIG_EBII2STX0_EBINRASBLOUT1 (1 << 7)
|
|
||||||
#define IOCONFIG_EBII2STX0_EBIA0ALE (1 << 8)
|
|
||||||
#define IOCONFIG_EBII2STX0_EBINWE (1 << 9)
|
|
||||||
|
|
||||||
/* CGU register bit definitions (all registers) */
|
|
||||||
|
|
||||||
#define IOCONFIG_CGU_SYSCLKO (1 << 0)
|
|
||||||
|
|
||||||
/* I2SRX_0 register bit definitions (all registers) */
|
|
||||||
|
|
||||||
#define IOCONFIG_I2SRX0_BCK (1 << 0)
|
|
||||||
#define IOCONFIG_I2SRX0_DATA (1 << 1)
|
|
||||||
#define IOCONFIG_I2SRX0_WS (1 << 2)
|
|
||||||
|
|
||||||
/* I2SRX_1 register bit definitions (all registers) */
|
|
||||||
|
|
||||||
#define IOCONFIG_I2SRX1_DATA (1 << 0)
|
|
||||||
#define IOCONFIG_I2SRX1_BCK (1 << 1)
|
|
||||||
#define IOCONFIG_I2SRX1_WS (1 << 2)
|
|
||||||
|
|
||||||
/* I2STX_1 register bit definitions (all registers) */
|
|
||||||
|
|
||||||
#define IOCONFIG_I2STX1_DATA (1 << 0)
|
|
||||||
#define IOCONFIG_I2STX1_BCK (1 << 1)
|
|
||||||
#define IOCONFIG_I2STX1_WS (1 << 2)
|
|
||||||
#define IOCONFIG_I2STX1_256FSO (1 << 3)
|
|
||||||
|
|
||||||
/* EBI register bit definitions (all registers) */
|
|
||||||
|
|
||||||
#define IOCONFIG_EBI_D9 (1 << 0)
|
|
||||||
#define IOCONFIG_EBI_D10 (1 << 1)
|
|
||||||
#define IOCONFIG_EBI_D11 (1 << 2)
|
|
||||||
#define IOCONFIG_EBI_D12 (1 << 3)
|
|
||||||
#define IOCONFIG_EBI_D13 (1 << 4)
|
|
||||||
#define IOCONFIG_EBI_D14 (1 << 5)
|
|
||||||
#define IOCONFIG_EBI_D4 (1 << 6)
|
|
||||||
#define IOCONFIG_EBI_D0 (1 << 7)
|
|
||||||
#define IOCONFIG_EBI_D1 (1 << 8)
|
|
||||||
#define IOCONFIG_EBI_D2 (1 << 9)
|
|
||||||
#define IOCONFIG_EBI_D3 (1 << 10)
|
|
||||||
#define IOCONFIG_EBI_D5 (1 << 11)
|
|
||||||
#define IOCONFIG_EBI_D6 (1 << 12)
|
|
||||||
#define IOCONFIG_EBI_D7 (1 << 13)
|
|
||||||
#define IOCONFIG_EBI_D8 (1 << 14)
|
|
||||||
#define IOCONFIG_EBI_D15 (1 << 15)
|
|
||||||
|
|
||||||
/* GPIO register bit definitions (all registers) */
|
|
||||||
|
|
||||||
#define IOCONFIG_GPIO_GPIO1 (1 << 0)
|
|
||||||
#define IOCONFIG_GPIO_GPIO0 (1 << 1)
|
|
||||||
#define IOCONFIG_GPIO_GPIO2 (1 << 2)
|
|
||||||
#define IOCONFIG_GPIO_GPIO3 (1 << 3)
|
|
||||||
#define IOCONFIG_GPIO_GPIO4 (1 << 4)
|
|
||||||
#define IOCONFIG_GPIO_GPIO11 (1 << 5)
|
|
||||||
#define IOCONFIG_GPIO_GPIO12 (1 << 6)
|
|
||||||
#define IOCONFIG_GPIO_GPIO13 (1 << 7)
|
|
||||||
#define IOCONFIG_GPIO_GPIO14 (1 << 8)
|
|
||||||
#define IOCONFIG_GPIO_GPIO15 (1 << 9)
|
|
||||||
#define IOCONFIG_GPIO_GPIO16 (1 << 10)
|
|
||||||
#define IOCONFIG_GPIO_GPIO17 (1 << 11)
|
|
||||||
#define IOCONFIG_GPIO_GPIO18 (1 << 12)
|
|
||||||
#define IOCONFIG_GPIO_GPIO19 (1 << 13)
|
|
||||||
#define IOCONFIG_GPIO_GPIO20 (1 << 14)
|
|
||||||
|
|
||||||
/* I2C1 register bit definitions (all registers) */
|
|
||||||
|
|
||||||
#define IOCONFIG_I2C1_SDA1 (1 << 0)
|
|
||||||
#define IOCONFIG_I2C1_SCL1 (1 << 1)
|
|
||||||
|
|
||||||
/* SPI register bit definitions (all registers) */
|
|
||||||
|
|
||||||
#define IOCONFIG_SPI_MISO (1 << 0)
|
|
||||||
#define IOCONFIG_SPI_MOSI (1 << 1)
|
|
||||||
#define IOCONFIG_SPI_CSIN (1 << 2)
|
|
||||||
#define IOCONFIG_SPI_SCK (1 << 3)
|
|
||||||
#define IOCONFIG_SPI_CSOUT0 (1 << 4)
|
|
||||||
|
|
||||||
/* NAND register bit definitions (all registers) */
|
|
||||||
|
|
||||||
#define IOCONFIG_NAND_NCS3 (1 << 0)
|
|
||||||
#define IOCONFIG_NAND_NCS0 (1 << 1)
|
|
||||||
#define IOCONFIG_NAND_NCS1 (1 << 2)
|
|
||||||
#define IOCONFIG_NAND_NCS2 (1 << 3)
|
|
||||||
|
|
||||||
/* PWM register bit definitions (all registers) */
|
|
||||||
|
|
||||||
#define IOCONFIG_PWM_DATA (1 << 0)
|
|
||||||
|
|
||||||
/* UART register bit definitions (all registers) */
|
|
||||||
|
|
||||||
#define IOCONFIG_UART_RXD (1 << 0)
|
|
||||||
#define IOCONFIG_UART_TXD (1 << 1)
|
|
||||||
|
|
||||||
/************************************************************************************************
|
|
||||||
* Public Types
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
/************************************************************************************************
|
|
||||||
* Public Data
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
/************************************************************************************************
|
|
||||||
* Public Functions
|
|
||||||
************************************************************************************************/
|
|
||||||
|
|
||||||
#endif /* __ARCH_ARM_SRC_LPC313X_IOCONFIG_H */
|
|
||||||
@@ -1,414 +0,0 @@
|
|||||||
/************************************************************************************
|
|
||||||
* arch/arm/src/lpc313x/chip.h
|
|
||||||
*
|
|
||||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions
|
|
||||||
* are met:
|
|
||||||
*
|
|
||||||
* 1. Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* 2. Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in
|
|
||||||
* the documentation and/or other materials provided with the
|
|
||||||
* distribution.
|
|
||||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
|
||||||
* used to endorse or promote products derived from this software
|
|
||||||
* without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
||||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
||||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
|
||||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
|
||||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
||||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
|
||||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
|
||||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
|
||||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
||||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|
||||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
||||||
* POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
*
|
|
||||||
************************************************************************************/
|
|
||||||
|
|
||||||
#ifndef __ARCH_ARM_SRC_LPC313X_MEMORYMAP_H
|
|
||||||
#define __ARCH_ARM_SRC_LPC313X_MEMORYMAP_H
|
|
||||||
|
|
||||||
/************************************************************************************
|
|
||||||
* Included Files
|
|
||||||
************************************************************************************/
|
|
||||||
|
|
||||||
#include <nuttx/config.h>
|
|
||||||
|
|
||||||
/************************************************************************************
|
|
||||||
* Pre-processor Definitions
|
|
||||||
************************************************************************************/
|
|
||||||
|
|
||||||
/* LPC313X Physical (unmapped) Memory Map */
|
|
||||||
|
|
||||||
#define LPC313X_FIRST_PSECTION 0x00000000 /* Beginning of the physical address space */
|
|
||||||
#define LPC313X_SHADOWSPACE_PSECTION 0x00000000 /* 0x00000000-0x00000fff: Shadow Area 4Kb */
|
|
||||||
/* 0x00001000-0xff027fff: Reserved */
|
|
||||||
#define LPC313X_INTSRAM_PSECTION 0x11028000 /* Internal SRAM 0+1 192Kb */
|
|
||||||
# define LPC313X_INTSRAM0_PADDR 0x11028000 /* 0x11028000-0x1103ffff: Internal SRAM 0 96Kb */
|
|
||||||
# define LPC313X_INTSRAM1_PADDR 0x11040000 /* 0x11040000-0x11057fff: Internal SRAM 1 96Kb */
|
|
||||||
/* 0x11058000-11ffffffff: Reserved */
|
|
||||||
#define LPC313X_INTSROM0_PSECTION 0x12000000 /* 0x12000000-0x1201ffff: Internal SROM 0 128Kb */
|
|
||||||
/* 0x12020000-0x12ffffff: Reserved */
|
|
||||||
#define LPC313X_APB01_PSECTION 0x13000000 /* 0x13000000-0x1300bfff: APB0 32Kb APB1 16Kb */
|
|
||||||
# define LPC313X_APB0_PADDR 0x13000000 /* 0x13000000-0x13007fff: APB0 32Kb */
|
|
||||||
# define LPC313X_APB1_PADDR 0x13008000 /* 0x13008000-0x1300bfff: APB1 16Kb */
|
|
||||||
/* 0x1300c000-0x14ffffff: Reserved */
|
|
||||||
#define LPC313X_APB2_PSECTION 0x15000000 /* 0x15000000-0x15003fff: APB2 16Kb */
|
|
||||||
#define LPC313X_APB3_PSECTION 0x16000000 /* 0x16000000-0x160003ff: APB3 1Kb */
|
|
||||||
#define LPC313X_APB4MPMC_PSECTION 0x17000000 /* 8Kb */
|
|
||||||
# define LPC313X_APB4_PADDR 0x17000000 /* 0x17000000-0x17000fff: APB4 4Kb */
|
|
||||||
# define LPC313X_MPMC_PADDR 0x17008000 /* 0x17008000-0x17008fff: MPMC cfg 4Kb */
|
|
||||||
/* 0x17009000-0x17ffffff: Reserved */
|
|
||||||
#define LPC313X_MCI_PSECTION 0x18000000 /* 0x18000000 0x180003ff: MCI/SD/SDIO 1Kb */
|
|
||||||
/* 0x18000900-0x18ffffff: Reserved */
|
|
||||||
#define LPC313X_USBOTG_PSECTION 0x19000000 /* 0x19000000-0x19000fff: USB OTG 4Kb */
|
|
||||||
/* 0x19001000-0x1fffffff: Reserved */
|
|
||||||
#define LPC313X_EXTSRAM_PSECTION 0x20000000 /* 64-128Kb */
|
|
||||||
# define LPC313X_EXTSRAM0_PADDR 0x20000000 /* 0x20000000-0x2001ffff: External SRAM 0 64-128Kb */
|
|
||||||
# define LPC313X_EXTSRAM1_PADDR 0x20020000 /* 0x20020000-0x2003ffff: External SRAM 1 64-128Kb */
|
|
||||||
#define LPC313X_EXTSDRAM0_PSECTION 0x30000000 /* 0x30000000-0x37ffffff: External SDRAM 0 128Mb */
|
|
||||||
/* 0x40000000-0x5fffffff: Reserved */
|
|
||||||
#define LPC313X_INTC_PSECTION 0x60000000 /* 0x60000000-0x60000fff: Interrupt controller 4Kb */
|
|
||||||
/* 0x60001000-0x6fffffff: Reserved */
|
|
||||||
#define LPC313X_NAND_PSECTION 0x70000000 /* 0x70000000-0x700007ff: NANDFLASH Ctrl 2Kb */
|
|
||||||
/* 0x70000800-0xffffffff: Reserved */
|
|
||||||
#ifdef CONFIG_LPC313X_EXTNAND /* End of the physical address space */
|
|
||||||
# define LPC313X_LAST_PSECTION (LPC313X_NAND_PSECTION + (1 << 20))
|
|
||||||
#else
|
|
||||||
# define LPC313X_LAST_PSECTION (LPC313X_INTC_PSECTION + (1 << 20))
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* APB0-4 Domain Offsets */
|
|
||||||
|
|
||||||
#define LPC313X_APB0_EVNTRTR_OFFSET 0x00000000 /* Event Router */
|
|
||||||
#define LPC313X_APB0_ADC_OFFSET 0x00002000 /* ADC 10-bit */
|
|
||||||
#define LPC313X_APB0_WDT_OFFSET 0x00002400 /* WDT */
|
|
||||||
#define LPC313X_APB0_SYSCREG_OFFSET 0x00002800 /* SYSCREG block */
|
|
||||||
#define LPC313X_APB0_IOCONFIG_OFFSET 0x00003000 /* IOCONFIG */
|
|
||||||
#define LPC313X_APB0_GCU_OFFSET 0x00004000 /* GCU */
|
|
||||||
/* 0x00005000 Reserved */
|
|
||||||
#define LPC313X_APB0_RNG_OFFSET 0x00006000 /* RNG */
|
|
||||||
|
|
||||||
#define LPC313X_APB1_TIMER0_OFFSET 0x00000000 /* TIMER0 */
|
|
||||||
#define LPC313X_APB1_TIMER1_OFFSET 0x00000400 /* TIMER1 */
|
|
||||||
#define LPC313X_APB1_TIMER2_OFFSET 0x00000800 /* TIMER2 */
|
|
||||||
#define LPC313X_APB1_TIMER3_OFFSET 0x00000c00 /* TIMER3 */
|
|
||||||
#define LPC313X_APB1_PWM_OFFSET 0x00001000 /* PWM */
|
|
||||||
#define LPC313X_APB1_I2C0_OFFSET 0x00002000 /* I2C0 */
|
|
||||||
#define LPC313X_APB1_I2C1_OFFSET 0x00002400 /* I2C1 */
|
|
||||||
|
|
||||||
#define LPC313X_APB2_PCM_OFFSET 0x00000000 /* PCM */
|
|
||||||
#define LPC313X_APB2_LCD_OFFSET 0x00000400 /* LCD */
|
|
||||||
/* 0x00000800 Reserved */
|
|
||||||
#define LPC313X_APB2_UART_OFFSET 0x00001000 /* UART */
|
|
||||||
#define LPC313X_APB2_SPI_OFFSET 0x00002000 /* SPI */
|
|
||||||
/* 0x00003000 Reserved */
|
|
||||||
|
|
||||||
#define LPC313X_APB3_I2SCONFIG_OFFSET 0x00000000 /* I2S System Configuration */
|
|
||||||
#define LPC313X_APB3_I2STX0_OFFSET 0x00000080 /* I2S TX0 */
|
|
||||||
#define LPC313X_APB3_I2STX1_OFFSET 0x00000100 /* I2S TX1 */
|
|
||||||
#define LPC313X_APB3_I2SRX0_OFFSET 0x00000180 /* I2S RX0 */
|
|
||||||
#define LPC313X_APB3_I2SRX1_OFFSET 0x00000200 /* I2S RX1 */
|
|
||||||
/* 0x00000280 Reserved */
|
|
||||||
|
|
||||||
#define LPC313X_APB4_DMA_OFFSET 0x00000000 /* DMA */
|
|
||||||
#define LPC313X_APB4_NAND_OFFSET 0x00000800 /* NAND FLASH Controller */
|
|
||||||
/* 0x00001000 Reserved */
|
|
||||||
|
|
||||||
/* Sizes of memory regions in bytes */
|
|
||||||
|
|
||||||
#define LPC313X_SHADOWSPACE_SIZE (4*1024)
|
|
||||||
#define LPC313X_INTSRAM0_SIZE (96*1024)
|
|
||||||
#define LPC313X_INTSRAM1_SIZE (96*1024)
|
|
||||||
#define LPC313X_INTSROM0_SIZE (128*1024)
|
|
||||||
#define LPC313X_APB0_SIZE (32*1024)
|
|
||||||
#define LPC313X_APB1_SIZE (16*1024)
|
|
||||||
#define LPC313X_APB2_SIZE (16*1024)
|
|
||||||
#define LPC313X_APB3_SIZE (1*1024)
|
|
||||||
#define LPC313X_APB4_SIZE (4*1024)
|
|
||||||
#define LPC313X_MPMC_SIZE (4*1024)
|
|
||||||
#define LPC313X_APB4MPMC_SIZE (LPC313X_APB4_SIZE+LPC313X_MPMC_SIZE)
|
|
||||||
#define LPC313X_MCI_SIZE (1*1024)
|
|
||||||
#define LPC313X_USBOTG_SIZE (4*1024)
|
|
||||||
#define LPC313X_INTC_SIZE (4*1024)
|
|
||||||
#define LPC313X_NAND_SIZE (2*1024)
|
|
||||||
|
|
||||||
#if defined(CONFIG_ARCH_CHIP_LPC3131)
|
|
||||||
# define LPC313X_ISRAM_SIZE (LPC313X_INTSRAM0_SIZE+LPC313X_INTSRAM1_SIZE)
|
|
||||||
#elif defined(CONFIG_ARCH_CHIP_LPC3130)
|
|
||||||
# define LPC313X_ISRAM_SIZE LPC313X_INTSRAM0_SIZE
|
|
||||||
#else
|
|
||||||
# error "Unsupported LPC313X architecture"
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Convert size in bytes to number of sections (in Mb). */
|
|
||||||
|
|
||||||
#define _NSECTIONS(b) (((b)+0x000fffff) >> 20)
|
|
||||||
|
|
||||||
/* Sizes of sections/regions. The boot logic in lpc313x_boot.c, will select
|
|
||||||
* 1Mb level 1 MMU mappings to span the entire physical address space.
|
|
||||||
* The definitiions below specifiy the number of 1Mb entries that are
|
|
||||||
* required to span a particular address region.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define LPC313X_SHADOWSPACE_NSECTIONS 1 /* 4Kb - <1 section */
|
|
||||||
#define LPC313X_INTSRAM_NSECTIONS 1 /* 96 or 192Kb - <1 section */
|
|
||||||
#define LPC313X_APB01_NSECTIONS 1 /* 32Kb - <1 section */
|
|
||||||
#define LPC313X_INTSROM0_NSECTIONS 1 /* 128Kb - <1 section */
|
|
||||||
#define LPC313X_APB1_NSECTIONS 1 /* 16Kb - <1 section */
|
|
||||||
#define LPC313X_APB2_NSECTIONS 1 /* 16Kb - <1 section */
|
|
||||||
#define LPC313X_APB3_NSECTIONS 1 /* 1Kb - <1 section */
|
|
||||||
#define LPC313X_APB4MPMC_NSECTIONS 1 /* 8Kb - <1 section */
|
|
||||||
#define LPC313X_MCI_NSECTIONS 1 /* 1Kb - <1 section */
|
|
||||||
#define LPC313X_USBOTG_NSECTIONS 1 /* 4Kb - <1 section */
|
|
||||||
#define LPC313X_EXTSRAM_NSECTIONS 1 /* 64-128Kb - <1 section */
|
|
||||||
#define LPC313X_INTC_NSECTIONS 1 /* 4Kb - <1 section */
|
|
||||||
#define LPC313X_NAND_NSECTIONS 1 /* 2Kb - <1 section */
|
|
||||||
|
|
||||||
/* External SDRAM is a special case -- the number of sections depends upon
|
|
||||||
* the size of the SDRAM installed.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if defined(CONFIG_LPC313X_EXTSDRAM) && CONFIG_LPC313X_EXTSDRAMSIZE > 0
|
|
||||||
# define LPC313X_EXTSDRAM0_NSECTIONS _NSECTIONS(CONFIG_LPC313X_EXTSDRAMSIZE)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Section MMU Flags */
|
|
||||||
|
|
||||||
#define LPC313X_SHADOWSPACE_MMUFLAGS MMU_ROMFLAGS
|
|
||||||
#define LPC313X_INTSRAM_MMUFLAGS MMU_MEMFLAGS
|
|
||||||
#define LPC313X_INTSROM_MMUFLAGS MMU_MEMFLAGS
|
|
||||||
#define LPC313X_APB01_MMUFLAGS MMU_IOFLAGS
|
|
||||||
#define LPC313X_APB2_MMUFLAGS MMU_IOFLAGS
|
|
||||||
#define LPC313X_APB3_MMUFLAGS MMU_IOFLAGS
|
|
||||||
#define LPC313X_APB4MPMC_MMUFLAGS MMU_IOFLAGS
|
|
||||||
#define LPC313X_MCI_MMUFLAGS MMU_IOFLAGS
|
|
||||||
#define LPC313X_USBOTG_MMUFLAGS MMU_IOFLAGS
|
|
||||||
#define LPC313X_EXTSRAM_MMUFLAGS MMU_MEMFLAGS
|
|
||||||
#define LPC313X_EXTSDRAM_MMUFLAGS MMU_MEMFLAGS
|
|
||||||
#define LPC313X_INTC_MMUFLAGS MMU_IOFLAGS
|
|
||||||
#define LPC313X_NAND_MMUFLAGS MMU_IOFLAGS
|
|
||||||
|
|
||||||
/* board_memorymap.h contains special mappings that are needed when a ROM
|
|
||||||
* memory map is used. It is included in this odd location becaue it depends
|
|
||||||
* on some the virtual address definitions provided above.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <arch/board/board_memorymap.h>
|
|
||||||
|
|
||||||
/* LPC313X Virtual (mapped) Memory Map. These are the mappings that will
|
|
||||||
* be created if the page table lies in RAM. If the platform has another,
|
|
||||||
* read-only, pre-initialized page table (perhaps in ROM), then the board.h
|
|
||||||
* file must provide these definitions.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef CONFIG_ARCH_ROMPGTABLE
|
|
||||||
# define LPC313X_FIRST_VSECTION 0x00000000 /* Beginning of the virtual address space */
|
|
||||||
# define LPC313X_SHADOWSPACE_VSECTION 0x00000000 /* 0x00000000-0x00000fff: Shadow Area 4Kb */
|
|
||||||
# define LPC313X_INTSRAM_VSECTION 0x11028000 /* Internal SRAM 96Kb-192Kb */
|
|
||||||
# define LPC313X_INTSRAM0_VADDR 0x11028000 /* 0x11028000-0x1103ffff: Internal SRAM 0 96Kb */
|
|
||||||
# define LPC313X_INTSRAM1_VADDR 0x11040000 /* 0x11040000-0x11057fff: Internal SRAM 1 96Kb */
|
|
||||||
# define LPC313X_INTSROM0_VSECTION 0x12000000 /* 0x12000000-0x1201ffff: Internal SROM 0 128Kb */
|
|
||||||
# define LPC313X_APB01_VSECTION 0x13000000 /* 0x13000000-0x1300bfff: APB0 32Kb APB0 32Kb */
|
|
||||||
# define LPC313X_APB0_VADDR 0x13000000 /* 0x13000000-0x13007fff: APB0 32Kb */
|
|
||||||
# define LPC313X_APB1_VADDR 0x13008000 /* 0x13008000-0x1300bfff: APB1 16Kb */
|
|
||||||
# define LPC313X_APB2_VSECTION 0x15000000 /* 0x15000000-0x15003fff: APB2 16Kb */
|
|
||||||
# define LPC313X_APB3_VSECTION 0x16000000 /* 0x16000000-0x160003ff: APB3 1Kb */
|
|
||||||
# define LPC313X_APB4MPMC_VSECTION 0x17000000 /* 8Kb */
|
|
||||||
# define LPC313X_APB4_VADDR 0x17000000 /* 0x17000000-0x17000fff: APB4 4Kb */
|
|
||||||
# define LPC313X_MPMC_VADDR 0x17008000 /* 0x17008000-0x17008fff: MPMC cfg 4Kb */
|
|
||||||
# define LPC313X_MCI_VSECTION 0x18000000 /* 0x18000000 0x180003ff: MCI/SD/SDIO 1Kb */
|
|
||||||
# define LPC313X_USBOTG_VSECTION 0x19000000 /* 0x19000000-0x19000fff: USB OTG 4Kb */
|
|
||||||
# define LPC313X_EXTSRAM_VSECTION 0x20020000 /* 64-128Kb */
|
|
||||||
# define LPC313X_EXTSRAM0_VADDR 0x20000000 /* 0x20000000-0x2001ffff: External SRAM 0 64-128Kb */
|
|
||||||
# define LPC313X_EXTSRAM1_VADDR 0x20020000 /* 0x20020000-0x2003ffff: External SRAM 1 64-128Kb */
|
|
||||||
# define LPC313X_EXTSDRAM0_VSECTION 0x30000000 /* 0x30000000-0x37ffffff: External SDRAM 0 128Mb */
|
|
||||||
# define LPC313X_INTC_VSECTION 0x60000000 /* 0x60000000-0x60000fff: Interrupt controller 4Kb */
|
|
||||||
# define LPC313X_NAND_VSECTION 0x70000000 /* 0x70000000-0x700007ff: NANDFLASH Ctrl 2Kb */
|
|
||||||
#
|
|
||||||
# ifdef CONFIG_LPC313X_EXTNAND /* End of the virtual address space */
|
|
||||||
# define LPC313X_LAST_VSECTION (LPC313X_NAND_VSECTION + (1 << 20))
|
|
||||||
# else
|
|
||||||
# define LPC313X_LAST_VSECTION (LPC313X_INTC_VSECTION + (1 << 20))
|
|
||||||
# endif
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* The boot logic will create a temporarily mapping based on where NuttX is
|
|
||||||
* executing in memory. In this case, NuttX could be running from NOR FLASH,
|
|
||||||
* SDRAM, external SRAM, or ISRAM.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#if defined(CONFIG_BOOT_RUNFROMFLASH)
|
|
||||||
# define NUTTX_START_VADDR LPC313X_MPMC_VADDR
|
|
||||||
#elif defined(CONFIG_BOOT_RUNFROMSDRAM)
|
|
||||||
# define NUTTX_START_VADDR LPC313X_EXTSDRAM0_VSECTION
|
|
||||||
#elif defined(CONFIG_BOOT_RUNFROMEXTSRAM)
|
|
||||||
# define NUTTX_START_VADDR LPC313X_EXTSRAM0_VADDR
|
|
||||||
#else /* CONFIG_BOOT_RUNFROMISRAM, CONFIG_PAGING */
|
|
||||||
# define NUTTX_START_VADDR LPC313X_INTSRAM0_VADDR
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Determine the address of the MMU page table. We will try to place that page
|
|
||||||
* table at the beginng of ISRAM0 if the vectors are at the high address, 0xffff:0000
|
|
||||||
* or at the end of ISRAM1 (or ISRAM0 on a LPC3130) if the vectors are at 0x0000:0000
|
|
||||||
*
|
|
||||||
* Or... the user may specify the address of the page table explicitly be defining
|
|
||||||
* CONFIG_PGTABLE_VADDR and CONFIG_PGTABLE_PADDR in the configuration or board.h file.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#undef PGTABLE_IN_HIGHSRAM
|
|
||||||
#undef PGTABLE_IN_LOWSRAM
|
|
||||||
|
|
||||||
#if !defined(PGTABLE_BASE_PADDR) || !defined(PGTABLE_BASE_VADDR)
|
|
||||||
|
|
||||||
/* Sanity check.. if one is undefined, both should be undefined */
|
|
||||||
|
|
||||||
# if defined(PGTABLE_BASE_PADDR) || defined(PGTABLE_BASE_VADDR)
|
|
||||||
# error "Only one of PGTABLE_BASE_PADDR or PGTABLE_BASE_VADDR is defined"
|
|
||||||
# endif
|
|
||||||
|
|
||||||
/* A sanity check, if the configuration says that the page table is read-only
|
|
||||||
* and pre-initialized (maybe ROM), then it should have also defined both of
|
|
||||||
* the page table base addresses.
|
|
||||||
*/
|
|
||||||
|
|
||||||
# ifdef CONFIG_ARCH_ROMPGTABLE
|
|
||||||
# error "CONFIG_ARCH_ROMPGTABLE defined; PGTABLE_BASE_P/VADDR not defined"
|
|
||||||
# else
|
|
||||||
|
|
||||||
/* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory
|
|
||||||
* map probably do not apply because paging logic will probably partition
|
|
||||||
* the SRAM section differently. In particular, if the page table is located
|
|
||||||
* at the end of SRAM, then the virtual page table address defined below
|
|
||||||
* will probably be in error.
|
|
||||||
*
|
|
||||||
* We work around this header file interdependency by (1) insisting that
|
|
||||||
* pg_macros.h be included AFTER this header file, then (2) allowing the
|
|
||||||
* pg_macros.h header file to redefine PGTABLE_BASE_VADDR.
|
|
||||||
*/
|
|
||||||
|
|
||||||
# if defined(CONFIG_PAGING) && defined(__ARCH_ARM_SRC_ARM_PG_MACROS_H)
|
|
||||||
# error "pg_macros.h must be included AFTER this header file"
|
|
||||||
# endif
|
|
||||||
|
|
||||||
|
|
||||||
/* We must declare the page table in ISRAM0 or 1. We decide depending upon
|
|
||||||
* where the vector table was place.
|
|
||||||
*/
|
|
||||||
|
|
||||||
# ifdef CONFIG_ARCH_LOWVECTORS /* Vectors located at 0x0000:0000 */
|
|
||||||
|
|
||||||
/* In this case, ISRAM0 will be shadowed at address 0x0000:0000. The page
|
|
||||||
* table must lie at the top 16Kb of ISRAM1 (or ISRAM0 if this is a LPC3130)
|
|
||||||
*/
|
|
||||||
|
|
||||||
# if CONFIG_ARCH_CHIP_LPC3131
|
|
||||||
# define PGTABLE_BASE_PADDR (LPC313X_INTSRAM1_PADDR+LPC313X_INTSRAM1_SIZE-PGTABLE_SIZE)
|
|
||||||
# define PGTABLE_BASE_VADDR (LPC313X_INTSRAM1_VADDR+LPC313X_INTSRAM1_SIZE-PGTABLE_SIZE)
|
|
||||||
# else
|
|
||||||
# define PGTABLE_BASE_PADDR (LPC313X_INTSRAM0_PADDR+LPC313X_INTSRAM0_SIZE-PGTABLE_SIZE)
|
|
||||||
# define PGTABLE_BASE_VADDR (LPC313X_INTSRAM0_VADDR+LPC313X_INTSRAM0_SIZE-PGTABLE_SIZE)
|
|
||||||
# endif
|
|
||||||
# define PGTABLE_IN_HIGHSRAM 1
|
|
||||||
|
|
||||||
/* If CONFIG_PAGING is defined, insist that pg_macros.h assign the virtual
|
|
||||||
* address of the page table.
|
|
||||||
*/
|
|
||||||
|
|
||||||
# ifdef CONFIG_PAGING
|
|
||||||
# undef PGTABLE_BASE_VADDR
|
|
||||||
# endif
|
|
||||||
# else
|
|
||||||
|
|
||||||
/* Otherwise, ISRAM1 (or ISRAM0 for the LPC3130) will be mapped so that
|
|
||||||
* the end of the SRAM region will provide memory for the vectors. The page
|
|
||||||
* table will then be places at the first 16Kb of ISRAM0 (which will be in
|
|
||||||
* the shadow memory region.
|
|
||||||
*/
|
|
||||||
|
|
||||||
# define PGTABLE_BASE_PADDR LPC313X_SHADOWSPACE_PSECTION
|
|
||||||
# define PGTABLE_BASE_VADDR LPC313X_SHADOWSPACE_VSECTION
|
|
||||||
# define PGTABLE_IN_LOWSRAM 1
|
|
||||||
# endif
|
|
||||||
# endif
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Page table start addresses:
|
|
||||||
*
|
|
||||||
* 16Kb of memory is reserved hold the page table for the virtual mappings. A
|
|
||||||
* portion of this table is not accessible in the virtual address space (for
|
|
||||||
* normal operation). We will reuse this memory for coarse page tables as follows:
|
|
||||||
*
|
|
||||||
* NOTE: If CONFIG_PAGING is defined, pg_macros.h will re-assign the virtual
|
|
||||||
* address of the page table.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define PGTABLE_L2_COARSE_OFFSET ((((LPC313X_LAST_PSECTION >> 20) + 255) & ~255) << 2)
|
|
||||||
#define PGTABLE_L2_COARSE_PBASE (PGTABLE_BASE_PADDR+PGTABLE_L2_COARSE_OFFSET)
|
|
||||||
#define PGTABLE_L2_COARSE_VBASE (PGTABLE_BASE_VADDR+PGTABLE_L2_COARSE_OFFSET)
|
|
||||||
|
|
||||||
#define PGTABLE_L2_FINE_OFFSET ((((LPC313X_LAST_PSECTION >> 20) + 1023) & ~1023) << 2)
|
|
||||||
#define PGTABLE_L2_FINE_PBASE (PGTABLE_BASE_PADDR+PGTABLE_L2_FINE_OFFSET)
|
|
||||||
#define PGTABLE_L2_FINE_VBASE (PGTABLE_BASE_VADDR+PGTABLE_L2_FINE_OFFSET)
|
|
||||||
|
|
||||||
/* Page table end addresses: */
|
|
||||||
|
|
||||||
#define PGTABLE_L2_END_PADDR (PGTABLE_BASE_PADDR+PGTABLE_SIZE)
|
|
||||||
#define PGTABLE_L2_END_VADDR (PGTABLE_BASE_VADDR+PGTABLE_SIZE)
|
|
||||||
|
|
||||||
/* Page table sizes */
|
|
||||||
|
|
||||||
#define PGTABLE_L2_COARSE_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_COARSE_VBASE)
|
|
||||||
#define PGTABLE_COARSE_TABLE_SIZE (4*256)
|
|
||||||
#define PGTABLE_NCOARSE_TABLES (PGTABLE_L2_COARSE_ALLOC / PGTABLE_COARSE_TABLE_SIZE)
|
|
||||||
|
|
||||||
#define PGTABLE_L2_FINE_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_FINE_VBASE)
|
|
||||||
#define PGTABLE_FINE_TABLE_SIZE (4*1024)
|
|
||||||
#define PGTABLE_NFINE_TABLES (PGTABLE_L2_FINE_ALLOC / PGTABLE_FINE_TABLE_SIZE)
|
|
||||||
|
|
||||||
/* Determine the base address of the vector table:
|
|
||||||
*
|
|
||||||
* LPC313X_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM
|
|
||||||
* LPC313X_VECTOR_VSRAM - Virtual address of vector table in SRAM
|
|
||||||
* LPC313X_VECTOR_VADDR - Virtual address of vector table (0x00000000 or 0xffff0000)
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define VECTOR_TABLE_SIZE 0x00010000
|
|
||||||
#ifdef CONFIG_ARCH_LOWVECTORS /* Vectors located at 0x0000:0000 */
|
|
||||||
# define LPC313X_VECTOR_PADDR LPC313X_INTSRAM0_PADDR
|
|
||||||
# define LPC313X_VECTOR_VSRAM LPC313X_INTSRAM0_VADDR
|
|
||||||
# define LPC313X_VECTOR_VADDR 0x00000000
|
|
||||||
# define LPC313X_VECTOR_VCOARSE 0x00000000
|
|
||||||
#else /* Vectors located at 0xffff:0000 -- this probably does not work */
|
|
||||||
# if CONFIG_ARCH_CHIP_LPC3131
|
|
||||||
# define LPC313X_VECTOR_PADDR (LPC313X_INTSRAM1_PADDR+LPC313X_INTSRAM1_SIZE-VECTOR_TABLE_SIZE)
|
|
||||||
# define LPC313X_VECTOR_VSRAM (LPC313X_INTSRAM1_VADDR+LPC313X_INTSRAM1_SIZE-VECTOR_TABLE_SIZE)
|
|
||||||
# else
|
|
||||||
# define LPC313X_VECTOR_PADDR (LPC313X_INTSRAM0_PADDR+LPC313X_INTSRAM0_SIZE-VECTOR_TABLE_SIZE)
|
|
||||||
# define LPC313X_VECTOR_VSRAM (LPC313X_INTSRAM0_VADDR+LPC313X_INTSRAM0_SIZE-VECTOR_TABLE_SIZE)
|
|
||||||
# endif
|
|
||||||
# define LPC313X_VECTOR_VADDR 0xffff0000
|
|
||||||
# define LPC313X_VECTOR_VCOARSE 0xfff00000
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/************************************************************************************
|
|
||||||
* Public Types
|
|
||||||
************************************************************************************/
|
|
||||||
|
|
||||||
/************************************************************************************
|
|
||||||
* Public Data
|
|
||||||
************************************************************************************/
|
|
||||||
|
|
||||||
/************************************************************************************
|
|
||||||
* Public Functions
|
|
||||||
************************************************************************************/
|
|
||||||
|
|
||||||
#endif /* __ARCH_ARM_SRC_LPC313X_MEMORYMAP_H */
|
|
||||||
File diff suppressed because it is too large
Load Diff
@@ -1,7 +1,7 @@
|
|||||||
############################################################################
|
############################################################################
|
||||||
# arch/arm/lpc313x/Make.defs
|
# arch/arm/lpc31xx/Make.defs
|
||||||
#
|
#
|
||||||
# Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
# Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
|
||||||
# Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
# Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
#
|
#
|
||||||
# Redistribution and use in source and binary forms, with or without
|
# Redistribution and use in source and binary forms, with or without
|
||||||
@@ -51,17 +51,17 @@ CMN_CSRCS += up_pginitialize.c up_checkmapping.c up_allocpage.c up_va2pte.c
|
|||||||
endif
|
endif
|
||||||
|
|
||||||
CGU_ASRCS =
|
CGU_ASRCS =
|
||||||
CGU_CSRCS = lpc313x_bcrndx.c lpc313x_clkdomain.c lpc313x_clkexten.c \
|
CGU_CSRCS = lpc31_bcrndx.c lpc31_clkdomain.c lpc31_clkexten.c \
|
||||||
lpc313x_clkfreq.c lpc313x_clkinit.c lpc313x_defclk.c \
|
lpc31_clkfreq.c lpc31_clkinit.c lpc31_defclk.c \
|
||||||
lpc313x_esrndx.c lpc313x_fdcndx.c lpc313x_fdivinit.c \
|
lpc31_esrndx.c lpc31_fdcndx.c lpc31_fdivinit.c \
|
||||||
lpc313x_freqin.c lpc313x_pllconfig.c lpc313x_resetclks.c \
|
lpc31_freqin.c lpc31_pllconfig.c lpc31_resetclks.c \
|
||||||
lpc313x_setfreqin.c lpc313x_setfdiv.c lpc313x_softreset.c
|
lpc31_setfreqin.c lpc31_setfdiv.c lpc31_softreset.c
|
||||||
|
|
||||||
CHIP_ASRCS = $(CGU_ASRCS)
|
CHIP_ASRCS = $(CGU_ASRCS)
|
||||||
CHIP_CSRCS = lpc313x_allocateheap.c lpc313x_boot.c lpc313x_decodeirq.c \
|
CHIP_CSRCS = lpc31_allocateheap.c lpc31_boot.c lpc31_decodeirq.c \
|
||||||
lpc313x_irq.c lpc313x_lowputc.c lpc313x_serial.c lpc313x_i2c.c \
|
lpc31_irq.c lpc31_lowputc.c lpc31_serial.c lpc31_i2c.c \
|
||||||
lpc313x_spi.c lpc313x_timerisr.c $(CGU_CSRCS)
|
lpc31_spi.c lpc31_timerisr.c $(CGU_CSRCS)
|
||||||
|
|
||||||
ifeq ($(CONFIG_USBDEV),y)
|
ifeq ($(CONFIG_USBDEV),y)
|
||||||
CHIP_CSRCS += lpc313x_usbdev.c
|
CHIP_CSRCS += lpc31_usbdev.c
|
||||||
endif
|
endif
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* arch/arm/src/lpc313x/chip.h
|
* arch/arm/src/lpc31xx/chip.h
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -33,15 +33,15 @@
|
|||||||
*
|
*
|
||||||
************************************************************************************/
|
************************************************************************************/
|
||||||
|
|
||||||
#ifndef __ARCH_ARM_SRC_LPC313X_CHIP_H
|
#ifndef __ARCH_ARM_SRC_LPC31XX_CHIP_H
|
||||||
#define __ARCH_ARM_SRC_LPC313X_CHIP_H
|
#define __ARCH_ARM_SRC_LPC31XX_CHIP_H
|
||||||
|
|
||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* Included Files
|
* Included Files
|
||||||
************************************************************************************/
|
************************************************************************************/
|
||||||
|
|
||||||
#include <nuttx/config.h>
|
#include <nuttx/config.h>
|
||||||
#include "lpc313x_memorymap.h"
|
#include "lpc31_memorymap.h"
|
||||||
|
|
||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -59,4 +59,4 @@
|
|||||||
* Public Functions
|
* Public Functions
|
||||||
************************************************************************************/
|
************************************************************************************/
|
||||||
|
|
||||||
#endif /* __ARCH_ARM_SRC_LPC313X_CHIP_H */
|
#endif /* __ARCH_ARM_SRC_LPC31XX_CHIP_H */
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_adc.h
|
* arch/arm/src/lpc31xx/lpc31_adc.h
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -33,15 +33,15 @@
|
|||||||
*
|
*
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#ifndef __ARCH_ARM_SRC_LPC313X_ADC_H
|
#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_ADC_H
|
||||||
#define __ARCH_ARM_SRC_LPC313X_ADC_H
|
#define __ARCH_ARM_SRC_LPC31XX_LPC31_ADC_H
|
||||||
|
|
||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* Included Files
|
* Included Files
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#include <nuttx/config.h>
|
#include <nuttx/config.h>
|
||||||
#include "lpc313x_memorymap.h"
|
#include "lpc31_memorymap.h"
|
||||||
|
|
||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -49,34 +49,34 @@
|
|||||||
|
|
||||||
/* ADC register base address offset into the APB0 domain ****************************************/
|
/* ADC register base address offset into the APB0 domain ****************************************/
|
||||||
|
|
||||||
#define LPC313X_ADC_VBASE (LPC313X_APB0_VADDR+LPC313X_APB0_ADC_OFFSET)
|
#define LPC31_ADC_VBASE (LPC31_APB0_VADDR+LPC31_APB0_ADC_OFFSET)
|
||||||
#define LPC313X_ADC_PBASE (LPC313X_APB0_PADDR+LPC313X_APB0_ADC_OFFSET)
|
#define LPC31_ADC_PBASE (LPC31_APB0_PADDR+LPC31_APB0_ADC_OFFSET)
|
||||||
|
|
||||||
/* ADC register offsets (with respect to the ADC base) ******************************************/
|
/* ADC register offsets (with respect to the ADC base) ******************************************/
|
||||||
|
|
||||||
#define LPC313X_ADC_R0_OFFSET 0x000 /* Data for analog input channel 0 */
|
#define LPC31_ADC_R0_OFFSET 0x000 /* Data for analog input channel 0 */
|
||||||
#define LPC313X_ADC_R1_OFFSET 0x004 /* Data for analog input channel 1 */
|
#define LPC31_ADC_R1_OFFSET 0x004 /* Data for analog input channel 1 */
|
||||||
#define LPC313X_ADC_R2_OFFSET 0x008 /* Data for analog input channel 2 */
|
#define LPC31_ADC_R2_OFFSET 0x008 /* Data for analog input channel 2 */
|
||||||
#define LPC313X_ADC_R3_OFFSET 0x00c /* Data for analog input channel 3 */
|
#define LPC31_ADC_R3_OFFSET 0x00c /* Data for analog input channel 3 */
|
||||||
/* 0x010-0x01c: Reserved */
|
/* 0x010-0x01c: Reserved */
|
||||||
#define LPC313X_ADC_CON_OFFSET 0x020 /* ADC control register */
|
#define LPC31_ADC_CON_OFFSET 0x020 /* ADC control register */
|
||||||
#define LPC313X_ADC_CSEL_OFFSET 0x024 /* Configure and select analog input channels */
|
#define LPC31_ADC_CSEL_OFFSET 0x024 /* Configure and select analog input channels */
|
||||||
#define LPC313X_ADC_INTEN_OFFSET 0x028 /* Enable ADC interrupts */
|
#define LPC31_ADC_INTEN_OFFSET 0x028 /* Enable ADC interrupts */
|
||||||
#define LPC313X_ADC_INTST_OFFSET 0x02C /* ADC interrupt status */
|
#define LPC31_ADC_INTST_OFFSET 0x02C /* ADC interrupt status */
|
||||||
#define LPC313X_ADC_INTCLR_OFFSET 0x030 /* Clear ADC interrupt status */
|
#define LPC31_ADC_INTCLR_OFFSET 0x030 /* Clear ADC interrupt status */
|
||||||
/* 0x034-: Reserved */
|
/* 0x034-: Reserved */
|
||||||
|
|
||||||
/* ADC register (virtual) addresses *************************************************************/
|
/* ADC register (virtual) addresses *************************************************************/
|
||||||
|
|
||||||
#define LPC313X_ADC_R0 (LPC313X_ADC_VBASE+LPC313X_ADC_R0_OFFSET)
|
#define LPC31_ADC_R0 (LPC31_ADC_VBASE+LPC31_ADC_R0_OFFSET)
|
||||||
#define LPC313X_ADC_R1 (LPC313X_ADC_VBASE+LPC313X_ADC_R1_OFFSET)
|
#define LPC31_ADC_R1 (LPC31_ADC_VBASE+LPC31_ADC_R1_OFFSET)
|
||||||
#define LPC313X_ADC_R2 (LPC313X_ADC_VBASE+LPC313X_ADC_R2_OFFSET)
|
#define LPC31_ADC_R2 (LPC31_ADC_VBASE+LPC31_ADC_R2_OFFSET)
|
||||||
#define LPC313X_ADC_R3 (LPC313X_ADC_VBASE+LPC313X_ADC_R3_OFFSET)
|
#define LPC31_ADC_R3 (LPC31_ADC_VBASE+LPC31_ADC_R3_OFFSET)
|
||||||
#define LPC313X_ADC_CON (LPC313X_ADC_VBASE+LPC313X_ADC_CON_OFFSET)
|
#define LPC31_ADC_CON (LPC31_ADC_VBASE+LPC31_ADC_CON_OFFSET)
|
||||||
#define LPC313X_ADC_CSEL (LPC313X_ADC_VBASE+LPC313X_ADC_CSEL_OFFSET)
|
#define LPC31_ADC_CSEL (LPC31_ADC_VBASE+LPC31_ADC_CSEL_OFFSET)
|
||||||
#define LPC313X_ADC_INTEN (LPC313X_ADC_VBASE+LPC313X_ADC_INTEN_OFFSET)
|
#define LPC31_ADC_INTEN (LPC31_ADC_VBASE+LPC31_ADC_INTEN_OFFSET)
|
||||||
#define LPC313X_ADC_INTST (LPC313X_ADC_VBASE+LPC313X_ADC_INTST_OFFSET)
|
#define LPC31_ADC_INTST (LPC31_ADC_VBASE+LPC31_ADC_INTST_OFFSET)
|
||||||
#define LPC313X_ADC_INTCLR (LPC313X_ADC_VBASE+LPC313X_ADC_INTCLR_OFFSET)
|
#define LPC31_ADC_INTCLR (LPC31_ADC_VBASE+LPC31_ADC_INTCLR_OFFSET)
|
||||||
|
|
||||||
/* ADC register bit definitions *****************************************************************/
|
/* ADC register bit definitions *****************************************************************/
|
||||||
|
|
||||||
@@ -129,4 +129,4 @@
|
|||||||
* Public Functions
|
* Public Functions
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#endif /* __ARCH_ARM_SRC_LPC313X_ADC_H */
|
#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_ADC_H */
|
||||||
+33
-33
@@ -1,5 +1,5 @@
|
|||||||
/************************************************************************
|
/************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_allocateheap.c
|
* arch/arm/src/lpc31xx/lpc31_allocateheap.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -49,7 +49,7 @@
|
|||||||
#include "chip.h"
|
#include "chip.h"
|
||||||
#include "up_arch.h"
|
#include "up_arch.h"
|
||||||
#include "up_internal.h"
|
#include "up_internal.h"
|
||||||
#include "lpc313x_memorymap.h"
|
#include "lpc31_memorymap.h"
|
||||||
|
|
||||||
#ifdef CONFIG_PAGING
|
#ifdef CONFIG_PAGING
|
||||||
# include <nuttx/page.h>
|
# include <nuttx/page.h>
|
||||||
@@ -67,51 +67,51 @@
|
|||||||
* memory regions that we have been asked to add to the heap.
|
* memory regions that we have been asked to add to the heap.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if defined(CONFIG_LPC313X_EXTSRAM0) && defined(CONFIG_LPC313X_EXTSRAM0HEAP)
|
#if defined(CONFIG_LPC31_EXTSRAM0) && defined(CONFIG_LPC31_EXTSRAM0HEAP)
|
||||||
# if defined(CONFIG_LPC313X_EXTSRAM1) && defined(CONFIG_LPC313X_EXTSRAM1HEAP)
|
# if defined(CONFIG_LPC31_EXTSRAM1) && defined(CONFIG_LPC31_EXTSRAM1HEAP)
|
||||||
# if defined(CONFIG_LPC313X_EXTSDRAM) && defined(CONFIG_LPC313X_EXTSDRAMHEAP)
|
# if defined(CONFIG_LPC31_EXTSDRAM) && defined(CONFIG_LPC31_EXTSDRAMHEAP)
|
||||||
# /* SRAM+EXTSRAM0+EXTSRAM1+EXTSDRAM */
|
# /* SRAM+EXTSRAM0+EXTSRAM1+EXTSDRAM */
|
||||||
# define LPC313X_NEXT_REGIONS 4
|
# define LPC31_NEXT_REGIONS 4
|
||||||
# else
|
# else
|
||||||
# /* SRAM+EXTSRAM0+EXTSRAM1 */
|
# /* SRAM+EXTSRAM0+EXTSRAM1 */
|
||||||
# define LPC313X_NEXT_REGIONS 3
|
# define LPC31_NEXT_REGIONS 3
|
||||||
# endif
|
# endif
|
||||||
# elif defined(CONFIG_LPC313X_EXTSDRAM) && defined(CONFIG_LPC313X_EXTSDRAMHEAP)
|
# elif defined(CONFIG_LPC31_EXTSDRAM) && defined(CONFIG_LPC31_EXTSDRAMHEAP)
|
||||||
# /* SRAM+EXTSRAM0+EXTSDRAM */
|
# /* SRAM+EXTSRAM0+EXTSDRAM */
|
||||||
# define LPC313X_NEXT_REGIONS 3
|
# define LPC31_NEXT_REGIONS 3
|
||||||
# else
|
# else
|
||||||
# /* SRAM+EXTSRAM0 */
|
# /* SRAM+EXTSRAM0 */
|
||||||
# define LPC313X_NEXT_REGIONS 2
|
# define LPC31_NEXT_REGIONS 2
|
||||||
# endif
|
# endif
|
||||||
#elif defined(CONFIG_LPC313X_EXTSRAM1) && defined(CONFIG_LPC313X_EXTSRAM1HEAP)
|
#elif defined(CONFIG_LPC31_EXTSRAM1) && defined(CONFIG_LPC31_EXTSRAM1HEAP)
|
||||||
# if defined(CONFIG_LPC313X_EXTSDRAM) && defined(CONFIG_LPC313X_EXTSDRAMHEAP)
|
# if defined(CONFIG_LPC31_EXTSDRAM) && defined(CONFIG_LPC31_EXTSDRAMHEAP)
|
||||||
# /* SRAM+EXTSRAM1+EXTSDRAM */
|
# /* SRAM+EXTSRAM1+EXTSDRAM */
|
||||||
# define LPC313X_NEXT_REGIONS 3
|
# define LPC31_NEXT_REGIONS 3
|
||||||
# else
|
# else
|
||||||
# /* SRAM+EXTSRAM1 */
|
# /* SRAM+EXTSRAM1 */
|
||||||
# define LPC313X_NEXT_REGIONS 2
|
# define LPC31_NEXT_REGIONS 2
|
||||||
# endif
|
# endif
|
||||||
#elif defined(CONFIG_LPC313X_EXTSDRAM) && defined(CONFIG_LPC313X_EXTSDRAMHEAP)
|
#elif defined(CONFIG_LPC31_EXTSDRAM) && defined(CONFIG_LPC31_EXTSDRAMHEAP)
|
||||||
# /* SRAM+EXTSDRAM */
|
# /* SRAM+EXTSDRAM */
|
||||||
# define LPC313X_NEXT_REGIONS 2
|
# define LPC31_NEXT_REGIONS 2
|
||||||
#else
|
#else
|
||||||
# /* SRAM */
|
# /* SRAM */
|
||||||
# define LPC313X_NEXT_REGIONS 1
|
# define LPC31_NEXT_REGIONS 1
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if CONFIG_MM_REGIONS != LPC313X_NEXT_REGIONS
|
#if CONFIG_MM_REGIONS != LPC31_NEXT_REGIONS
|
||||||
# if CONFIG_MM_REGIONS < LPC313X_NEXT_REGIONS
|
# if CONFIG_MM_REGIONS < LPC31_NEXT_REGIONS
|
||||||
# error "CONFIG_MM_REGIONS is large enough for the selected memory regions"
|
# error "CONFIG_MM_REGIONS is large enough for the selected memory regions"
|
||||||
# else
|
# else
|
||||||
# error "CONFIG_MM_REGIONS is too large for the selected memory regions"
|
# error "CONFIG_MM_REGIONS is too large for the selected memory regions"
|
||||||
# endif
|
# endif
|
||||||
# if defined(CONFIG_LPC313X_EXTSRAM0) && defined(CONFIG_LPC313X_EXTSRAM0HEAP)
|
# if defined(CONFIG_LPC31_EXTSRAM0) && defined(CONFIG_LPC31_EXTSRAM0HEAP)
|
||||||
# error "External SRAM0 is selected for heap"
|
# error "External SRAM0 is selected for heap"
|
||||||
# endif
|
# endif
|
||||||
# if defined(CONFIG_LPC313X_EXTSRAM1) && defined(CONFIG_LPC313X_EXTSRAM1HEAP)
|
# if defined(CONFIG_LPC31_EXTSRAM1) && defined(CONFIG_LPC31_EXTSRAM1HEAP)
|
||||||
# error "External SRAM1 is selected for heap"
|
# error "External SRAM1 is selected for heap"
|
||||||
# endif
|
# endif
|
||||||
# if defined(CONFIG_LPC313X_EXTSDRAM) && defined(CONFIG_LPC313X_EXTSDRAMHEAP)
|
# if defined(CONFIG_LPC31_EXTSDRAM) && defined(CONFIG_LPC31_EXTSDRAMHEAP)
|
||||||
# error "External SRAM1 is selected for heap"
|
# error "External SRAM1 is selected for heap"
|
||||||
# endif
|
# endif
|
||||||
#endif
|
#endif
|
||||||
@@ -128,15 +128,15 @@
|
|||||||
|
|
||||||
#ifdef CONFIG_PAGING
|
#ifdef CONFIG_PAGING
|
||||||
# ifdef PGTABLE_IN_HIGHSRAM
|
# ifdef PGTABLE_IN_HIGHSRAM
|
||||||
# define LPC313X_HEAP_VEND (PG_LOCKED_VBASE + PG_TOTAL_VSIZE - PGTABLE_SIZE)
|
# define LPC31_HEAP_VEND (PG_LOCKED_VBASE + PG_TOTAL_VSIZE - PGTABLE_SIZE)
|
||||||
# else
|
# else
|
||||||
# define LPC313X_HEAP_VEND (PG_LOCKED_VBASE + PG_TOTAL_VSIZE)
|
# define LPC31_HEAP_VEND (PG_LOCKED_VBASE + PG_TOTAL_VSIZE)
|
||||||
# endif
|
# endif
|
||||||
#else
|
#else
|
||||||
# ifdef PGTABLE_IN_HIGHSRAM
|
# ifdef PGTABLE_IN_HIGHSRAM
|
||||||
# define LPC313X_HEAP_VEND (LPC313X_INTSRAM_VSECTION + LPC313X_ISRAM_SIZE - PGTABLE_SIZE)
|
# define LPC31_HEAP_VEND (LPC31_INTSRAM_VSECTION + LPC31_ISRAM_SIZE - PGTABLE_SIZE)
|
||||||
# else
|
# else
|
||||||
# define LPC313X_HEAP_VEND (LPC313X_INTSRAM_VSECTION + LPC313X_ISRAM_SIZE)
|
# define LPC31_HEAP_VEND (LPC31_INTSRAM_VSECTION + LPC31_ISRAM_SIZE)
|
||||||
# endif
|
# endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
@@ -176,7 +176,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
|
|||||||
{
|
{
|
||||||
up_ledon(LED_HEAPALLOCATE);
|
up_ledon(LED_HEAPALLOCATE);
|
||||||
*heap_start = (FAR void*)g_heapbase;
|
*heap_start = (FAR void*)g_heapbase;
|
||||||
*heap_size = LPC313X_HEAP_VEND - g_heapbase;
|
*heap_size = LPC31_HEAP_VEND - g_heapbase;
|
||||||
}
|
}
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
@@ -191,16 +191,16 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
|
|||||||
#if CONFIG_MM_REGIONS > 1
|
#if CONFIG_MM_REGIONS > 1
|
||||||
void up_addregion(void)
|
void up_addregion(void)
|
||||||
{
|
{
|
||||||
#if defined(CONFIG_LPC313X_EXTSRAM0) && defined(CONFIG_LPC313X_EXTSRAM0HEAP)
|
#if defined(CONFIG_LPC31_EXTSRAM0) && defined(CONFIG_LPC31_EXTSRAM0HEAP)
|
||||||
mm_addregion((FAR void*)LPC313X_EXTSRAM0_VSECTION, CONFIG_LPC313X_EXTSRAM0SIZE);
|
mm_addregion((FAR void*)LPC31_EXTSRAM0_VSECTION, CONFIG_LPC31_EXTSRAM0SIZE);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(CONFIG_LPC313X_EXTSRAM1) && defined(CONFIG_LPC313X_EXTSRAM1HEAP)
|
#if defined(CONFIG_LPC31_EXTSRAM1) && defined(CONFIG_LPC31_EXTSRAM1HEAP)
|
||||||
mm_addregion((FAR void*)LPC313X_EXTSRAM1_VSECTION, CONFIG_LPC313X_EXTSRAM1SIZE);
|
mm_addregion((FAR void*)LPC31_EXTSRAM1_VSECTION, CONFIG_LPC31_EXTSRAM1SIZE);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined(CONFIG_LPC313X_EXTSDRAM) && defined(CONFIG_LPC313X_EXTSDRAMHEAP)
|
#if defined(CONFIG_LPC31_EXTSDRAM) && defined(CONFIG_LPC31_EXTSDRAMHEAP)
|
||||||
mm_addregion((FAR void*)LPC313X_EXTSDRAM_VSECTION, CONFIG_LPC313X_EXTSDRAMSIZE);
|
mm_addregion((FAR void*)LPC31_EXTSDRAM_VSECTION, CONFIG_LPC31_EXTSDRAMSIZE);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/************************************************************************
|
/************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_bcrndx.c
|
* arch/arm/src/lpc31xx/lpc31_bcrndx.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -45,7 +45,7 @@
|
|||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
|
|
||||||
#include "up_arch.h"
|
#include "up_arch.h"
|
||||||
#include "lpc313x_cgudrvr.h"
|
#include "lpc31_cgudrvr.h"
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -64,7 +64,7 @@
|
|||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_bcrndx
|
* Name: lpc31_bcrndx
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Only 5 of the 12 domains have an associated BCR register. This
|
* Only 5 of the 12 domains have an associated BCR register. This
|
||||||
@@ -73,7 +73,7 @@
|
|||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
int lpc313x_bcrndx(enum lpc313x_domainid_e dmnid)
|
int lpc31_bcrndx(enum lpc31_domainid_e dmnid)
|
||||||
{
|
{
|
||||||
switch (dmnid)
|
switch (dmnid)
|
||||||
{
|
{
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_boot.c
|
* arch/arm/src/lpc31xx/lpc31_boot.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -47,9 +47,9 @@
|
|||||||
#include "up_internal.h"
|
#include "up_internal.h"
|
||||||
#include "up_arch.h"
|
#include "up_arch.h"
|
||||||
|
|
||||||
#include "lpc313x_syscreg.h"
|
#include "lpc31_syscreg.h"
|
||||||
#include "lpc313x_cgudrvr.h"
|
#include "lpc31_cgudrvr.h"
|
||||||
#include "lpc313x_internal.h"
|
#include "lpc31_internal.h"
|
||||||
|
|
||||||
#ifdef CONFIG_PAGING
|
#ifdef CONFIG_PAGING
|
||||||
# include <nuttx/page.h>
|
# include <nuttx/page.h>
|
||||||
@@ -90,41 +90,41 @@ extern uint32_t _vector_end; /* End+1 of vector block */
|
|||||||
#ifndef CONFIG_ARCH_ROMPGTABLE
|
#ifndef CONFIG_ARCH_ROMPGTABLE
|
||||||
static const struct section_mapping_s section_mapping[] =
|
static const struct section_mapping_s section_mapping[] =
|
||||||
{
|
{
|
||||||
{ LPC313X_SHADOWSPACE_PSECTION, LPC313X_SHADOWSPACE_VSECTION,
|
{ LPC31_SHADOWSPACE_PSECTION, LPC31_SHADOWSPACE_VSECTION,
|
||||||
LPC313X_SHADOWSPACE_MMUFLAGS, LPC313X_SHADOWSPACE_NSECTIONS},
|
LPC31_SHADOWSPACE_MMUFLAGS, LPC31_SHADOWSPACE_NSECTIONS},
|
||||||
#ifndef CONFIG_PAGING /* SRAM is already fully mapped */
|
#ifndef CONFIG_PAGING /* SRAM is already fully mapped */
|
||||||
{ LPC313X_INTSRAM_PSECTION, LPC313X_INTSRAM_VSECTION,
|
{ LPC31_INTSRAM_PSECTION, LPC31_INTSRAM_VSECTION,
|
||||||
LPC313X_INTSRAM_MMUFLAGS, LPC313X_INTSRAM_NSECTIONS},
|
LPC31_INTSRAM_MMUFLAGS, LPC31_INTSRAM_NSECTIONS},
|
||||||
#endif
|
#endif
|
||||||
#ifdef CONFIG_ARCH_ROMPGTABLE
|
#ifdef CONFIG_ARCH_ROMPGTABLE
|
||||||
{ LPC313X_INTSROM0_PSECTION, LPC313X_INTSROM0_VSECTION,
|
{ LPC31_INTSROM0_PSECTION, LPC31_INTSROM0_VSECTION,
|
||||||
LPC313X_INTSROM_MMUFLAGS, LPC313X_INTSROM0_NSECTIONS},
|
LPC31_INTSROM_MMUFLAGS, LPC31_INTSROM0_NSECTIONS},
|
||||||
#endif
|
#endif
|
||||||
{ LPC313X_APB01_PSECTION, LPC313X_APB01_VSECTION,
|
{ LPC31_APB01_PSECTION, LPC31_APB01_VSECTION,
|
||||||
LPC313X_APB01_MMUFLAGS, LPC313X_APB01_NSECTIONS},
|
LPC31_APB01_MMUFLAGS, LPC31_APB01_NSECTIONS},
|
||||||
{ LPC313X_APB2_PSECTION, LPC313X_APB2_VSECTION,
|
{ LPC31_APB2_PSECTION, LPC31_APB2_VSECTION,
|
||||||
LPC313X_APB2_MMUFLAGS, LPC313X_APB2_NSECTIONS},
|
LPC31_APB2_MMUFLAGS, LPC31_APB2_NSECTIONS},
|
||||||
{ LPC313X_APB3_PSECTION, LPC313X_APB3_VSECTION,
|
{ LPC31_APB3_PSECTION, LPC31_APB3_VSECTION,
|
||||||
LPC313X_APB3_MMUFLAGS, LPC313X_APB3_NSECTIONS},
|
LPC31_APB3_MMUFLAGS, LPC31_APB3_NSECTIONS},
|
||||||
{ LPC313X_APB4MPMC_PSECTION, LPC313X_APB4MPMC_VSECTION,
|
{ LPC31_APB4MPMC_PSECTION, LPC31_APB4MPMC_VSECTION,
|
||||||
LPC313X_APB4MPMC_MMUFLAGS, LPC313X_APB4MPMC_NSECTIONS},
|
LPC31_APB4MPMC_MMUFLAGS, LPC31_APB4MPMC_NSECTIONS},
|
||||||
{ LPC313X_MCI_PSECTION, LPC313X_MCI_VSECTION,
|
{ LPC31_MCI_PSECTION, LPC31_MCI_VSECTION,
|
||||||
LPC313X_MCI_MMUFLAGS, LPC313X_MCI_NSECTIONS},
|
LPC31_MCI_MMUFLAGS, LPC31_MCI_NSECTIONS},
|
||||||
{ LPC313X_USBOTG_PSECTION, LPC313X_USBOTG_VSECTION,
|
{ LPC31_USBOTG_PSECTION, LPC31_USBOTG_VSECTION,
|
||||||
LPC313X_USBOTG_MMUFLAGS, LPC313X_USBOTG_NSECTIONS},
|
LPC31_USBOTG_MMUFLAGS, LPC31_USBOTG_NSECTIONS},
|
||||||
#if defined(CONFIG_LPC313X_EXTSRAM0) && CONFIG_LPC313X_EXTSRAM0SIZE > 0
|
#if defined(CONFIG_LPC31_EXTSRAM0) && CONFIG_LPC31_EXTSRAM0SIZE > 0
|
||||||
{ LPC313X_EXTSRAM_PSECTION, LPC313X_EXTSRAM_VSECTION,
|
{ LPC31_EXTSRAM_PSECTION, LPC31_EXTSRAM_VSECTION,
|
||||||
LPC313X_EXTSDRAM_MMUFLAGS, LPC313X_EXTSRAM_NSECTIONS},
|
LPC31_EXTSDRAM_MMUFLAGS, LPC31_EXTSRAM_NSECTIONS},
|
||||||
#endif
|
#endif
|
||||||
#if defined(CONFIG_LPC313X_EXTSDRAM) && CONFIG_LPC313X_EXTSDRAMSIZE > 0
|
#if defined(CONFIG_LPC31_EXTSDRAM) && CONFIG_LPC31_EXTSDRAMSIZE > 0
|
||||||
{ LPC313X_EXTSDRAM0_PSECTION, LPC313X_EXTSDRAM0_VSECTION,
|
{ LPC31_EXTSDRAM0_PSECTION, LPC31_EXTSDRAM0_VSECTION,
|
||||||
LPC313X_EXTSDRAM_MMUFLAGS, LPC313X_EXTSDRAM0_NSECTIONS},
|
LPC31_EXTSDRAM_MMUFLAGS, LPC31_EXTSDRAM0_NSECTIONS},
|
||||||
#endif
|
#endif
|
||||||
{ LPC313X_INTC_PSECTION, LPC313X_INTC_VSECTION,
|
{ LPC31_INTC_PSECTION, LPC31_INTC_VSECTION,
|
||||||
LPC313X_INTC_MMUFLAGS, LPC313X_INTC_NSECTIONS},
|
LPC31_INTC_MMUFLAGS, LPC31_INTC_NSECTIONS},
|
||||||
#ifdef CONFIG_LPC313X_EXTNAND
|
#ifdef CONFIG_LPC31_EXTNAND
|
||||||
{ LPC313X_NAND_PSECTION, LPC313X_NAND_VSECTION
|
{ LPC31_NAND_PSECTION, LPC31_NAND_VSECTION
|
||||||
LPC313X_NAND_MMUFLAGS, LPC313X_NAND_NSECTIONS},
|
LPC31_NAND_MMUFLAGS, LPC31_NAND_NSECTIONS},
|
||||||
#endif
|
#endif
|
||||||
};
|
};
|
||||||
#define NMAPPINGS (sizeof(section_mapping) / sizeof(struct section_mapping_s))
|
#define NMAPPINGS (sizeof(section_mapping) / sizeof(struct section_mapping_s))
|
||||||
@@ -251,8 +251,8 @@ static void up_vectorpermissions(uint32_t mmuflags)
|
|||||||
#if !defined(CONFIG_ARCH_ROMPGTABLE) && !defined(CONFIG_ARCH_LOWVECTORS)
|
#if !defined(CONFIG_ARCH_ROMPGTABLE) && !defined(CONFIG_ARCH_LOWVECTORS)
|
||||||
static void up_vectormapping(void)
|
static void up_vectormapping(void)
|
||||||
{
|
{
|
||||||
uint32_t vector_paddr = LPC313X_VECTOR_PADDR;
|
uint32_t vector_paddr = LPC31_VECTOR_PADDR;
|
||||||
uint32_t vector_vaddr = LPC313X_VECTOR_VADDR;
|
uint32_t vector_vaddr = LPC31_VECTOR_VADDR;
|
||||||
uint32_t end_paddr = vector_paddr + VECTOR_TABLE_SIZE;
|
uint32_t end_paddr = vector_paddr + VECTOR_TABLE_SIZE;
|
||||||
|
|
||||||
/* We want to keep our interrupt vectors and interrupt-related logic in zero-wait
|
/* We want to keep our interrupt vectors and interrupt-related logic in zero-wait
|
||||||
@@ -270,7 +270,7 @@ static void up_vectormapping(void)
|
|||||||
|
|
||||||
/* Now set the level 1 descriptor to refer to the level 2 coarse page table. */
|
/* Now set the level 1 descriptor to refer to the level 2 coarse page table. */
|
||||||
|
|
||||||
up_setlevel1entry(PGTABLE_L2_COARSE_PBASE, LPC313X_VECTOR_VCOARSE,
|
up_setlevel1entry(PGTABLE_L2_COARSE_PBASE, LPC31_VECTOR_VCOARSE,
|
||||||
MMU_L1_VECTORFLAGS);
|
MMU_L1_VECTORFLAGS);
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
@@ -300,14 +300,14 @@ static void up_copyvectorblock(void)
|
|||||||
/* Copy the vectors into ISRAM at the address that will be mapped to the vector
|
/* Copy the vectors into ISRAM at the address that will be mapped to the vector
|
||||||
* address:
|
* address:
|
||||||
*
|
*
|
||||||
* LPC313X_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM
|
* LPC31_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM
|
||||||
* LPC313X_VECTOR_VSRAM - Virtual address of vector table in SRAM
|
* LPC31_VECTOR_VSRAM - Virtual address of vector table in SRAM
|
||||||
* LPC313X_VECTOR_VADDR - Virtual address of vector table (0x00000000 or 0xffff0000)
|
* LPC31_VECTOR_VADDR - Virtual address of vector table (0x00000000 or 0xffff0000)
|
||||||
*/
|
*/
|
||||||
|
|
||||||
src = (uint32_t*)&_vector_start;
|
src = (uint32_t*)&_vector_start;
|
||||||
end = (uint32_t*)&_vector_end;
|
end = (uint32_t*)&_vector_end;
|
||||||
dest = (uint32_t*)LPC313X_VECTOR_VSRAM;
|
dest = (uint32_t*)LPC31_VECTOR_VSRAM;
|
||||||
|
|
||||||
while (src < end)
|
while (src < end)
|
||||||
{
|
{
|
||||||
@@ -320,12 +320,12 @@ static void up_copyvectorblock(void)
|
|||||||
up_vectorpermissions(MMU_L2_VECTROFLAGS);
|
up_vectorpermissions(MMU_L2_VECTROFLAGS);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Then set the LPC313x shadow register, LPC313X_SYSCREG_ARM926SHADOWPTR, so that
|
/* Then set the LPC313x shadow register, LPC31_SYSCREG_ARM926SHADOWPTR, so that
|
||||||
* the vector table is mapped to address 0x0000:0000 - NOTE: that there is not yet
|
* the vector table is mapped to address 0x0000:0000 - NOTE: that there is not yet
|
||||||
* full support for the vector table at address 0xffff0000.
|
* full support for the vector table at address 0xffff0000.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
putreg32(LPC313X_VECTOR_PADDR, LPC313X_SYSCREG_ARM926SHADOWPTR);
|
putreg32(LPC31_VECTOR_PADDR, LPC31_SYSCREG_ARM926SHADOWPTR);
|
||||||
}
|
}
|
||||||
|
|
||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
@@ -366,24 +366,24 @@ void up_boot(void)
|
|||||||
|
|
||||||
/* Reset all clocks */
|
/* Reset all clocks */
|
||||||
|
|
||||||
lpc313x_resetclks();
|
lpc31_resetclks();
|
||||||
|
|
||||||
/* Initialize the PLLs */
|
/* Initialize the PLLs */
|
||||||
|
|
||||||
lpc313x_hp1pllconfig();
|
lpc31_hp1pllconfig();
|
||||||
lpc313x_hp0pllconfig();
|
lpc31_hp0pllconfig();
|
||||||
|
|
||||||
/* Initialize clocking to settings provided by board-specific logic */
|
/* Initialize clocking to settings provided by board-specific logic */
|
||||||
|
|
||||||
lpc313x_clkinit(&g_boardclks);
|
lpc31_clkinit(&g_boardclks);
|
||||||
|
|
||||||
/* Map first 4KB of ARM space to ISRAM area */
|
/* Map first 4KB of ARM space to ISRAM area */
|
||||||
|
|
||||||
putreg32(LPC313X_INTSRAM0_PADDR, LPC313X_SYSCREG_ARM926SHADOWPTR);
|
putreg32(LPC31_INTSRAM0_PADDR, LPC31_SYSCREG_ARM926SHADOWPTR);
|
||||||
|
|
||||||
/* Perform common, low-level chip initialization (might do nothing) */
|
/* Perform common, low-level chip initialization (might do nothing) */
|
||||||
|
|
||||||
lpc313x_lowsetup();
|
lpc31_lowsetup();
|
||||||
|
|
||||||
/* Perform early serial initialization if we are going to use the serial driver */
|
/* Perform early serial initialization if we are going to use the serial driver */
|
||||||
|
|
||||||
@@ -393,5 +393,5 @@ void up_boot(void)
|
|||||||
|
|
||||||
/* Perform board-specific initialization */
|
/* Perform board-specific initialization */
|
||||||
|
|
||||||
lpc313x_boardinitialize();
|
lpc31_boardinitialize();
|
||||||
}
|
}
|
||||||
Executable
+1626
File diff suppressed because it is too large
Load Diff
@@ -1,5 +1,5 @@
|
|||||||
/************************************************************************
|
/************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_cgudrvr.h
|
* arch/arm/src/lpc31xx/lpc31_cgudrvr.h
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -37,8 +37,8 @@
|
|||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
#ifndef __ARCH_ARM_SRC_LPC313X_CGUDRVR_H
|
#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_CGUDRVR_H
|
||||||
#define __ARCH_ARM_SRC_LPC313X_CGUDRVR_H
|
#define __ARCH_ARM_SRC_LPC31XX_LPC31_CGUDRVR_H
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Included Files
|
* Included Files
|
||||||
@@ -50,7 +50,7 @@
|
|||||||
#include <stdbool.h>
|
#include <stdbool.h>
|
||||||
|
|
||||||
#include "up_arch.h"
|
#include "up_arch.h"
|
||||||
#include "lpc313x_cgu.h"
|
#include "lpc31_cgu.h"
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -60,7 +60,7 @@
|
|||||||
|
|
||||||
#define _RBIT(x,b) (1<<((x)-(b)))
|
#define _RBIT(x,b) (1<<((x)-(b)))
|
||||||
|
|
||||||
/* Clock ID ranges (see enum lpc313x_clockid_e) *************************************************/
|
/* Clock ID ranges (see enum lpc31_clockid_e) *************************************************/
|
||||||
|
|
||||||
#define CLKID_FIRST CLKID_APB0CLK
|
#define CLKID_FIRST CLKID_APB0CLK
|
||||||
#define CLKID_SYSBASE_FIRST CLKID_APB0CLK /* Domain 0: SYS_BASE */
|
#define CLKID_SYSBASE_FIRST CLKID_APB0CLK /* Domain 0: SYS_BASE */
|
||||||
@@ -193,7 +193,7 @@ extern "C" {
|
|||||||
|
|
||||||
/* Clock domains */
|
/* Clock domains */
|
||||||
|
|
||||||
enum lpc313x_domainid_e
|
enum lpc31_domainid_e
|
||||||
{
|
{
|
||||||
DOMAINID_SYS = 0, /* Domain 0: SYS_BASE */
|
DOMAINID_SYS = 0, /* Domain 0: SYS_BASE */
|
||||||
DOMAINID_AHB0APB0, /* Domain 1: AHB0APB0_BASE */
|
DOMAINID_AHB0APB0, /* Domain 1: AHB0APB0_BASE */
|
||||||
@@ -210,10 +210,10 @@ enum lpc313x_domainid_e
|
|||||||
};
|
};
|
||||||
|
|
||||||
/* Clock IDs -- These are indices must correspond to the register
|
/* Clock IDs -- These are indices must correspond to the register
|
||||||
* offsets in lpc313x_cgu.h
|
* offsets in lpc31_cgu.h
|
||||||
*/
|
*/
|
||||||
|
|
||||||
enum lpc313x_clockid_e
|
enum lpc31_clockid_e
|
||||||
{
|
{
|
||||||
/* Domain 0: SYS_BASE */
|
/* Domain 0: SYS_BASE */
|
||||||
|
|
||||||
@@ -345,7 +345,7 @@ enum lpc313x_clockid_e
|
|||||||
|
|
||||||
/* Indices into the CGU configuration reset control registers */
|
/* Indices into the CGU configuration reset control registers */
|
||||||
|
|
||||||
enum lpc313x_resetid_e
|
enum lpc31_resetid_e
|
||||||
{
|
{
|
||||||
RESETID_APB0RST, /* 0 AHB part of AHB_TO_APB0 bridge (Reserved) */
|
RESETID_APB0RST, /* 0 AHB part of AHB_TO_APB0 bridge (Reserved) */
|
||||||
RESETID_AHB2APB0RST, /* 1 APB part of AHB_TO_APB0 bridge (Reserved) */
|
RESETID_AHB2APB0RST, /* 1 APB part of AHB_TO_APB0 bridge (Reserved) */
|
||||||
@@ -407,7 +407,7 @@ enum lpc313x_resetid_e
|
|||||||
|
|
||||||
/* This structure describes one CGU fractional divider configuration */
|
/* This structure describes one CGU fractional divider configuration */
|
||||||
|
|
||||||
struct lpc313x_fdivconfig_s
|
struct lpc31_fdivconfig_s
|
||||||
{
|
{
|
||||||
uint8_t stretch; /* Fractional divider stretch enable. */
|
uint8_t stretch; /* Fractional divider stretch enable. */
|
||||||
uint8_t n; /* Fractional divider nominal nominator */
|
uint8_t n; /* Fractional divider nominal nominator */
|
||||||
@@ -416,9 +416,9 @@ struct lpc313x_fdivconfig_s
|
|||||||
|
|
||||||
/* The structure describes the configuration of one CGU sub-domain */
|
/* The structure describes the configuration of one CGU sub-domain */
|
||||||
|
|
||||||
struct lpc313x_subdomainconfig_s
|
struct lpc31_subdomainconfig_s
|
||||||
{
|
{
|
||||||
struct lpc313x_fdivconfig_s fdiv; /* Fractional divider settings */
|
struct lpc31_fdivconfig_s fdiv; /* Fractional divider settings */
|
||||||
uint32_t clkset; /* Bitset of all clocks in the sub-domain */
|
uint32_t clkset; /* Bitset of all clocks in the sub-domain */
|
||||||
};
|
};
|
||||||
|
|
||||||
@@ -426,54 +426,54 @@ struct lpc313x_subdomainconfig_s
|
|||||||
* configuration of every clock domain.
|
* configuration of every clock domain.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
struct lpc313x_clkinit_s
|
struct lpc31_clkinit_s
|
||||||
{
|
{
|
||||||
struct
|
struct
|
||||||
{
|
{
|
||||||
uint8_t finsel;
|
uint8_t finsel;
|
||||||
struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE0_CNT];
|
struct lpc31_subdomainconfig_s sub[FRACDIV_BASE0_CNT];
|
||||||
} domain0;
|
} domain0;
|
||||||
|
|
||||||
struct
|
struct
|
||||||
{
|
{
|
||||||
uint8_t finsel;
|
uint8_t finsel;
|
||||||
struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE1_CNT];
|
struct lpc31_subdomainconfig_s sub[FRACDIV_BASE1_CNT];
|
||||||
} domain1;
|
} domain1;
|
||||||
|
|
||||||
struct
|
struct
|
||||||
{
|
{
|
||||||
uint8_t finsel;
|
uint8_t finsel;
|
||||||
struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE2_CNT];
|
struct lpc31_subdomainconfig_s sub[FRACDIV_BASE2_CNT];
|
||||||
} domain2;
|
} domain2;
|
||||||
|
|
||||||
struct
|
struct
|
||||||
{
|
{
|
||||||
uint8_t finsel;
|
uint8_t finsel;
|
||||||
struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE3_CNT];
|
struct lpc31_subdomainconfig_s sub[FRACDIV_BASE3_CNT];
|
||||||
} domain3;
|
} domain3;
|
||||||
|
|
||||||
struct
|
struct
|
||||||
{
|
{
|
||||||
uint8_t finsel;
|
uint8_t finsel;
|
||||||
struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE4_CNT];
|
struct lpc31_subdomainconfig_s sub[FRACDIV_BASE4_CNT];
|
||||||
} domain4;
|
} domain4;
|
||||||
|
|
||||||
struct
|
struct
|
||||||
{
|
{
|
||||||
uint8_t finsel;
|
uint8_t finsel;
|
||||||
struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE5_CNT];
|
struct lpc31_subdomainconfig_s sub[FRACDIV_BASE5_CNT];
|
||||||
} domain5;
|
} domain5;
|
||||||
|
|
||||||
struct
|
struct
|
||||||
{
|
{
|
||||||
uint8_t finsel;
|
uint8_t finsel;
|
||||||
struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE6_CNT];
|
struct lpc31_subdomainconfig_s sub[FRACDIV_BASE6_CNT];
|
||||||
} domain6;
|
} domain6;
|
||||||
|
|
||||||
struct
|
struct
|
||||||
{
|
{
|
||||||
uint8_t finsel;
|
uint8_t finsel;
|
||||||
struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE7_CNT];
|
struct lpc31_subdomainconfig_s sub[FRACDIV_BASE7_CNT];
|
||||||
} domain7;
|
} domain7;
|
||||||
|
|
||||||
struct
|
struct
|
||||||
@@ -489,7 +489,7 @@ struct lpc313x_clkinit_s
|
|||||||
struct
|
struct
|
||||||
{
|
{
|
||||||
uint8_t finsel;
|
uint8_t finsel;
|
||||||
struct lpc313x_subdomainconfig_s sub[FRACDIV_BASE10_CNT];
|
struct lpc31_subdomainconfig_s sub[FRACDIV_BASE10_CNT];
|
||||||
} domain10;
|
} domain10;
|
||||||
|
|
||||||
struct
|
struct
|
||||||
@@ -501,16 +501,16 @@ struct lpc313x_clkinit_s
|
|||||||
struct
|
struct
|
||||||
{
|
{
|
||||||
uint16_t sel;
|
uint16_t sel;
|
||||||
struct lpc313x_fdivconfig_s cfg;
|
struct lpc31_fdivconfig_s cfg;
|
||||||
} dynfdiv[CGU_NDYNFRACDIV];
|
} dynfdiv[CGU_NDYNFRACDIV];
|
||||||
#endif
|
#endif
|
||||||
};
|
};
|
||||||
|
|
||||||
/* This structure is used to pass PLL configuration data to
|
/* This structure is used to pass PLL configuration data to
|
||||||
* lpc313x_pllconfig()
|
* lpc31_pllconfig()
|
||||||
*/
|
*/
|
||||||
|
|
||||||
struct lpc313x_pllconfig_s
|
struct lpc31_pllconfig_s
|
||||||
{
|
{
|
||||||
uint8_t hppll; /* PLL selection: 0=HPLL0 1=HPLL1 */
|
uint8_t hppll; /* PLL selection: 0=HPLL0 1=HPLL1 */
|
||||||
uint8_t pdec; /* PLL P-divider value: 0-0x7f */
|
uint8_t pdec; /* PLL P-divider value: 0-0x7f */
|
||||||
@@ -534,34 +534,34 @@ struct lpc313x_pllconfig_s
|
|||||||
|
|
||||||
EXTERN uint32_t g_boardfreqin[CGU_NFREQIN];
|
EXTERN uint32_t g_boardfreqin[CGU_NFREQIN];
|
||||||
|
|
||||||
/* This instance of the lpc313x_clkinit_s structure provides the initial,
|
/* This instance of the lpc31_clkinit_s structure provides the initial,
|
||||||
* default clock configuration for the board. Every board must provide
|
* default clock configuration for the board. Every board must provide
|
||||||
* an implementation of g_boardclks. This rather complex structure is
|
* an implementation of g_boardclks. This rather complex structure is
|
||||||
* used by the boot-up logic to configure initial lpc313x clocking.
|
* used by the boot-up logic to configure initial lpc31xx clocking.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
EXTERN const struct lpc313x_clkinit_s g_boardclks;
|
EXTERN const struct lpc31_clkinit_s g_boardclks;
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Inline Functions
|
* Inline Functions
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_getbasefreq
|
* Name: lpc31_getbasefreq
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Return the base frequency associated with a clock domain
|
* Return the base frequency associated with a clock domain
|
||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
static inline uint32_t lpc313x_getbasefreq(enum lpc313x_domainid_e dmnid)
|
static inline uint32_t lpc31_getbasefreq(enum lpc31_domainid_e dmnid)
|
||||||
{
|
{
|
||||||
uint32_t regval;
|
uint32_t regval;
|
||||||
int ndx;
|
int ndx;
|
||||||
|
|
||||||
/* Fetch the SSR register associated with this clock domain */
|
/* Fetch the SSR register associated with this clock domain */
|
||||||
|
|
||||||
regval = getreg32(LPC313X_CGU_SSR((int)dmnid));
|
regval = getreg32(LPC31_CGU_SSR((int)dmnid));
|
||||||
|
|
||||||
/* Extract the last frequency input selection */
|
/* Extract the last frequency input selection */
|
||||||
|
|
||||||
@@ -573,16 +573,16 @@ static inline uint32_t lpc313x_getbasefreq(enum lpc313x_domainid_e dmnid)
|
|||||||
}
|
}
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_enableclock
|
* Name: lpc31_enableclock
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Enable the specified clock
|
* Enable the specified clock
|
||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
static inline void lpc313x_enableclock(enum lpc313x_clockid_e clkid)
|
static inline void lpc31_enableclock(enum lpc31_clockid_e clkid)
|
||||||
{
|
{
|
||||||
uint32_t address = LPC313X_CGU_PCR((int)clkid);
|
uint32_t address = LPC31_CGU_PCR((int)clkid);
|
||||||
uint32_t regval = getreg32(address);
|
uint32_t regval = getreg32(address);
|
||||||
|
|
||||||
regval |= CGU_PCR_RUN;
|
regval |= CGU_PCR_RUN;
|
||||||
@@ -590,16 +590,16 @@ static inline void lpc313x_enableclock(enum lpc313x_clockid_e clkid)
|
|||||||
}
|
}
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_disableclock
|
* Name: lpc31_disableclock
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Disable the specified clock
|
* Disable the specified clock
|
||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
static inline void lpc313x_disableclock(enum lpc313x_clockid_e clkid)
|
static inline void lpc31_disableclock(enum lpc31_clockid_e clkid)
|
||||||
{
|
{
|
||||||
uint32_t address = LPC313X_CGU_PCR((int)clkid);
|
uint32_t address = LPC31_CGU_PCR((int)clkid);
|
||||||
uint32_t regval = getreg32(address);
|
uint32_t regval = getreg32(address);
|
||||||
|
|
||||||
regval &= ~CGU_PCR_RUN;
|
regval &= ~CGU_PCR_RUN;
|
||||||
@@ -611,7 +611,7 @@ static inline void lpc313x_disableclock(enum lpc313x_clockid_e clkid)
|
|||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: lpc313x_defclk
|
* Name: lpc31_defclk
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Enable the specified clock if it is one of the default clocks needed
|
* Enable the specified clock if it is one of the default clocks needed
|
||||||
@@ -619,20 +619,20 @@ static inline void lpc313x_disableclock(enum lpc313x_clockid_e clkid)
|
|||||||
*
|
*
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
EXTERN bool lpc313x_defclk(enum lpc313x_clockid_e clkid);
|
EXTERN bool lpc31_defclk(enum lpc31_clockid_e clkid);
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: lpc313x_resetclks
|
* Name: lpc31_resetclks
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Put all clocks into a known, initial state
|
* Put all clocks into a known, initial state
|
||||||
*
|
*
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
EXTERN void lpc313x_resetclks(void);
|
EXTERN void lpc31_resetclks(void);
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_clkinit
|
* Name: lpc31_clkinit
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Initialize all clock domains based on board-specific clock
|
* Initialize all clock domains based on board-specific clock
|
||||||
@@ -640,24 +640,24 @@ EXTERN void lpc313x_resetclks(void);
|
|||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
EXTERN void lpc313x_clkinit(const struct lpc313x_clkinit_s* cfg);
|
EXTERN void lpc31_clkinit(const struct lpc31_clkinit_s* cfg);
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_fdivinit
|
* Name: lpc31_fdivinit
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Enable and configure (or disable) a fractional divider. For
|
* Enable and configure (or disable) a fractional divider. For
|
||||||
* internal us only... see lpc313x_setfdiv() the externally usable
|
* internal us only... see lpc31_setfdiv() the externally usable
|
||||||
* function.
|
* function.
|
||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
EXTERN uint32_t lpc313x_fdivinit(int fdcndx,
|
EXTERN uint32_t lpc31_fdivinit(int fdcndx,
|
||||||
const struct lpc313x_fdivconfig_s *fdiv,
|
const struct lpc31_fdivconfig_s *fdiv,
|
||||||
bool enable);
|
bool enable);
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_setfdiv
|
* Name: lpc31_setfdiv
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Set/reset subdomain frequency containing the specified clock using
|
* Set/reset subdomain frequency containing the specified clock using
|
||||||
@@ -665,52 +665,52 @@ EXTERN uint32_t lpc313x_fdivinit(int fdcndx,
|
|||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
EXTERN void lpc313x_setfdiv(enum lpc313x_domainid_e dmnid,
|
EXTERN void lpc31_setfdiv(enum lpc31_domainid_e dmnid,
|
||||||
enum lpc313x_clockid_e clkid,
|
enum lpc31_clockid_e clkid,
|
||||||
const struct lpc313x_fdivconfig_s *fdiv);
|
const struct lpc31_fdivconfig_s *fdiv);
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: lpc313x_pllconfig
|
* Name: lpc31_pllconfig
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Re-onfigure the PLL according to the provided selections.
|
* Re-onfigure the PLL according to the provided selections.
|
||||||
*
|
*
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
EXTERN void lpc313x_pllconfig(const struct lpc313x_pllconfig_s * const cfg);
|
EXTERN void lpc31_pllconfig(const struct lpc31_pllconfig_s * const cfg);
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_hp0pllconfig
|
* Name: lpc31_hp0pllconfig
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Configure the HP0 PLL according to the board.h default selections.
|
* Configure the HP0 PLL according to the board.h default selections.
|
||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
EXTERN void lpc313x_hp0pllconfig(void);
|
EXTERN void lpc31_hp0pllconfig(void);
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_hp1pllconfig
|
* Name: lpc31_hp1pllconfig
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Configure the HP1 PLL according to the board.h default selections.
|
* Configure the HP1 PLL according to the board.h default selections.
|
||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
EXTERN void lpc313x_hp1pllconfig(void);
|
EXTERN void lpc31_hp1pllconfig(void);
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_softreset
|
* Name: lpc31_softreset
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Perform a soft reset on the specified module.
|
* Perform a soft reset on the specified module.
|
||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
EXTERN void lpc313x_softreset(enum lpc313x_resetid_e resetid);
|
EXTERN void lpc31_softreset(enum lpc31_resetid_e resetid);
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_clkdomain
|
* Name: lpc31_clkdomain
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Given a clock ID, return the ID of the domain in which the clock
|
* Given a clock ID, return the ID of the domain in which the clock
|
||||||
@@ -718,10 +718,10 @@ EXTERN void lpc313x_softreset(enum lpc313x_resetid_e resetid);
|
|||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
EXTERN enum lpc313x_domainid_e lpc313x_clkdomain(enum lpc313x_clockid_e clkid);
|
EXTERN enum lpc31_domainid_e lpc31_clkdomain(enum lpc31_clockid_e clkid);
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_esrndx
|
* Name: lpc31_esrndx
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Given a clock ID, return the index of the corresponding ESR
|
* Given a clock ID, return the index of the corresponding ESR
|
||||||
@@ -740,10 +740,10 @@ EXTERN enum lpc313x_domainid_e lpc313x_clkdomain(enum lpc313x_clockid_e clkid);
|
|||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
EXTERN int lpc313x_esrndx(enum lpc313x_clockid_e clkid);
|
EXTERN int lpc31_esrndx(enum lpc31_clockid_e clkid);
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_bcrndx
|
* Name: lpc31_bcrndx
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Only 5 of the 12 domains have an associated BCR register. This
|
* Only 5 of the 12 domains have an associated BCR register. This
|
||||||
@@ -752,10 +752,10 @@ EXTERN int lpc313x_esrndx(enum lpc313x_clockid_e clkid);
|
|||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
EXTERN int lpc313x_bcrndx(enum lpc313x_domainid_e dmnid);
|
EXTERN int lpc31_bcrndx(enum lpc31_domainid_e dmnid);
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_fdcndx
|
* Name: lpc31_fdcndx
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Given a clock ID and its domain ID, return the index of the
|
* Given a clock ID and its domain ID, return the index of the
|
||||||
@@ -764,22 +764,22 @@ EXTERN int lpc313x_bcrndx(enum lpc313x_domainid_e dmnid);
|
|||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
EXTERN int lpc313x_fdcndx(enum lpc313x_clockid_e clkid,
|
EXTERN int lpc31_fdcndx(enum lpc31_clockid_e clkid,
|
||||||
enum lpc313x_domainid_e dmnid);
|
enum lpc31_domainid_e dmnid);
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_selectfreqin
|
* Name: lpc31_selectfreqin
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Set the base frequency source selection for with a clock domain
|
* Set the base frequency source selection for with a clock domain
|
||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
EXTERN void lpc313x_selectfreqin(enum lpc313x_domainid_e dmnid,
|
EXTERN void lpc31_selectfreqin(enum lpc31_domainid_e dmnid,
|
||||||
uint32_t finsel);
|
uint32_t finsel);
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_clkfreq
|
* Name: lpc31_clkfreq
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Given a clock ID and its domain ID, return the frequency of the
|
* Given a clock ID and its domain ID, return the frequency of the
|
||||||
@@ -787,28 +787,28 @@ EXTERN void lpc313x_selectfreqin(enum lpc313x_domainid_e dmnid,
|
|||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
EXTERN uint32_t lpc313x_clkfreq(enum lpc313x_clockid_e clkid,
|
EXTERN uint32_t lpc31_clkfreq(enum lpc31_clockid_e clkid,
|
||||||
enum lpc313x_domainid_e dmnid);
|
enum lpc31_domainid_e dmnid);
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_enableexten
|
* Name: lpc31_enableexten
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Enable external enabling for the the specified possible clocks.
|
* Enable external enabling for the the specified possible clocks.
|
||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
EXTERN void lpc313x_enableexten(enum lpc313x_clockid_e clkid);
|
EXTERN void lpc31_enableexten(enum lpc31_clockid_e clkid);
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_disableexten
|
* Name: lpc31_disableexten
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Disable external enabling for the the specified possible clocks.
|
* Disable external enabling for the the specified possible clocks.
|
||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
EXTERN void lpc313x_disableexten(enum lpc313x_clockid_e clkid);
|
EXTERN void lpc31_disableexten(enum lpc31_clockid_e clkid);
|
||||||
|
|
||||||
#undef EXTERN
|
#undef EXTERN
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
@@ -816,4 +816,4 @@ EXTERN void lpc313x_disableexten(enum lpc313x_clockid_e clkid);
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif /* __ASSEMBLY__ */
|
#endif /* __ASSEMBLY__ */
|
||||||
#endif /* __ARCH_ARM_SRC_LPC313X_CGUDRVR_H */
|
#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_CGUDRVR_H */
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/************************************************************************
|
/************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_clkdomain.c
|
* arch/arm/src/lpc31xx/lpc31_clkdomain.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -45,7 +45,7 @@
|
|||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
|
|
||||||
#include "up_arch.h"
|
#include "up_arch.h"
|
||||||
#include "lpc313x_cgudrvr.h"
|
#include "lpc31_cgudrvr.h"
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -64,7 +64,7 @@
|
|||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_clkdomain
|
* Name: lpc31_clkdomain
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Given a clock ID, return the ID of the domain in which the clock
|
* Given a clock ID, return the ID of the domain in which the clock
|
||||||
@@ -72,7 +72,7 @@
|
|||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
enum lpc313x_domainid_e lpc313x_clkdomain(enum lpc313x_clockid_e clkid)
|
enum lpc31_domainid_e lpc31_clkdomain(enum lpc31_clockid_e clkid)
|
||||||
{
|
{
|
||||||
if (clkid <= CLKID_SYSBASE_LAST) /* Domain 0: SYS_BASE */
|
if (clkid <= CLKID_SYSBASE_LAST) /* Domain 0: SYS_BASE */
|
||||||
{
|
{
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_exten.c
|
* arch/arm/src/lpc31xx/lpc31_exten.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -43,7 +43,7 @@
|
|||||||
|
|
||||||
#include <arch/board/board.h>
|
#include <arch/board/board.h>
|
||||||
|
|
||||||
#include "lpc313x_cgudrvr.h"
|
#include "lpc31_cgudrvr.h"
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -66,14 +66,14 @@
|
|||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: lpc313x_enableexten
|
* Name: lpc31_enableexten
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Enable external enabling for the the specified possible clocks.
|
* Enable external enabling for the the specified possible clocks.
|
||||||
*
|
*
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
void lpc313x_enableexten(enum lpc313x_clockid_e clkid)
|
void lpc31_enableexten(enum lpc31_clockid_e clkid)
|
||||||
{
|
{
|
||||||
uint32_t regaddr;
|
uint32_t regaddr;
|
||||||
uint32_t regval;
|
uint32_t regval;
|
||||||
@@ -92,7 +92,7 @@ void lpc313x_enableexten(enum lpc313x_clockid_e clkid)
|
|||||||
case CLKID_SPIPCLKGATED: /* 57 SPI_PCLK_GATED */
|
case CLKID_SPIPCLKGATED: /* 57 SPI_PCLK_GATED */
|
||||||
case CLKID_SPICLKGATED: /* 90 SPI_CLK_GATED */
|
case CLKID_SPICLKGATED: /* 90 SPI_CLK_GATED */
|
||||||
case CLKID_PCMCLKIP: /* 71 PCM_CLK_IP */
|
case CLKID_PCMCLKIP: /* 71 PCM_CLK_IP */
|
||||||
regaddr = LPC313X_CGU_PCR(clkid);
|
regaddr = LPC31_CGU_PCR(clkid);
|
||||||
regval = getreg32(regaddr);
|
regval = getreg32(regaddr);
|
||||||
regval |= CGU_PCR_EXTENEN;
|
regval |= CGU_PCR_EXTENEN;
|
||||||
putreg32(regval, regaddr);
|
putreg32(regval, regaddr);
|
||||||
@@ -103,20 +103,20 @@ void lpc313x_enableexten(enum lpc313x_clockid_e clkid)
|
|||||||
*/
|
*/
|
||||||
|
|
||||||
default:
|
default:
|
||||||
lpc313x_disableexten(clkid);
|
lpc31_disableexten(clkid);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: lpc313x_disableexten
|
* Name: lpc31_disableexten
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Disable external enabling for the the specified possible clocks.
|
* Disable external enabling for the the specified possible clocks.
|
||||||
*
|
*
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
void lpc313x_disableexten(enum lpc313x_clockid_e clkid)
|
void lpc31_disableexten(enum lpc31_clockid_e clkid)
|
||||||
{
|
{
|
||||||
uint32_t regaddr;
|
uint32_t regaddr;
|
||||||
uint32_t regval;
|
uint32_t regval;
|
||||||
@@ -140,7 +140,7 @@ void lpc313x_disableexten(enum lpc313x_clockid_e clkid)
|
|||||||
case CLKID_SPICLKGATED: /* 90 SPI_CLK_GATED */
|
case CLKID_SPICLKGATED: /* 90 SPI_CLK_GATED */
|
||||||
case CLKID_PCMCLKIP: /* 71 PCM_CLK_IP */
|
case CLKID_PCMCLKIP: /* 71 PCM_CLK_IP */
|
||||||
case CLKID_LCDPCLK: /* 54 LCD_PCLK */
|
case CLKID_LCDPCLK: /* 54 LCD_PCLK */
|
||||||
regaddr = LPC313X_CGU_PCR(clkid);
|
regaddr = LPC31_CGU_PCR(clkid);
|
||||||
regval = getreg32(regaddr);
|
regval = getreg32(regaddr);
|
||||||
regval &= ~CGU_PCR_EXTENEN;
|
regval &= ~CGU_PCR_EXTENEN;
|
||||||
putreg32(regval, regaddr);
|
putreg32(regval, regaddr);
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/************************************************************************
|
/************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_clkfreq.c
|
* arch/arm/src/lpc31xx/lpc31_clkfreq.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -45,7 +45,7 @@
|
|||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
|
|
||||||
#include "up_arch.h"
|
#include "up_arch.h"
|
||||||
#include "lpc313x_cgudrvr.h"
|
#include "lpc31_cgudrvr.h"
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -64,7 +64,7 @@
|
|||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_fdcndx
|
* Name: lpc31_fdcndx
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Given a clock ID and its domain ID, return the frequency of the
|
* Given a clock ID and its domain ID, return the frequency of the
|
||||||
@@ -72,8 +72,8 @@
|
|||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
uint32_t lpc313x_clkfreq(enum lpc313x_clockid_e clkid,
|
uint32_t lpc31_clkfreq(enum lpc31_clockid_e clkid,
|
||||||
enum lpc313x_domainid_e dmnid)
|
enum lpc31_domainid_e dmnid)
|
||||||
{
|
{
|
||||||
uint32_t freq = 0;
|
uint32_t freq = 0;
|
||||||
uint32_t fdcndx;
|
uint32_t fdcndx;
|
||||||
@@ -81,11 +81,11 @@ uint32_t lpc313x_clkfreq(enum lpc313x_clockid_e clkid,
|
|||||||
|
|
||||||
/* Get then fractional divider register index for this clock */
|
/* Get then fractional divider register index for this clock */
|
||||||
|
|
||||||
fdcndx = lpc313x_fdcndx(clkid, dmnid);
|
fdcndx = lpc31_fdcndx(clkid, dmnid);
|
||||||
|
|
||||||
/* Get base frequency for the domain */
|
/* Get base frequency for the domain */
|
||||||
|
|
||||||
freq = lpc313x_getbasefreq(dmnid);
|
freq = lpc31_getbasefreq(dmnid);
|
||||||
|
|
||||||
/* If there is no fractional divider associated with the clodk, then the
|
/* If there is no fractional divider associated with the clodk, then the
|
||||||
* connection is directo and we just return the base frequency.
|
* connection is directo and we just return the base frequency.
|
||||||
@@ -97,10 +97,10 @@ uint32_t lpc313x_clkfreq(enum lpc313x_clockid_e clkid,
|
|||||||
}
|
}
|
||||||
|
|
||||||
/* Read fractional divider control (FDC) register value and double check that
|
/* Read fractional divider control (FDC) register value and double check that
|
||||||
* it is enabled (not necessary since lpc313x_fdcndx() also does this check
|
* it is enabled (not necessary since lpc31_fdcndx() also does this check
|
||||||
*/
|
*/
|
||||||
|
|
||||||
regval = getreg32(LPC313X_CGU_FDC(fdcndx));
|
regval = getreg32(LPC31_CGU_FDC(fdcndx));
|
||||||
if ((regval & CGU_ESR_ESREN) != 0)
|
if ((regval & CGU_ESR_ESREN) != 0)
|
||||||
{
|
{
|
||||||
int32_t msub;
|
int32_t msub;
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_clkinit.c
|
* arch/arm/src/lpc31xx/lpc31_clkinit.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -43,8 +43,8 @@
|
|||||||
|
|
||||||
#include <arch/board/board.h>
|
#include <arch/board/board.h>
|
||||||
|
|
||||||
#include "lpc313x_cgu.h"
|
#include "lpc31_cgu.h"
|
||||||
#include "lpc313x_cgudrvr.h"
|
#include "lpc31_cgudrvr.h"
|
||||||
|
|
||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -56,15 +56,15 @@
|
|||||||
|
|
||||||
/* This structure describes the configuration of one domain */
|
/* This structure describes the configuration of one domain */
|
||||||
|
|
||||||
struct lpc313x_domainconfig_s
|
struct lpc31_domainconfig_s
|
||||||
{
|
{
|
||||||
enum lpc313x_domainid_e dmnid; /* Domain ID */
|
enum lpc31_domainid_e dmnid; /* Domain ID */
|
||||||
uint32_t finsel; /* Frequency input selection */
|
uint32_t finsel; /* Frequency input selection */
|
||||||
uint32_t clk1; /* ID of first clock in the domain */
|
uint32_t clk1; /* ID of first clock in the domain */
|
||||||
uint32_t nclks; /* Number of clocks in the domain */
|
uint32_t nclks; /* Number of clocks in the domain */
|
||||||
uint32_t fdiv1; /* First frequency divider in the domain */
|
uint32_t fdiv1; /* First frequency divider in the domain */
|
||||||
uint32_t nfdiv; /* Number of frequency dividers in the domain */
|
uint32_t nfdiv; /* Number of frequency dividers in the domain */
|
||||||
const struct lpc313x_subdomainconfig_s* sub; /* Sub=domain array */
|
const struct lpc31_subdomainconfig_s* sub; /* Sub=domain array */
|
||||||
};
|
};
|
||||||
|
|
||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
@@ -80,29 +80,29 @@ struct lpc313x_domainconfig_s
|
|||||||
************************************************************************************/
|
************************************************************************************/
|
||||||
|
|
||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* Name: lpc313x_domaininit
|
* Name: lpc31_domaininit
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Initialize one clock domain based on board-specific clock configuration data
|
* Initialize one clock domain based on board-specific clock configuration data
|
||||||
*
|
*
|
||||||
************************************************************************************/
|
************************************************************************************/
|
||||||
|
|
||||||
static void lpc313x_domaininit(struct lpc313x_domainconfig_s* dmn)
|
static void lpc31_domaininit(struct lpc31_domainconfig_s* dmn)
|
||||||
{
|
{
|
||||||
const struct lpc313x_subdomainconfig_s * sub = dmn->sub;
|
const struct lpc31_subdomainconfig_s * sub = dmn->sub;
|
||||||
uint32_t fdivcfg;
|
uint32_t fdivcfg;
|
||||||
uint32_t regaddr;
|
uint32_t regaddr;
|
||||||
uint32_t regval;
|
uint32_t regval;
|
||||||
int fdndx;
|
int fdndx;
|
||||||
int clkndx;
|
int clkndx;
|
||||||
int bcrndx = lpc313x_bcrndx(dmn->dmnid);
|
int bcrndx = lpc31_bcrndx(dmn->dmnid);
|
||||||
int esrndx;
|
int esrndx;
|
||||||
|
|
||||||
if (bcrndx != BCRNDX_INVALID)
|
if (bcrndx != BCRNDX_INVALID)
|
||||||
{
|
{
|
||||||
/* Disable BCR for domain */
|
/* Disable BCR for domain */
|
||||||
|
|
||||||
regaddr = LPC313X_CGU_BCR(bcrndx);
|
regaddr = LPC31_CGU_BCR(bcrndx);
|
||||||
putreg32(0, regaddr);
|
putreg32(0, regaddr);
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -112,7 +112,7 @@ static void lpc313x_domaininit(struct lpc313x_domainconfig_s* dmn)
|
|||||||
{
|
{
|
||||||
/* Set fractional divider confiruation but don't enable it yet */
|
/* Set fractional divider confiruation but don't enable it yet */
|
||||||
|
|
||||||
fdivcfg = lpc313x_fdivinit(fdndx + dmn->fdiv1, &sub->fdiv, false);
|
fdivcfg = lpc31_fdivinit(fdndx + dmn->fdiv1, &sub->fdiv, false);
|
||||||
|
|
||||||
/* Enable frac divider only if it has valid settings */
|
/* Enable frac divider only if it has valid settings */
|
||||||
|
|
||||||
@@ -126,7 +126,7 @@ static void lpc313x_domaininit(struct lpc313x_domainconfig_s* dmn)
|
|||||||
{
|
{
|
||||||
/* Does this clock have an ESR register? */
|
/* Does this clock have an ESR register? */
|
||||||
|
|
||||||
esrndx = lpc313x_esrndx((enum lpc313x_clockid_e)(clkndx + dmn->clk1));
|
esrndx = lpc31_esrndx((enum lpc31_clockid_e)(clkndx + dmn->clk1));
|
||||||
if (esrndx != ESRNDX_INVALID)
|
if (esrndx != ESRNDX_INVALID)
|
||||||
{
|
{
|
||||||
/* Yes.. Check if this clock belongs to this sub-domain */
|
/* Yes.. Check if this clock belongs to this sub-domain */
|
||||||
@@ -135,7 +135,7 @@ static void lpc313x_domaininit(struct lpc313x_domainconfig_s* dmn)
|
|||||||
{
|
{
|
||||||
/* Yes.. configure the clock to use this fractional divider */
|
/* Yes.. configure the clock to use this fractional divider */
|
||||||
|
|
||||||
regaddr = LPC313X_CGU_ESR(esrndx);
|
regaddr = LPC31_CGU_ESR(esrndx);
|
||||||
putreg32((fdndx << CGU_ESR_ESRSEL_SHIFT) | CGU_ESR_ESREN, regaddr);
|
putreg32((fdndx << CGU_ESR_ESRSEL_SHIFT) | CGU_ESR_ESREN, regaddr);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@@ -143,7 +143,7 @@ static void lpc313x_domaininit(struct lpc313x_domainconfig_s* dmn)
|
|||||||
|
|
||||||
/* Enable the fractional divider */
|
/* Enable the fractional divider */
|
||||||
|
|
||||||
regaddr = LPC313X_CGU_FDC(fdndx + dmn->fdiv1);
|
regaddr = LPC31_CGU_FDC(fdndx + dmn->fdiv1);
|
||||||
regval = getreg32(regaddr);
|
regval = getreg32(regaddr);
|
||||||
regval |= CGU_FDC_RUN;
|
regval |= CGU_FDC_RUN;
|
||||||
putreg32(regval, regaddr);
|
putreg32(regval, regaddr);
|
||||||
@@ -154,13 +154,13 @@ static void lpc313x_domaininit(struct lpc313x_domainconfig_s* dmn)
|
|||||||
{
|
{
|
||||||
/* Enable the BCR for domain */
|
/* Enable the BCR for domain */
|
||||||
|
|
||||||
regaddr = LPC313X_CGU_BCR(bcrndx);
|
regaddr = LPC31_CGU_BCR(bcrndx);
|
||||||
putreg32(CGU_BCR_FDRUN, regaddr);
|
putreg32(CGU_BCR_FDRUN, regaddr);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Select input base clock for domain*/
|
/* Select input base clock for domain*/
|
||||||
|
|
||||||
lpc313x_selectfreqin(dmn->dmnid, dmn->finsel);
|
lpc31_selectfreqin(dmn->dmnid, dmn->finsel);
|
||||||
}
|
}
|
||||||
|
|
||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
@@ -168,20 +168,20 @@ static void lpc313x_domaininit(struct lpc313x_domainconfig_s* dmn)
|
|||||||
************************************************************************************/
|
************************************************************************************/
|
||||||
|
|
||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* Name: lpc313x_clkinit
|
* Name: lpc31_clkinit
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Initialize all clock domains based on board-specific clock configuration data
|
* Initialize all clock domains based on board-specific clock configuration data
|
||||||
*
|
*
|
||||||
************************************************************************************/
|
************************************************************************************/
|
||||||
|
|
||||||
void lpc313x_clkinit(const struct lpc313x_clkinit_s* cfg)
|
void lpc31_clkinit(const struct lpc31_clkinit_s* cfg)
|
||||||
{
|
{
|
||||||
struct lpc313x_domainconfig_s domain;
|
struct lpc31_domainconfig_s domain;
|
||||||
|
|
||||||
/* Reset all clocks and connect them to FFAST */
|
/* Reset all clocks and connect them to FFAST */
|
||||||
|
|
||||||
lpc313x_resetclks();
|
lpc31_resetclks();
|
||||||
|
|
||||||
/* Initialize Domain0 = SYS_BASE clocks */
|
/* Initialize Domain0 = SYS_BASE clocks */
|
||||||
|
|
||||||
@@ -192,7 +192,7 @@ void lpc313x_clkinit(const struct lpc313x_clkinit_s* cfg)
|
|||||||
domain.fdiv1 = FRACDIV_BASE0_LOW;
|
domain.fdiv1 = FRACDIV_BASE0_LOW;
|
||||||
domain.nfdiv = FRACDIV_BASE0_CNT;
|
domain.nfdiv = FRACDIV_BASE0_CNT;
|
||||||
domain.sub = cfg->domain0.sub;
|
domain.sub = cfg->domain0.sub;
|
||||||
lpc313x_domaininit(&domain);
|
lpc31_domaininit(&domain);
|
||||||
|
|
||||||
/* Initialize Domain1 = AHB0APB0_BASE clocks */
|
/* Initialize Domain1 = AHB0APB0_BASE clocks */
|
||||||
|
|
||||||
@@ -203,7 +203,7 @@ void lpc313x_clkinit(const struct lpc313x_clkinit_s* cfg)
|
|||||||
domain.fdiv1 = FRACDIV_BASE1_LOW;
|
domain.fdiv1 = FRACDIV_BASE1_LOW;
|
||||||
domain.nfdiv = FRACDIV_BASE1_CNT;
|
domain.nfdiv = FRACDIV_BASE1_CNT;
|
||||||
domain.sub = cfg->domain1.sub;
|
domain.sub = cfg->domain1.sub;
|
||||||
lpc313x_domaininit(&domain);
|
lpc31_domaininit(&domain);
|
||||||
|
|
||||||
/* Initialize Domain2 = AHB0APB1_BASE clocks */
|
/* Initialize Domain2 = AHB0APB1_BASE clocks */
|
||||||
|
|
||||||
@@ -214,7 +214,7 @@ void lpc313x_clkinit(const struct lpc313x_clkinit_s* cfg)
|
|||||||
domain.fdiv1 = FRACDIV_BASE2_LOW;
|
domain.fdiv1 = FRACDIV_BASE2_LOW;
|
||||||
domain.nfdiv = FRACDIV_BASE2_CNT;
|
domain.nfdiv = FRACDIV_BASE2_CNT;
|
||||||
domain.sub = cfg->domain2.sub;
|
domain.sub = cfg->domain2.sub;
|
||||||
lpc313x_domaininit(&domain);
|
lpc31_domaininit(&domain);
|
||||||
|
|
||||||
/* Initialize Domain3 = AHB0APB2_BASE clocks */
|
/* Initialize Domain3 = AHB0APB2_BASE clocks */
|
||||||
|
|
||||||
@@ -225,7 +225,7 @@ void lpc313x_clkinit(const struct lpc313x_clkinit_s* cfg)
|
|||||||
domain.fdiv1 = FRACDIV_BASE3_LOW;
|
domain.fdiv1 = FRACDIV_BASE3_LOW;
|
||||||
domain.nfdiv = FRACDIV_BASE3_CNT;
|
domain.nfdiv = FRACDIV_BASE3_CNT;
|
||||||
domain.sub = cfg->domain3.sub;
|
domain.sub = cfg->domain3.sub;
|
||||||
lpc313x_domaininit(&domain);
|
lpc31_domaininit(&domain);
|
||||||
|
|
||||||
/* Initialize Domain4 = AHB0APB3_BASE clocks */
|
/* Initialize Domain4 = AHB0APB3_BASE clocks */
|
||||||
|
|
||||||
@@ -236,7 +236,7 @@ void lpc313x_clkinit(const struct lpc313x_clkinit_s* cfg)
|
|||||||
domain.fdiv1 = FRACDIV_BASE4_LOW;
|
domain.fdiv1 = FRACDIV_BASE4_LOW;
|
||||||
domain.nfdiv = FRACDIV_BASE4_CNT;
|
domain.nfdiv = FRACDIV_BASE4_CNT;
|
||||||
domain.sub = cfg->domain4.sub;
|
domain.sub = cfg->domain4.sub;
|
||||||
lpc313x_domaininit(&domain);
|
lpc31_domaininit(&domain);
|
||||||
|
|
||||||
/* Initialize Domain5 = PCM_BASE clocks */
|
/* Initialize Domain5 = PCM_BASE clocks */
|
||||||
|
|
||||||
@@ -247,7 +247,7 @@ void lpc313x_clkinit(const struct lpc313x_clkinit_s* cfg)
|
|||||||
domain.fdiv1 = FRACDIV_BASE5_LOW;
|
domain.fdiv1 = FRACDIV_BASE5_LOW;
|
||||||
domain.nfdiv = FRACDIV_BASE5_CNT;
|
domain.nfdiv = FRACDIV_BASE5_CNT;
|
||||||
domain.sub = cfg->domain5.sub;
|
domain.sub = cfg->domain5.sub;
|
||||||
lpc313x_domaininit(&domain);
|
lpc31_domaininit(&domain);
|
||||||
|
|
||||||
/* Initialize Domain6 = UART_BASE clocks */
|
/* Initialize Domain6 = UART_BASE clocks */
|
||||||
|
|
||||||
@@ -258,7 +258,7 @@ void lpc313x_clkinit(const struct lpc313x_clkinit_s* cfg)
|
|||||||
domain.fdiv1 = FRACDIV_BASE6_LOW;
|
domain.fdiv1 = FRACDIV_BASE6_LOW;
|
||||||
domain.nfdiv = FRACDIV_BASE6_CNT;
|
domain.nfdiv = FRACDIV_BASE6_CNT;
|
||||||
domain.sub = cfg->domain6.sub;
|
domain.sub = cfg->domain6.sub;
|
||||||
lpc313x_domaininit(&domain);
|
lpc31_domaininit(&domain);
|
||||||
|
|
||||||
/* Initialize Domain7 = CLK1024FS_BASE clocks */
|
/* Initialize Domain7 = CLK1024FS_BASE clocks */
|
||||||
|
|
||||||
@@ -269,15 +269,15 @@ void lpc313x_clkinit(const struct lpc313x_clkinit_s* cfg)
|
|||||||
domain.fdiv1 = FRACDIV_BASE7_LOW;
|
domain.fdiv1 = FRACDIV_BASE7_LOW;
|
||||||
domain.nfdiv = FRACDIV_BASE7_CNT;
|
domain.nfdiv = FRACDIV_BASE7_CNT;
|
||||||
domain.sub = cfg->domain7.sub;
|
domain.sub = cfg->domain7.sub;
|
||||||
lpc313x_domaininit(&domain);
|
lpc31_domaininit(&domain);
|
||||||
|
|
||||||
/* Initialize Domain8 = I2SRX_BCK0_BASE clocks */
|
/* Initialize Domain8 = I2SRX_BCK0_BASE clocks */
|
||||||
|
|
||||||
lpc313x_selectfreqin(DOMAINID_BCK0, cfg->domain8.finsel);
|
lpc31_selectfreqin(DOMAINID_BCK0, cfg->domain8.finsel);
|
||||||
|
|
||||||
/* Initialize Domain9 = I2SRX_BCK1_BASE clocks */
|
/* Initialize Domain9 = I2SRX_BCK1_BASE clocks */
|
||||||
|
|
||||||
lpc313x_selectfreqin(DOMAINID_BCK1, cfg->domain9.finsel);
|
lpc31_selectfreqin(DOMAINID_BCK1, cfg->domain9.finsel);
|
||||||
|
|
||||||
/* Initialize Domain10 = SPI_BASE clocks */
|
/* Initialize Domain10 = SPI_BASE clocks */
|
||||||
|
|
||||||
@@ -288,11 +288,11 @@ void lpc313x_clkinit(const struct lpc313x_clkinit_s* cfg)
|
|||||||
domain.fdiv1 = FRACDIV_BASE10_LOW;
|
domain.fdiv1 = FRACDIV_BASE10_LOW;
|
||||||
domain.nfdiv = FRACDIV_BASE10_CNT;
|
domain.nfdiv = FRACDIV_BASE10_CNT;
|
||||||
domain.sub = cfg->domain10.sub;
|
domain.sub = cfg->domain10.sub;
|
||||||
lpc313x_domaininit(&domain);
|
lpc31_domaininit(&domain);
|
||||||
|
|
||||||
/* Initialize Domain11 = SYSCLK_O_BASE clocks */
|
/* Initialize Domain11 = SYSCLK_O_BASE clocks */
|
||||||
|
|
||||||
lpc313x_selectfreqin(DOMAINID_SYSCLKO, cfg->domain11.finsel);
|
lpc31_selectfreqin(DOMAINID_SYSCLKO, cfg->domain11.finsel);
|
||||||
|
|
||||||
/* Initialize Dynamic fractional dividers -- to be provided */
|
/* Initialize Dynamic fractional dividers -- to be provided */
|
||||||
}
|
}
|
||||||
@@ -1,6 +1,6 @@
|
|||||||
/********************************************************************************
|
/********************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_decodeirq.c
|
* arch/arm/src/lpc31xx/lpc31_decodeirq.c
|
||||||
* arch/arm/src/chip/lpc313x_decodeirq.c
|
* arch/arm/src/chip/lpc31_decodeirq.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -52,7 +52,7 @@
|
|||||||
#include "os_internal.h"
|
#include "os_internal.h"
|
||||||
#include "up_internal.h"
|
#include "up_internal.h"
|
||||||
|
|
||||||
#include "lpc313x_intc.h"
|
#include "lpc31_intc.h"
|
||||||
|
|
||||||
/********************************************************************************
|
/********************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -89,7 +89,7 @@ void up_decodeirq(uint32_t *regs)
|
|||||||
* following masking should be unnecessary)
|
* following masking should be unnecessary)
|
||||||
*/
|
*/
|
||||||
|
|
||||||
index = getreg32(LPC313X_INTC_VECTOR0) & INTC_VECTOR_INDEX_MASK;
|
index = getreg32(LPC31_INTC_VECTOR0) & INTC_VECTOR_INDEX_MASK;
|
||||||
if (index != 0)
|
if (index != 0)
|
||||||
{
|
{
|
||||||
/* Shift the index so that the range of IRQ numbers are in bits 0-7 (values
|
/* Shift the index so that the range of IRQ numbers are in bits 0-7 (values
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_defclk.c
|
* arch/arm/src/lpc31xx/lpc31_defclk.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -44,7 +44,7 @@
|
|||||||
|
|
||||||
#include <arch/board/board.h>
|
#include <arch/board/board.h>
|
||||||
|
|
||||||
#include "lpc313x_cgudrvr.h"
|
#include "lpc31_cgudrvr.h"
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -67,7 +67,7 @@
|
|||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: lpc313x_defclk
|
* Name: lpc31_defclk
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Enable the specified clock if it is one of the default clocks needed
|
* Enable the specified clock if it is one of the default clocks needed
|
||||||
@@ -75,7 +75,7 @@
|
|||||||
*
|
*
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
bool lpc313x_defclk(enum lpc313x_clockid_e clkid)
|
bool lpc31_defclk(enum lpc31_clockid_e clkid)
|
||||||
{
|
{
|
||||||
|
|
||||||
uint32_t regaddr;
|
uint32_t regaddr;
|
||||||
@@ -103,7 +103,7 @@ bool lpc313x_defclk(enum lpc313x_clockid_e clkid)
|
|||||||
* accordingly.
|
* accordingly.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
regaddr = LPC313X_CGU_PCR((int)clkid);
|
regaddr = LPC31_CGU_PCR((int)clkid);
|
||||||
regval = getreg32(regaddr);
|
regval = getreg32(regaddr);
|
||||||
if (enable)
|
if (enable)
|
||||||
{
|
{
|
||||||
Executable
+423
@@ -0,0 +1,423 @@
|
|||||||
|
/************************************************************************************************
|
||||||
|
* arch/arm/src/lpc31xx/lpc31_dma.h
|
||||||
|
*
|
||||||
|
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||||
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||||
|
* used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||||
|
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||||
|
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_DMA_H
|
||||||
|
#define __ARCH_ARM_SRC_LPC31XX_LPC31_DMA_H
|
||||||
|
|
||||||
|
/************************************************************************************************
|
||||||
|
* Included Files
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
#include <nuttx/config.h>
|
||||||
|
#include "lpc31_memorymap.h"
|
||||||
|
|
||||||
|
/************************************************************************************************
|
||||||
|
* Pre-processor Definitions
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
/* DMA register base address offset into the APB4 domain ****************************************/
|
||||||
|
|
||||||
|
#define LPC31_DMA_VBASE (LPC31_APB4_VADDR+LPC31_APB4_DMA_OFFSET)
|
||||||
|
#define LPC31_DMA_PBASE (LPC31_APB4_PADDR+LPC31_APB4_DMA_OFFSET)
|
||||||
|
|
||||||
|
/* DMA channel offsets (with respect to the DMA register base address) **************************/
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN_OFFSET(n) ((n)*0x020)
|
||||||
|
#define LPC31_DMACHAN0_OFFSET 0x000
|
||||||
|
#define LPC31_DMACHAN1_OFFSET 0x020
|
||||||
|
#define LPC31_DMACHAN2_OFFSET 0x040
|
||||||
|
#define LPC31_DMACHAN3_OFFSET 0x060
|
||||||
|
#define LPC31_DMACHAN4_OFFSET 0x080
|
||||||
|
#define LPC31_DMACHAN5_OFFSET 0x0a0
|
||||||
|
#define LPC31_DMACHAN6_OFFSET 0x0c0
|
||||||
|
#define LPC31_DMACHAN7_OFFSET 0x0e0
|
||||||
|
#define LPC31_DMACHAN8_OFFSET 0x100
|
||||||
|
#define LPC31_DMACHAN9_OFFSET 0x120
|
||||||
|
#define LPC31_DMACHAN10_OFFSET 0x140
|
||||||
|
#define LPC31_DMACHAN11_OFFSET 0x160
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN_ALT_OFFSET(n) (0x200+((n)*0x020))
|
||||||
|
#define LPC31_DMACHAN0_ALT_OFFSET 0x200
|
||||||
|
#define LPC31_DMACHAN1_ALT_OFFSET 0x220
|
||||||
|
#define LPC31_DMACHAN2_ALT_OFFSET 0x240
|
||||||
|
#define LPC31_DMACHAN3_ALT_OFFSET 0x260
|
||||||
|
#define LPC31_DMACHAN4_ALT_OFFSET 0x280
|
||||||
|
#define LPC31_DMACHAN5_ALT_OFFSET 0x2a0
|
||||||
|
#define LPC31_DMACHAN6_ALT_OFFSET 0x2c0
|
||||||
|
#define LPC31_DMACHAN7_ALT_OFFSET 0x2e0
|
||||||
|
#define LPC31_DMACHAN8_ALT_OFFSET 0x300
|
||||||
|
#define LPC31_DMACHAN9_ALT_OFFSET 0x320
|
||||||
|
#define LPC31_DMACHAN10_ALT_OFFSET 0x340
|
||||||
|
#define LPC31_DMACHAN11_ALT_OFFSET 0x360
|
||||||
|
|
||||||
|
/* DMA channel virtual base addresses ***********************************************************/
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN_VBASE(n) (LPC31_DMA_VBASE+LPC31_DMACHAN_OFFSET(n))
|
||||||
|
#define LPC31_DMACHAN0_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN0_OFFSET)
|
||||||
|
#define LPC31_DMACHAN1_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN1_OFFSET)
|
||||||
|
#define LPC31_DMACHAN2_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN2_OFFSET)
|
||||||
|
#define LPC31_DMACHAN3_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN3_OFFSET)
|
||||||
|
#define LPC31_DMACHAN4_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN4_OFFSET)
|
||||||
|
#define LPC31_DMACHAN5_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN5_OFFSET)
|
||||||
|
#define LPC31_DMACHAN6_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN6_OFFSET)
|
||||||
|
#define LPC31_DMACHAN7_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN7_OFFSET)
|
||||||
|
#define LPC31_DMACHAN8_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN8_OFFSET)
|
||||||
|
#define LPC31_DMACHAN9_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN9_OFFSET)
|
||||||
|
#define LPC31_DMACHAN10_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN10_OFFSET)
|
||||||
|
#define LPC31_DMACHAN11_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN11_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN_ALT_VBASE(n) (LPC31_DMA_VBASE+LPC31_DMACHAN_ALT_OFFSET(n))
|
||||||
|
#define LPC31_DMACHAN0_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN0_ALT_OFFSET)
|
||||||
|
#define LPC31_DMACHAN1_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN1_ALT_OFFSET)
|
||||||
|
#define LPC31_DMACHAN2_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN2_ALT_OFFSET)
|
||||||
|
#define LPC31_DMACHAN3_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN3_ALT_OFFSET)
|
||||||
|
#define LPC31_DMACHAN4_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN4_ALT_OFFSET)
|
||||||
|
#define LPC31_DMACHAN5_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN5_ALT_OFFSET)
|
||||||
|
#define LPC31_DMACHAN6_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN6_ALT_OFFSET)
|
||||||
|
#define LPC31_DMACHAN7_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN7_ALT_OFFSET)
|
||||||
|
#define LPC31_DMACHAN8_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN8_ALT_OFFSET)
|
||||||
|
#define LPC31_DMACHAN9_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN9_ALT_OFFSET)
|
||||||
|
#define LPC31_DMACHAN10_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN10_ALT_OFFSET)
|
||||||
|
#define LPC31_DMACHAN11_VBASE (LPC31_DMA_VBASE+LPC31_DMACHAN11_ALT_OFFSET)
|
||||||
|
|
||||||
|
/* DMA channel register offsets (with respect to the DMA channel register base) *****************/
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN_SRCADDR_OFFSET 0x000 /* Source address register of DMA channel */
|
||||||
|
#define LPC31_DMACHAN_DESTADDR_OFFSET 0X004 /* Destination address register of DMA channel */
|
||||||
|
#define LPC31_DMACHAN_XFERLEN_OFFSET 0X008 /* Transfer length register for DMA channel */
|
||||||
|
#define LPC31_DMACHAN_CONFIG_OFFSET 0x00c /* Configuration register for DMA channel */
|
||||||
|
#define LPC31_DMACHAN_ENABLE_OFFSET 0x010 /* Enable register for DMA channel */
|
||||||
|
#define LPC31_DMACHAN_XFERCOUNT_OFFSET 0x01c /* Transfer counter register for DMA channel */
|
||||||
|
|
||||||
|
/* DMA global register offsets (with respect to the DMA register base) *************************/
|
||||||
|
|
||||||
|
#define LPC31_DMA_ALTENABLE_OFFSET 0x400 /* Alternative enable register */
|
||||||
|
#define LPC31_DMA_IRQSTATUSCLR_OFFSET 0x404 /* IRQ status clear register */
|
||||||
|
#define LPC31_DMA_IRQMASK_OFFSET 0x408 /* IRQ mask register */
|
||||||
|
#define LPC31_DMA_TESTSTATUS_OFFSET 0x40c /* Test FIFO response status register */
|
||||||
|
#define LPC31_DMA_SOFTINT_OFFSET 0x410 /* Software interrupt register */
|
||||||
|
|
||||||
|
/* DMA channel register (virtual) addresses *****************************************************/
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN_SRCADDR(n) (LPC31_DMACHAN_VBASE(n)+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN_DESTADDR(n) (LPC31_DMACHAN_VBASE(n)+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN_XFERLEN(n) (LPC31_DMACHAN_VBASE(n)+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN_CONFIG(n) (LPC31_DMACHAN_VBASE(n)+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
#define LPC31_DMACHAN_ENABLE(n) (LPC31_DMACHAN_VBASE(n)+LPC31_DMACHAN_ENABLE_OFFSET)
|
||||||
|
#define LPC31_DMACHAN_XFERCOUNT(n) (LPC31_DMACHAN_VBASE(n)+LPC31_DMACHAN_XFERCOUNT_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN0_SRCADDR (LPC31_DMACHAN0_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN0_DESTADDR (LPC31_DMACHAN0_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN0_XFERLEN (LPC31_DMACHAN0_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN0_CONFIG (LPC31_DMACHAN0_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
#define LPC31_DMACHAN0_ENABLE (LPC31_DMACHAN0_VBASE+LPC31_DMACHAN_ENABLE_OFFSET)
|
||||||
|
#define LPC31_DMACHAN0_XFERCOUNT (LPC31_DMACHAN0_VBASE+LPC31_DMACHAN_XFERCOUNT_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN1_SRCADDR (LPC31_DMACHAN1_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN1_DESTADDR (LPC31_DMACHAN1_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN1_XFERLEN (LPC31_DMACHAN1_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN1_CONFIG (LPC31_DMACHAN1_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
#define LPC31_DMACHAN1_ENABLE (LPC31_DMACHAN1_VBASE+LPC31_DMACHAN_ENABLE_OFFSET)
|
||||||
|
#define LPC31_DMACHAN1_XFERCOUNT (LPC31_DMACHAN1_VBASE+LPC31_DMACHAN_XFERCOUNT_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN2_SRCADDR (LPC31_DMACHAN2_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN2_DESTADDR (LPC31_DMACHAN2_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN2_XFERLEN (LPC31_DMACHAN2_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN2_CONFIG (LPC31_DMACHAN2_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
#define LPC31_DMACHAN2_ENABLE (LPC31_DMACHAN2_VBASE+LPC31_DMACHAN_ENABLE_OFFSET)
|
||||||
|
#define LPC31_DMACHAN2_XFERCOUNT (LPC31_DMACHAN2_VBASE+LPC31_DMACHAN_XFERCOUNT_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN3_SRCADDR (LPC31_DMACHAN3_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN3_DESTADDR (LPC31_DMACHAN3_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN3_XFERLEN (LPC31_DMACHAN3_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN3_CONFIG (LPC31_DMACHAN3_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
#define LPC31_DMACHAN3_ENABLE (LPC31_DMACHAN3_VBASE+LPC31_DMACHAN_ENABLE_OFFSET)
|
||||||
|
#define LPC31_DMACHAN3_XFERCOUNT (LPC31_DMACHAN3_VBASE+LPC31_DMACHAN_XFERCOUNT_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN4_SRCADDR (LPC31_DMACHAN4_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN4_DESTADDR (LPC31_DMACHAN4_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN4_XFERLEN (LPC31_DMACHAN4_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN4_CONFIG (LPC31_DMACHAN4_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
#define LPC31_DMACHAN4_ENABLE (LPC31_DMACHAN4_VBASE+LPC31_DMACHAN_ENABLE_OFFSET)
|
||||||
|
#define LPC31_DMACHAN4_XFERCOUNT (LPC31_DMACHAN4_VBASE+LPC31_DMACHAN_XFERCOUNT_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN5_SRCADDR (LPC31_DMACHAN5_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN5_DESTADDR (LPC31_DMACHAN5_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN5_XFERLEN (LPC31_DMACHAN5_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN5_CONFIG (LPC31_DMACHAN5_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
#define LPC31_DMACHAN5_ENABLE (LPC31_DMACHAN5_VBASE+LPC31_DMACHAN_ENABLE_OFFSET)
|
||||||
|
#define LPC31_DMACHAN5_XFERCOUNT (LPC31_DMACHAN5_VBASE+LPC31_DMACHAN_XFERCOUNT_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN6_SRCADDR (LPC31_DMACHAN6_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN6_DESTADDR (LPC31_DMACHAN6_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN6_XFERLEN (LPC31_DMACHAN6_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN6_CONFIG (LPC31_DMACHAN6_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
#define LPC31_DMACHAN6_ENABLE (LPC31_DMACHAN6_VBASE+LPC31_DMACHAN_ENABLE_OFFSET)
|
||||||
|
#define LPC31_DMACHAN6_XFERCOUNT (LPC31_DMACHAN6_VBASE+LPC31_DMACHAN_XFERCOUNT_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN7_SRCADDR (LPC31_DMACHAN7_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN7_DESTADDR (LPC31_DMACHAN7_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN7_XFERLEN (LPC31_DMACHAN7_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN7_CONFIG (LPC31_DMACHAN7_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
#define LPC31_DMACHAN7_ENABLE (LPC31_DMACHAN7_VBASE+LPC31_DMACHAN_ENABLE_OFFSET)
|
||||||
|
#define LPC31_DMACHAN7_XFERCOUNT (LPC31_DMACHAN7_VBASE+LPC31_DMACHAN_XFERCOUNT_OFFSET)7
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN8_SRCADDR (LPC31_DMACHAN8_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN8_DESTADDR (LPC31_DMACHAN8_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN8_XFERLEN (LPC31_DMACHAN8_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN8_CONFIG (LPC31_DMACHAN8_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
#define LPC31_DMACHAN8_ENABLE (LPC31_DMACHAN8_VBASE+LPC31_DMACHAN_ENABLE_OFFSET)
|
||||||
|
#define LPC31_DMACHAN8_XFERCOUNT (LPC31_DMACHAN8_VBASE+LPC31_DMACHAN_XFERCOUNT_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN9_SRCADDR (LPC31_DMACHAN9_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN9_DESTADDR (LPC31_DMACHAN9_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN9_XFERLEN (LPC31_DMACHAN9_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN9_CONFIG (LPC31_DMACHAN9_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
#define LPC31_DMACHAN9_ENABLE (LPC31_DMACHAN9_VBASE+LPC31_DMACHAN_ENABLE_OFFSET)
|
||||||
|
#define LPC31_DMACHAN9_XFERCOUNT (LPC31_DMACHAN9_VBASE+LPC31_DMACHAN_XFERCOUNT_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN10_SRCADDR (LPC31_DMACHAN10_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN10_DESTADDR (LPC31_DMACHAN10_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN10_XFERLEN (LPC31_DMACHAN10_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN10_CONFIG (LPC31_DMACHAN10_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
#define LPC31_DMACHAN10_ENABLE (LPC31_DMACHAN10_VBASE+LPC31_DMACHAN_ENABLE_OFFSET)
|
||||||
|
#define LPC31_DMACHAN10_XFERCOUNT (LPC31_DMACHAN10_VBASE+LPC31_DMACHAN_XFERCOUNT_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN11_SRCADDR (LPC31_DMACHAN11_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN11_DESTADDR (LPC31_DMACHAN11_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN11_XFERLEN (LPC31_DMACHAN11_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN11_CONFIG (LPC31_DMACHAN11_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
#define LPC31_DMACHAN11_ENABLE (LPC31_DMACHAN11_VBASE+LPC31_DMACHAN_ENABLE_OFFSET)
|
||||||
|
#define LPC31_DMACHAN11_XFERCOUNT (LPC31_DMACHAN11_VBASE+LPC31_DMACHAN_XFERCOUNT_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN_ALT_SRCADDR(n) (LPC31_DMACHAN_ALT_VBASE(n)+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN_ALT_DESTADDR(n) (LPC31_DMACHAN_ALT_VBASE(n)+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN_ALT_XFERLEN(n) (LPC31_DMACHAN_ALT_VBASE(n)+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN_ALT_CONFIG(n) (LPC31_DMACHAN_ALT_VBASE(n)+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN0_ALT_SRCADDR (LPC31_DMACHAN0_ALT_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN0_ALT_DESTADDR (LPC31_DMACHAN0_ALT_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN0_ALT_XFERLEN (LPC31_DMACHAN0_ALT_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN0_ALT_CONFIG (LPC31_DMACHAN0_ALT_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN1_ALT_SRCADDR (LPC31_DMACHAN1_ALT_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN1_ALT_DESTADDR (LPC31_DMACHAN1_ALT_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN1_ALT_XFERLEN (LPC31_DMACHAN1_ALT_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN1_ALT_CONFIG (LPC31_DMACHAN1_ALT_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN2_ALT_SRCADDR (LPC31_DMACHAN2_ALT_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN2_ALT_DESTADDR (LPC31_DMACHAN2_ALT_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN2_ALT_XFERLEN (LPC31_DMACHAN2_ALT_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN2_ALT_CONFIG (LPC31_DMACHAN2_ALT_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN3_ALT_SRCADDR (LPC31_DMACHAN3_ALT_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN3_ALT_DESTADDR (LPC31_DMACHAN3_ALT_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN3_ALT_XFERLEN (LPC31_DMACHAN3_ALT_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN3_ALT_CONFIG (LPC31_DMACHAN3_ALT_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN4_ALT_SRCADDR (LPC31_DMACHAN4_ALT_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN4_ALT_DESTADDR (LPC31_DMACHAN4_ALT_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN4_ALT_XFERLEN (LPC31_DMACHAN4_ALT_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN4_ALT_CONFIG (LPC31_DMACHAN4_ALT_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN5_ALT_SRCADDR (LPC31_DMACHAN5_ALT_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN5_ALT_DESTADDR (LPC31_DMACHAN5_ALT_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN5_ALT_XFERLEN (LPC31_DMACHAN5_ALT_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN5_ALT_CONFIG (LPC31_DMACHAN5_ALT_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN6_ALT_SRCADDR (LPC31_DMACHAN6_ALT_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN6_ALT_DESTADDR (LPC31_DMACHAN6_ALT_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN6_ALT_XFERLEN (LPC31_DMACHAN6_ALT_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN6_ALT_CONFIG (LPC31_DMACHAN6_ALT_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN7_ALT_SRCADDR (LPC31_DMACHAN7_ALT_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN7_ALT_DESTADDR (LPC31_DMACHAN7_ALT_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN7_ALT_XFERLEN (LPC31_DMACHAN7_ALT_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN7_ALT_CONFIG (LPC31_DMACHAN7_ALT_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN8_ALT_SRCADDR (LPC31_DMACHAN8_ALT_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN8_ALT_DESTADDR (LPC31_DMACHAN8_ALT_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN8_ALT_XFERLEN (LPC31_DMACHAN8_ALT_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN8_ALT_CONFIG (LPC31_DMACHAN8_ALT_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN9_ALT_SRCADDR (LPC31_DMACHAN9_ALT_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN9_ALT_DESTADDR (LPC31_DMACHAN9_ALT_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN9_ALT_XFERLEN (LPC31_DMACHAN9_ALT_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN9_ALT_CONFIG (LPC31_DMACHAN9_ALT_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN10_ALT_SRCADDR (LPC31_DMACHAN10_ALT_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN10_ALT_DESTADDR (LPC31_DMACHAN10_ALT_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN10_ALT_XFERLEN (LPC31_DMACHAN10_ALT_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN10_ALT_CONFIG (LPC31_DMACHAN10_ALT_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_DMACHAN11_ALT_SRCADDR (LPC31_DMACHAN11_ALT_VBASE+LPC31_DMACHAN_SRCADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN11_ALT_DESTADDR (LPC31_DMACHAN11_ALT_VBASE+LPC31_DMACHAN_DESTADDR_OFFSET)
|
||||||
|
#define LPC31_DMACHAN11_ALT_XFERLEN (LPC31_DMACHAN11_ALT_VBASE+LPC31_DMACHAN_XFERLEN_OFFSET)
|
||||||
|
#define LPC31_DMACHAN11_ALT_CONFIG (LPC31_DMACHAN11_ALT_VBASE+LPC31_DMACHAN_CONFIG_OFFSET)
|
||||||
|
|
||||||
|
/* DMA global register (virtual) addresses ******************************************************/
|
||||||
|
|
||||||
|
#define LPC31_DMA_ALTENABLE (LPC31_DMA_VBASE+LPC31_DMA_ALTENABLE_OFFSET)
|
||||||
|
#define LPC31_DMA_IRQSTATUSCLR (LPC31_DMA_VBASE+LPC31_DMA_IRQSTATUSCLR_OFFSET)
|
||||||
|
#define LPC31_DMA_IRQMASK (LPC31_DMA_VBASE+LPC31_DMA_IRQMASK_OFFSET)
|
||||||
|
#define LPC31_DMA_TESTSTATUS (LPC31_DMA_VBASE+LPC31_DMA_TESTSTATUS_OFFSET)
|
||||||
|
#define LPC31_DMA_SOFTINT (LPC31_DMA_VBASE+LPC31_DMA_SOFTINT_OFFSET)
|
||||||
|
|
||||||
|
/* DMA channel register bit definitions *********************************************************/
|
||||||
|
|
||||||
|
/* TRANSFER_LENGTH (addresses 0x17000008 (channel 0) to 0x17000168 (channel 11)) */
|
||||||
|
|
||||||
|
#define DMACHAN_XFRLEN_SHIFT (0) /* Bits 0-20: Transfer length */
|
||||||
|
#define DMACHAN_XFRLEN_MASK (0x001fffff << DMACHAN_XFRLEN_SHIFT)
|
||||||
|
|
||||||
|
/* CONFIGURATION (addresses 0x1700000c (channel 0) to 0x1700016c (channel 11)) */
|
||||||
|
|
||||||
|
#define DMACHAN_CONFIG_CIRC (1 << 18) /* Bit 18: Enable circular buffer */
|
||||||
|
#define DMACHAN_CONFIG_COMPCHENABLE (1 << 17) /* Bit 17: Enable companion channel */
|
||||||
|
#define DMACHAN_CONFIG_COMPCHNR_SHIFT (13) /* Bits 13-15: Companion channel number */
|
||||||
|
#define DMACHAN_CONFIG_COMPCHNR_MASK (7 << DMACHAN_CONFIG_COMPCHNR_SHIFT)
|
||||||
|
#define DMACHAN_CONFIG_INVENDIAN (1 << 12) /* Bit 12: Invert endian-ness */
|
||||||
|
#define DMACHAN_CONFIG_XFERSIZE_SHIFT (10) /* Bits 10-11: Transfer size */
|
||||||
|
#define DMACHAN_CONFIG_XFERSIZE_MASK (3 << DMACHAN_CONFIG_XFERSIZE_SHIFT)
|
||||||
|
# define DMACHAN_CONFIG_XFERSIZE_WORDS (0 << DMACHAN_CONFIG_XFERSIZE_SHIFT) /* Transfer words */
|
||||||
|
# define DMACHAN_CONFIG_XFERSIZE_HWORDS (1 << DMACHAN_CONFIG_XFERSIZE_SHIFT) /* Transfer half-words */
|
||||||
|
# define DMACHAN_CONFIG_XFERSIZE_BYTES (2 << DMACHAN_CONFIG_XFERSIZE_SHIFT) /* Transfer bytes */
|
||||||
|
# define DMACHAN_CONFIG_XFERSIZE_BURSTS (3 << DMACHAN_CONFIG_XFERSIZE_SHIFT) /* Transfer bursts */
|
||||||
|
#define DMACHAN_CONFIG_RDSLAVENR_SHIFT (5) /* Bits 5-9: Read slave enable */
|
||||||
|
#define DMACHAN_CONFIG_RDSLAVENR_MASK (31 << DMACHAN_CONFIG_RDSLAVENR_SHIFT)
|
||||||
|
#define DMACHAN_CONFIG_WRSLAVENR_SHIFT (0) /* Bits 0-4: Write slave enable */
|
||||||
|
#define DMACHAN_CONFIG_WRSLAVENR_MASK (31 << DMACHAN_CONFIG_WRSLAVENR_SHIFT)
|
||||||
|
|
||||||
|
/* ENABLE (addresses 0x17000010 (channel 0) to 0x17000170 (channel 11)) */
|
||||||
|
|
||||||
|
#define DMACHAN_ENABLE_BIT (1 << 0) /* Bit 0: Enable */
|
||||||
|
|
||||||
|
/* TRANSFER_COUNTER (addresses 0x1700001v (channel 0) to 0x1700017c (channel 11)) */
|
||||||
|
|
||||||
|
#define DMACHAN_XFRCOUNT_SHIFT (0) /* Bits 0-20: Transfer count */
|
||||||
|
#define DMACHAN_XFRCOUNT_MASK (0x001fffff << DMACHAN_XFRCOUNT_SHIFT)
|
||||||
|
|
||||||
|
/* DMA global register bit definitions **********************************************************/
|
||||||
|
|
||||||
|
/* ALT_ENABLE (address 0x17000400) */
|
||||||
|
|
||||||
|
#define DMA_ALTENABLE_CHAN11 (1 << 11) /* Bit 11: Enable channel 11 */
|
||||||
|
#define DMA_ALTENABLE_CHAN10 (1 << 10) /* Bit 10: Enable channel 10 */
|
||||||
|
#define DMA_ALTENABLE_CHAN9 (1 << 9) /* Bit 9: Enable channel 9 */
|
||||||
|
#define DMA_ALTENABLE_CHAN8 (1 << 8) /* Bit 8: Enable channel 8 */
|
||||||
|
#define DMA_ALTENABLE_CHAN7 (1 << 7) /* Bit 7: Enable channel 7 */
|
||||||
|
#define DMA_ALTENABLE_CHAN6 (1 << 6) /* Bit 6: Enable channel 6 */
|
||||||
|
#define DMA_ALTENABLE_CHAN5 (1 << 5) /* Bit 5: Enable channel 5 */
|
||||||
|
#define DMA_ALTENABLE_CHAN4 (1 << 4) /* Bit 4: Enable channel 4 */
|
||||||
|
#define DMA_ALTENABLE_CHAN3 (1 << 3) /* Bit 3: Enable channel 3 */
|
||||||
|
#define DMA_ALTENABLE_CHAN2 (1 << 2) /* Bit 2: Enable channel 2 */
|
||||||
|
#define DMA_ALTENABLE_CHAN1 (1 << 1) /* Bit 1: Enable channel 1 */
|
||||||
|
#define DMA_ALTENABLE_CHAN0 (1 << 0) /* Bit 0: Enable channel 0 */
|
||||||
|
|
||||||
|
/* IRQ_STATUS_CLR (address 0x17000404) */
|
||||||
|
|
||||||
|
#define DMA_IRQSTATUSCLR_DMAABORT (1 << 31) /* Bit 31: DMA abort */
|
||||||
|
#define DMA_IRQSTATUSCLR_SOFTINT (1 << 30) /* Bit 30: Soft interrupt, scatter gather */
|
||||||
|
#define DMA_IRQSTATUSCLR_HALFWAY11 (1 << 23) /* Bit 23: Chan 11 more than half finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_FINISHED11 (1 << 22) /* Bit 22: Chan 11 finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_HALFWAY10 (1 << 21) /* Bit 21: Chan 10 more than half finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_FINISHED10 (1 << 20) /* Bit 20: Chan 10 finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_HALFWAY9 (1 << 19) /* Bit 19: Chan 9 more than half finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_FINISHED9 (1 << 18) /* Bit 18: Chan 9 finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_HALFWAY8 (1 << 17) /* Bit 17: Chan 8 more than half finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_FINISHED8 (1 << 16) /* Bit 16: Chan 8 finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_HALFWAY7 (1 << 15) /* Bit 15: Chan 7 more than half finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_FINISHED7 (1 << 14) /* Bit 14: Chan 7 finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_HALFWAY6 (1 << 13) /* Bit 13: Chan 6 more than half finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_FINISHED6 (1 << 12) /* Bit 12: Chan 6 finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_HALFWAY5 (1 << 11) /* Bit 11: Chan 5 more than half finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_FINISHED5 (1 << 10) /* Bit 10: Chan 5 finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_HALFWAY4 (1 << 9) /* Bit 9: Chan 4 more than half finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_FINISHED4 (1 << 8) /* Bit 8: Chan 4 finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_HALFWAY3 (1 << 7) /* Bit 7: Chan 3 more than half finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_FINISHED3 (1 << 6) /* Bit 6: Chan 3 finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_HALFWAY2 (1 << 5) /* Bit 5: Chan 2 more than half finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_FINISHED2 (1 << 4) /* Bit 4: Chan 2 finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_HALFWAY1 (1 << 3) /* Bit 3: Chan 1 more than half finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_FINISHED1 (1 << 2) /* Bit 2: Chan 1 finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_HALFWAY0 (1 << 1) /* Bit 1: Chan 0 more than half finished */
|
||||||
|
#define DMA_IRQSTATUSCLR_FINISHED0 (1 << 0) /* Bit 0: Chan 0 finished */
|
||||||
|
|
||||||
|
/* IRQ_MASK (address 0x17000404) */
|
||||||
|
|
||||||
|
#define DMA_IRQMASK_DMAABORT (1 << 31) /* Bit 31: DMA abort */
|
||||||
|
#define DMA_IRQMASK_SOFTINT (1 << 30) /* Bit 30: Soft interrupt, scatter gather */
|
||||||
|
#define DMA_IRQMASK_HALFWAY11 (1 << 23) /* Bit 23: Chan 11 more than half finished */
|
||||||
|
#define DMA_IRQMASK_FINISHED11 (1 << 22) /* Bit 22: Chan 11 finished */
|
||||||
|
#define DMA_IRQMASK_HALFWAY10 (1 << 21) /* Bit 21: Chan 10 more than half finished */
|
||||||
|
#define DMA_IRQMASK_FINISHED10 (1 << 20) /* Bit 20: Chan 10 finished */
|
||||||
|
#define DMA_IRQMASK_HALFWAY9 (1 << 19) /* Bit 19: Chan 9 more than half finished */
|
||||||
|
#define DMA_IRQMASK_FINISHED9 (1 << 18) /* Bit 18: Chan 9 finished */
|
||||||
|
#define DMA_IRQMASK_HALFWAY8 (1 << 17) /* Bit 17: Chan 8 more than half finished */
|
||||||
|
#define DMA_IRQMASK_FINISHED8 (1 << 16) /* Bit 16: Chan 8 finished */
|
||||||
|
#define DMA_IRQMASK_HALFWAY7 (1 << 15) /* Bit 15: Chan 7 more than half finished */
|
||||||
|
#define DMA_IRQMASK_FINISHED7 (1 << 14) /* Bit 14: Chan 7 finished */
|
||||||
|
#define DMA_IRQMASK_HALFWAY6 (1 << 13) /* Bit 13: Chan 6 more than half finished */
|
||||||
|
#define DMA_IRQMASK_FINISHED6 (1 << 12) /* Bit 12: Chan 6 finished */
|
||||||
|
#define DMA_IRQMASK_HALFWAY5 (1 << 11) /* Bit 11: Chan 5 more than half finished */
|
||||||
|
#define DMA_IRQMASK_FINISHED5 (1 << 10) /* Bit 10: Chan 5 finished */
|
||||||
|
#define DMA_IRQMASK_HALFWAY4 (1 << 9) /* Bit 9: Chan 4 more than half finished */
|
||||||
|
#define DMA_IRQMASK_FINISHED4 (1 << 8) /* Bit 8: Chan 4 finished */
|
||||||
|
#define DMA_IRQMASK_HALFWAY3 (1 << 7) /* Bit 7: Chan 3 more than half finished */
|
||||||
|
#define DMA_IRQMASK_FINISHED3 (1 << 6) /* Bit 6: Chan 3 finished */
|
||||||
|
#define DMA_IRQMASK_HALFWAY2 (1 << 5) /* Bit 5: Chan 2 more than half finished */
|
||||||
|
#define DMA_IRQMASK_FINISHED2 (1 << 4) /* Bit 4: Chan 2 finished */
|
||||||
|
#define DMA_IRQMASK_HALFWAY1 (1 << 3) /* Bit 3: Chan 1 more than half finished */
|
||||||
|
#define DMA_IRQMASK_FINISHED1 (1 << 2) /* Bit 2: Chan 1 finished */
|
||||||
|
#define DMA_IRQMASK_HALFWAY0 (1 << 1) /* Bit 1: Chan 0 more than half finished */
|
||||||
|
#define DMA_IRQMASK_FINISHED0 (1 << 0) /* Bit 0: Chan 0 finished */
|
||||||
|
|
||||||
|
/* SOFT_INT (address 0x1700040c) */
|
||||||
|
|
||||||
|
#define DMA_SOFTINT_ENABLE (1 << 0) /* Bit 0: Enable soft interrupt */
|
||||||
|
|
||||||
|
/************************************************************************************************
|
||||||
|
* Public Types
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
/************************************************************************************************
|
||||||
|
* Public Data
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
/************************************************************************************************
|
||||||
|
* Public Functions
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_DMA_H */
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/************************************************************************
|
/************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_esrndx.c
|
* arch/arm/src/lpc31xx/lpc31_esrndx.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -45,7 +45,7 @@
|
|||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
|
|
||||||
#include "up_arch.h"
|
#include "up_arch.h"
|
||||||
#include "lpc313x_cgudrvr.h"
|
#include "lpc31_cgudrvr.h"
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -64,7 +64,7 @@
|
|||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_esrndx
|
* Name: lpc31_esrndx
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Given a clock ID, return the index of the corresponding ESR
|
* Given a clock ID, return the index of the corresponding ESR
|
||||||
@@ -83,7 +83,7 @@
|
|||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
int lpc313x_esrndx(enum lpc313x_clockid_e clkid)
|
int lpc31_esrndx(enum lpc31_clockid_e clkid)
|
||||||
{
|
{
|
||||||
int esrndx = (int)clkid;
|
int esrndx = (int)clkid;
|
||||||
|
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/********************************************************************************************************
|
/********************************************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_evntrtr.h
|
* arch/arm/src/lpc31xx/lpc31_evntrtr.h
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -33,15 +33,15 @@
|
|||||||
*
|
*
|
||||||
********************************************************************************************************/
|
********************************************************************************************************/
|
||||||
|
|
||||||
#ifndef __ARCH_ARM_SRC_LPC313X_EVNTRTR_H
|
#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_EVNTRTR_H
|
||||||
#define __ARCH_ARM_SRC_LPC313X_EVNTRTR_H
|
#define __ARCH_ARM_SRC_LPC31XX_LPC31_EVNTRTR_H
|
||||||
|
|
||||||
/********************************************************************************************************
|
/********************************************************************************************************
|
||||||
* Included Files
|
* Included Files
|
||||||
********************************************************************************************************/
|
********************************************************************************************************/
|
||||||
|
|
||||||
#include <nuttx/config.h>
|
#include <nuttx/config.h>
|
||||||
#include "lpc313x_memorymap.h"
|
#include "lpc31_memorymap.h"
|
||||||
|
|
||||||
/********************************************************************************************************
|
/********************************************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -49,14 +49,14 @@
|
|||||||
|
|
||||||
/* EVNTRTR register base address offset into the APB0 domain ********************************************/
|
/* EVNTRTR register base address offset into the APB0 domain ********************************************/
|
||||||
|
|
||||||
#define LPC313X_EVNTRTR_VBASE (LPC313X_APB0_VADDR+LPC313X_APB0_EVNTRTR_OFFSET)
|
#define LPC31_EVNTRTR_VBASE (LPC31_APB0_VADDR+LPC31_APB0_EVNTRTR_OFFSET)
|
||||||
#define LPC313X_EVNTRTR_PBASE (LPC313X_APB0_PADDR+LPC313X_APB0_EVNTRTR_OFFSET)
|
#define LPC31_EVNTRTR_PBASE (LPC31_APB0_PADDR+LPC31_APB0_EVNTRTR_OFFSET)
|
||||||
|
|
||||||
/* Sizes of things */
|
/* Sizes of things */
|
||||||
|
|
||||||
#define LPC313X_EVNTRTR_NBANKS 4 /* Banks b=0-3 */
|
#define LPC31_EVNTRTR_NBANKS 4 /* Banks b=0-3 */
|
||||||
#define LPC313X_EVNTRTR_NOUTPUTS 5 /* Outputs o=0-4 (incl CGU Wakeup) */
|
#define LPC31_EVNTRTR_NOUTPUTS 5 /* Outputs o=0-4 (incl CGU Wakeup) */
|
||||||
#define LPC313X_EVNTRTR_NEVENTS (32*LPC313X_EVNTRTR_NBANKS)
|
#define LPC31_EVNTRTR_NEVENTS (32*LPC31_EVNTRTR_NBANKS)
|
||||||
|
|
||||||
#define _B(b) ((b)<<2) /* Maps bank number 0-3 to word offset */
|
#define _B(b) ((b)<<2) /* Maps bank number 0-3 to word offset */
|
||||||
#define _O(o) ((o)<<5) /* Maps output to bank group offset */
|
#define _O(o) ((o)<<5) /* Maps output to bank group offset */
|
||||||
@@ -69,46 +69,46 @@
|
|||||||
/* EVNTRTR register offsets (with respect to the EVNTRTR base) ******************************************/
|
/* EVNTRTR register offsets (with respect to the EVNTRTR base) ******************************************/
|
||||||
|
|
||||||
/* 0x0000-0x0bff: Reserved */
|
/* 0x0000-0x0bff: Reserved */
|
||||||
#define LPC313X_EVNTRTR_PEND_OFFSET(b) (0x0c00+_B(b)) /* Input event pending */
|
#define LPC31_EVNTRTR_PEND_OFFSET(b) (0x0c00+_B(b)) /* Input event pending */
|
||||||
#define LPC313X_EVNTRTR_INTCLR_OFFSET(b) (0x0c20+_B(b)) /* Input event clear */
|
#define LPC31_EVNTRTR_INTCLR_OFFSET(b) (0x0c20+_B(b)) /* Input event clear */
|
||||||
#define LPC313X_EVNTRTR_INTSET_OFFSET(b) (0x0c40+_B(b)) /* Input event set */
|
#define LPC31_EVNTRTR_INTSET_OFFSET(b) (0x0c40+_B(b)) /* Input event set */
|
||||||
#define LPC313X_EVNTRTR_MASK_OFFSET(b) (0x0c60+_B(b)) /* Input event mask */
|
#define LPC31_EVNTRTR_MASK_OFFSET(b) (0x0c60+_B(b)) /* Input event mask */
|
||||||
#define LPC313X_EVNTRTR_MASKCLR_OFFSET(b) (0x0c80+_B(b)) /* Input event mask clear */
|
#define LPC31_EVNTRTR_MASKCLR_OFFSET(b) (0x0c80+_B(b)) /* Input event mask clear */
|
||||||
#define LPC313X_EVNTRTR_MASKSET_OFFSET(b) (0x0ca0+_B(b)) /* Input event mask set */
|
#define LPC31_EVNTRTR_MASKSET_OFFSET(b) (0x0ca0+_B(b)) /* Input event mask set */
|
||||||
#define LPC313X_EVNTRTR_APR_OFFSET(b) (0x0cc0+_B(b)) /* Input event activation polarity */
|
#define LPC31_EVNTRTR_APR_OFFSET(b) (0x0cc0+_B(b)) /* Input event activation polarity */
|
||||||
#define LPC313X_EVNTRTR_ATR_OFFSET(b) (0x0ce0+_B(b)) /* Input event activation type */
|
#define LPC31_EVNTRTR_ATR_OFFSET(b) (0x0ce0+_B(b)) /* Input event activation type */
|
||||||
#define LPC313X_EVNTRTR_RSR_OFFSET(b) (0x0d20+_B(b)) /* Input event raw status */
|
#define LPC31_EVNTRTR_RSR_OFFSET(b) (0x0d20+_B(b)) /* Input event raw status */
|
||||||
#define LPC313X_EVNTRTR_INTOUT_OFFSET 0x0d40 /* State of interrupt output pins */
|
#define LPC31_EVNTRTR_INTOUT_OFFSET 0x0d40 /* State of interrupt output pins */
|
||||||
/* 0x0e00-0x0ffc: Reserved */
|
/* 0x0e00-0x0ffc: Reserved */
|
||||||
#define LPC313X_EVNTRTR_INTOUTPEND_OFFSET(o,b) (0x1000+_OB(o,b)) /* Interrupt output 'o' pending */
|
#define LPC31_EVNTRTR_INTOUTPEND_OFFSET(o,b) (0x1000+_OB(o,b)) /* Interrupt output 'o' pending */
|
||||||
#define LPC313X_EVNTRTR_CGUWKUPPEND_OFFSET(b) (0x1000+_OB(4,b)) /* cgu_wakeup pending */
|
#define LPC31_EVNTRTR_CGUWKUPPEND_OFFSET(b) (0x1000+_OB(4,b)) /* cgu_wakeup pending */
|
||||||
#define LPC313X_EVNTRTR_INTOUTMASK_OFFSET(o,b) (0x1400+_OB(o,b)) /* Interrupt output 'o' mask */
|
#define LPC31_EVNTRTR_INTOUTMASK_OFFSET(o,b) (0x1400+_OB(o,b)) /* Interrupt output 'o' mask */
|
||||||
#define LPC313X_EVNTRTR_CGUWKUPMASK_OFFSET(b) (0x1400+_OB(4,b)) /* cgu_wakeup mask */
|
#define LPC31_EVNTRTR_CGUWKUPMASK_OFFSET(b) (0x1400+_OB(4,b)) /* cgu_wakeup mask */
|
||||||
#define LPC313X_EVNTRTR_INTOUTMASKCLR_OFFSET(o,b) (0x1800+_OB(o,b)) /* Interrupt output 'o' mask clear */
|
#define LPC31_EVNTRTR_INTOUTMASKCLR_OFFSET(o,b) (0x1800+_OB(o,b)) /* Interrupt output 'o' mask clear */
|
||||||
#define LPC313X_EVNTRTR_CGUWKUPMASKCLR_OFFSET(b) (0x1800+_OB(4,b)) /* cgu_wakeup mask clear */
|
#define LPC31_EVNTRTR_CGUWKUPMASKCLR_OFFSET(b) (0x1800+_OB(4,b)) /* cgu_wakeup mask clear */
|
||||||
#define LPC313X_EVNTRTR_INTOUTMASKSET_OFFSET(o,b) (0x1c00+_OB(o,b)) /* Interrupt output 'o' mask set */
|
#define LPC31_EVNTRTR_INTOUTMASKSET_OFFSET(o,b) (0x1c00+_OB(o,b)) /* Interrupt output 'o' mask set */
|
||||||
#define LPC313X_EVNTRTR_CGUWKUPMASKSET_OFFSET(b) (0x1c00+_OB(4,b)) /* cgu_wakeup mask set */
|
#define LPC31_EVNTRTR_CGUWKUPMASKSET_OFFSET(b) (0x1c00+_OB(4,b)) /* cgu_wakeup mask set */
|
||||||
|
|
||||||
/* EVNTRTR register (virtual) addresses *********************************************************************/
|
/* EVNTRTR register (virtual) addresses *********************************************************************/
|
||||||
|
|
||||||
#define LPC313X_EVNTRTR_PEND(b) (LPC313X_EVNTRTR_VBASE+LPC313X_EVNTRTR_PEND_OFFSET(b))
|
#define LPC31_EVNTRTR_PEND(b) (LPC31_EVNTRTR_VBASE+LPC31_EVNTRTR_PEND_OFFSET(b))
|
||||||
#define LPC313X_EVNTRTR_INTCLR(b) (LPC313X_EVNTRTR_VBASE+LPC313X_EVNTRTR_INTCLR_OFFSET(b))
|
#define LPC31_EVNTRTR_INTCLR(b) (LPC31_EVNTRTR_VBASE+LPC31_EVNTRTR_INTCLR_OFFSET(b))
|
||||||
#define LPC313X_EVNTRTR_INTSET(b) (LPC313X_EVNTRTR_VBASE+LPC313X_EVNTRTR_INTSET_OFFSET(b))
|
#define LPC31_EVNTRTR_INTSET(b) (LPC31_EVNTRTR_VBASE+LPC31_EVNTRTR_INTSET_OFFSET(b))
|
||||||
#define LPC313X_EVNTRTR_MASK(b) (LPC313X_EVNTRTR_VBASE+LPC313X_EVNTRTR_MASK_OFFSET(b))
|
#define LPC31_EVNTRTR_MASK(b) (LPC31_EVNTRTR_VBASE+LPC31_EVNTRTR_MASK_OFFSET(b))
|
||||||
#define LPC313X_EVNTRTR_MASKCLR(b) (LPC313X_EVNTRTR_VBASE+LPC313X_EVNTRTR_MASKCLR_OFFSET(b))
|
#define LPC31_EVNTRTR_MASKCLR(b) (LPC31_EVNTRTR_VBASE+LPC31_EVNTRTR_MASKCLR_OFFSET(b))
|
||||||
#define LPC313X_EVNTRTR_MASKSET(b) (LPC313X_EVNTRTR_VBASE+LPC313X_EVNTRTR_MASKSET_OFFSET(b))
|
#define LPC31_EVNTRTR_MASKSET(b) (LPC31_EVNTRTR_VBASE+LPC31_EVNTRTR_MASKSET_OFFSET(b))
|
||||||
#define LPC313X_EVNTRTR_APR(b) (LPC313X_EVNTRTR_VBASE+LPC313X_EVNTRTR_APR_OFFSET(b))
|
#define LPC31_EVNTRTR_APR(b) (LPC31_EVNTRTR_VBASE+LPC31_EVNTRTR_APR_OFFSET(b))
|
||||||
#define LPC313X_EVNTRTR_ATR(b) (LPC313X_EVNTRTR_VBASE+LPC313X_EVNTRTR_ATR_OFFSET(b))
|
#define LPC31_EVNTRTR_ATR(b) (LPC31_EVNTRTR_VBASE+LPC31_EVNTRTR_ATR_OFFSET(b))
|
||||||
#define LPC313X_EVNTRTR_RSR(b) (LPC313X_EVNTRTR_VBASE+LPC313X_EVNTRTR_RSR_OFFSET(b))
|
#define LPC31_EVNTRTR_RSR(b) (LPC31_EVNTRTR_VBASE+LPC31_EVNTRTR_RSR_OFFSET(b))
|
||||||
#define LPC313X_EVNTRTR_INTOUT (LPC313X_EVNTRTR_VBASE+LPC313X_EVNTRTR_INTOUT_OFFSET)
|
#define LPC31_EVNTRTR_INTOUT (LPC31_EVNTRTR_VBASE+LPC31_EVNTRTR_INTOUT_OFFSET)
|
||||||
#define LPC313X_EVNTRTR_INTOUTPEND(o,b) (LPC313X_EVNTRTR_VBASE+LPC313X_EVNTRTR_INTOUTPEND_OFFSET(o,b))
|
#define LPC31_EVNTRTR_INTOUTPEND(o,b) (LPC31_EVNTRTR_VBASE+LPC31_EVNTRTR_INTOUTPEND_OFFSET(o,b))
|
||||||
#define LPC313X_EVNTRTR_CGUWKUPPEND(b) (LPC313X_EVNTRTR_VBASE+LPC313X_EVNTRTR_CGUWKUPPEND_OFFSET(b))
|
#define LPC31_EVNTRTR_CGUWKUPPEND(b) (LPC31_EVNTRTR_VBASE+LPC31_EVNTRTR_CGUWKUPPEND_OFFSET(b))
|
||||||
#define LPC313X_EVNTRTR_INTOUTMASK(o,b) (LPC313X_EVNTRTR_VBASE+LPC313X_EVNTRTR_INTOUTMASK_OFFSET(o,b))
|
#define LPC31_EVNTRTR_INTOUTMASK(o,b) (LPC31_EVNTRTR_VBASE+LPC31_EVNTRTR_INTOUTMASK_OFFSET(o,b))
|
||||||
#define LPC313X_EVNTRTR_CGUWKUPMASK(b) (LPC313X_EVNTRTR_VBASE+LPC313X_EVNTRTR_CGUWKUPMASK_OFFSET(b))
|
#define LPC31_EVNTRTR_CGUWKUPMASK(b) (LPC31_EVNTRTR_VBASE+LPC31_EVNTRTR_CGUWKUPMASK_OFFSET(b))
|
||||||
#define LPC313X_EVNTRTR_INTOUTMASKCLR(o,b) (LPC313X_EVNTRTR_VBASE+LPC313X_EVNTRTR_INTOUTMASKCLR_OFFSET(o,b))
|
#define LPC31_EVNTRTR_INTOUTMASKCLR(o,b) (LPC31_EVNTRTR_VBASE+LPC31_EVNTRTR_INTOUTMASKCLR_OFFSET(o,b))
|
||||||
#define LPC313X_EVNTRTR_CGUWKUPMASKCLR(b) (LPC313X_EVNTRTR_VBASE+LPC313X_EVNTRTR_CGUWKUPMASKCLR_OFFSET(b))
|
#define LPC31_EVNTRTR_CGUWKUPMASKCLR(b) (LPC31_EVNTRTR_VBASE+LPC31_EVNTRTR_CGUWKUPMASKCLR_OFFSET(b))
|
||||||
#define LPC313X_EVNTRTR_INTOUTMASKSET(o,b) (LPC313X_EVNTRTR_VBASE+LPC313X_EVNTRTR_INTOUTMASKSET_OFFSET(o,b))
|
#define LPC31_EVNTRTR_INTOUTMASKSET(o,b) (LPC31_EVNTRTR_VBASE+LPC31_EVNTRTR_INTOUTMASKSET_OFFSET(o,b))
|
||||||
#define LPC313X_EVNTRTR_CGUWKUPMASKSET(b) (LPC313X_EVNTRTR_VBASE+LPC313X_EVNTRTR_CGUWKUPMASKSET_OFFSET(b)
|
#define LPC31_EVNTRTR_CGUWKUPMASKSET(b) (LPC31_EVNTRTR_VBASE+LPC31_EVNTRTR_CGUWKUPMASKSET_OFFSET(b)
|
||||||
|
|
||||||
/* EVNTRTR event definitions ********************************************************************************/
|
/* EVNTRTR event definitions ********************************************************************************/
|
||||||
/* Bank 0 */
|
/* Bank 0 */
|
||||||
@@ -261,4 +261,4 @@
|
|||||||
* Public Functions
|
* Public Functions
|
||||||
********************************************************************************************************/
|
********************************************************************************************************/
|
||||||
|
|
||||||
#endif /* __ARCH_ARM_SRC_LPC313X_EVNTRTR_H */
|
#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_EVNTRTR_H */
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/************************************************************************
|
/************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_fdcndx.c
|
* arch/arm/src/lpc31xx/lpc31_fdcndx.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -45,7 +45,7 @@
|
|||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
|
|
||||||
#include "up_arch.h"
|
#include "up_arch.h"
|
||||||
#include "lpc313x_cgudrvr.h"
|
#include "lpc31_cgudrvr.h"
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -88,7 +88,7 @@ static const uint8_t g_fdcbase[CGU_NDOMAINS] =
|
|||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_fdcndx
|
* Name: lpc31_fdcndx
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Given a clock ID and its domain ID, return the index of the
|
* Given a clock ID and its domain ID, return the index of the
|
||||||
@@ -97,19 +97,19 @@ static const uint8_t g_fdcbase[CGU_NDOMAINS] =
|
|||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
int lpc313x_fdcndx(enum lpc313x_clockid_e clkid, enum lpc313x_domainid_e dmnid)
|
int lpc31_fdcndx(enum lpc31_clockid_e clkid, enum lpc31_domainid_e dmnid)
|
||||||
{
|
{
|
||||||
int esrndx;
|
int esrndx;
|
||||||
int fdcndx = FDCNDX_INVALID;
|
int fdcndx = FDCNDX_INVALID;
|
||||||
|
|
||||||
/* Check if there is an ESR register associate with this clock ID */
|
/* Check if there is an ESR register associate with this clock ID */
|
||||||
|
|
||||||
esrndx = lpc313x_esrndx(clkid);
|
esrndx = lpc31_esrndx(clkid);
|
||||||
if (esrndx != ESRNDX_INVALID)
|
if (esrndx != ESRNDX_INVALID)
|
||||||
{
|
{
|
||||||
/* Read the clock's ESR to get the fractional divider */
|
/* Read the clock's ESR to get the fractional divider */
|
||||||
|
|
||||||
uint32_t regval = getreg32(LPC313X_CGU_ESR(esrndx));
|
uint32_t regval = getreg32(LPC31_CGU_ESR(esrndx));
|
||||||
|
|
||||||
/* Check if any fractional divider is enabled for this clock. */
|
/* Check if any fractional divider is enabled for this clock. */
|
||||||
|
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_fdivinit.c
|
* arch/arm/src/lpc31xx/lpc31_fdivinit.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -43,8 +43,8 @@
|
|||||||
|
|
||||||
#include <arch/board/board.h>
|
#include <arch/board/board.h>
|
||||||
|
|
||||||
#include "lpc313x_cgu.h"
|
#include "lpc31_cgu.h"
|
||||||
#include "lpc313x_cgudrvr.h"
|
#include "lpc31_cgudrvr.h"
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -63,7 +63,7 @@
|
|||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: lpc313x_bitwidth
|
* Name: lpc31_bitwidth
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Find the bit width of a msub or madd value. This will be use to
|
* Find the bit width of a msub or madd value. This will be use to
|
||||||
@@ -98,7 +98,7 @@
|
|||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
static inline unsigned int
|
static inline unsigned int
|
||||||
lpc313x_bitwidth(unsigned int value, unsigned int fdwid)
|
lpc31_bitwidth(unsigned int value, unsigned int fdwid)
|
||||||
{
|
{
|
||||||
unsigned int width = 0;
|
unsigned int width = 0;
|
||||||
int bit;
|
int bit;
|
||||||
@@ -124,15 +124,15 @@ lpc313x_bitwidth(unsigned int value, unsigned int fdwid)
|
|||||||
* Public Functions
|
* Public Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: lpc313x_fdivinit
|
* Name: lpc31_fdivinit
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Enable and configure (or disable) a fractional divider.
|
* Enable and configure (or disable) a fractional divider.
|
||||||
*
|
*
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
uint32_t lpc313x_fdivinit(int fdcndx,
|
uint32_t lpc31_fdivinit(int fdcndx,
|
||||||
const struct lpc313x_fdivconfig_s *fdiv, bool enable)
|
const struct lpc31_fdivconfig_s *fdiv, bool enable)
|
||||||
{
|
{
|
||||||
uint32_t regaddr;
|
uint32_t regaddr;
|
||||||
uint32_t regval;
|
uint32_t regval;
|
||||||
@@ -173,7 +173,7 @@ uint32_t lpc313x_fdivinit(int fdcndx,
|
|||||||
* of the two values. The width of the OR will be the width of the wider value
|
* of the two values. The width of the OR will be the width of the wider value
|
||||||
*/
|
*/
|
||||||
|
|
||||||
fdshift = fdwid - lpc313x_bitwidth((unsigned int)madd | (unsigned int)fdiv->n, fdwid);
|
fdshift = fdwid - lpc31_bitwidth((unsigned int)madd | (unsigned int)fdiv->n, fdwid);
|
||||||
|
|
||||||
/* Calculate the fractional divider register values */
|
/* Calculate the fractional divider register values */
|
||||||
|
|
||||||
@@ -198,7 +198,7 @@ uint32_t lpc313x_fdivinit(int fdcndx,
|
|||||||
|
|
||||||
/* Finally configure the divider */
|
/* Finally configure the divider */
|
||||||
|
|
||||||
regaddr = LPC313X_CGU_FDC(fdcndx);
|
regaddr = LPC31_CGU_FDC(fdcndx);
|
||||||
putreg32(regval, regaddr);
|
putreg32(regval, regaddr);
|
||||||
return regval;
|
return regval;
|
||||||
}
|
}
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_freqin.c
|
* arch/arm/src/lpc31xx/lpc31_freqin.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -43,7 +43,7 @@
|
|||||||
|
|
||||||
#include <arch/board/board.h>
|
#include <arch/board/board.h>
|
||||||
|
|
||||||
#include "lpc313x_cgudrvr.h"
|
#include "lpc31_cgudrvr.h"
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_i2c.c
|
* arch/arm/src/lpc31xx/lpc31_i2c.c
|
||||||
*
|
*
|
||||||
* Author: David Hewson
|
* Author: David Hewson
|
||||||
*
|
*
|
||||||
@@ -60,9 +60,9 @@
|
|||||||
#include "up_arch.h"
|
#include "up_arch.h"
|
||||||
#include "up_internal.h"
|
#include "up_internal.h"
|
||||||
|
|
||||||
#include "lpc313x_i2c.h"
|
#include "lpc31_i2c.h"
|
||||||
#include "lpc313x_evntrtr.h"
|
#include "lpc31_evntrtr.h"
|
||||||
#include "lpc313x_syscreg.h"
|
#include "lpc31_syscreg.h"
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* Definitions
|
* Definitions
|
||||||
@@ -77,7 +77,7 @@
|
|||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Private Data
|
* Private Data
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
struct lpc313x_i2cdev_s
|
struct lpc31_i2cdev_s
|
||||||
{
|
{
|
||||||
struct i2c_dev_s dev; /* Generic I2C device */
|
struct i2c_dev_s dev; /* Generic I2C device */
|
||||||
struct i2c_msg_s msg; /* a single message for legacy read/write */
|
struct i2c_msg_s msg; /* a single message for legacy read/write */
|
||||||
@@ -106,15 +106,15 @@ struct lpc313x_i2cdev_s
|
|||||||
#define I2C_STATE_HEADER 2
|
#define I2C_STATE_HEADER 2
|
||||||
#define I2C_STATE_TRANSFER 3
|
#define I2C_STATE_TRANSFER 3
|
||||||
|
|
||||||
static struct lpc313x_i2cdev_s i2cdevices[2];
|
static struct lpc31_i2cdev_s i2cdevices[2];
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Private Functions
|
* Private Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
static int i2c_interrupt (int irq, FAR void *context);
|
static int i2c_interrupt (int irq, FAR void *context);
|
||||||
static void i2c_progress (struct lpc313x_i2cdev_s *priv);
|
static void i2c_progress (struct lpc31_i2cdev_s *priv);
|
||||||
static void i2c_timeout (int argc, uint32_t arg, ...);
|
static void i2c_timeout (int argc, uint32_t arg, ...);
|
||||||
static void i2c_reset (struct lpc313x_i2cdev_s *priv);
|
static void i2c_reset (struct lpc31_i2cdev_s *priv);
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Public Functions
|
* Public Functions
|
||||||
@@ -130,7 +130,7 @@ static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int
|
|||||||
static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen);
|
static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen);
|
||||||
static int i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int count);
|
static int i2c_transfer(FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int count);
|
||||||
|
|
||||||
struct i2c_ops_s lpc313x_i2c_ops = {
|
struct i2c_ops_s lpc31_i2c_ops = {
|
||||||
.setfrequency = i2c_setfrequency,
|
.setfrequency = i2c_setfrequency,
|
||||||
.setaddress = i2c_setaddress,
|
.setaddress = i2c_setaddress,
|
||||||
.write = i2c_write,
|
.write = i2c_write,
|
||||||
@@ -150,23 +150,23 @@ struct i2c_ops_s lpc313x_i2c_ops = {
|
|||||||
|
|
||||||
struct i2c_dev_s *up_i2cinitialize(int port)
|
struct i2c_dev_s *up_i2cinitialize(int port)
|
||||||
{
|
{
|
||||||
struct lpc313x_i2cdev_s *priv = &i2cdevices[port];
|
struct lpc31_i2cdev_s *priv = &i2cdevices[port];
|
||||||
|
|
||||||
priv->base = (port == 0) ? LPC313X_I2C0_VBASE : LPC313X_I2C1_VBASE;
|
priv->base = (port == 0) ? LPC31_I2C0_VBASE : LPC31_I2C1_VBASE;
|
||||||
priv->clkid = (port == 0) ? CLKID_I2C0PCLK : CLKID_I2C1PCLK;
|
priv->clkid = (port == 0) ? CLKID_I2C0PCLK : CLKID_I2C1PCLK;
|
||||||
priv->rstid = (port == 0) ? RESETID_I2C0RST : RESETID_I2C1RST;
|
priv->rstid = (port == 0) ? RESETID_I2C0RST : RESETID_I2C1RST;
|
||||||
priv->irqid = (port == 0) ? LPC313X_IRQ_I2C0 : LPC313X_IRQ_I2C1;
|
priv->irqid = (port == 0) ? LPC31_IRQ_I2C0 : LPC31_IRQ_I2C1;
|
||||||
|
|
||||||
sem_init (&priv->mutex, 0, 1);
|
sem_init (&priv->mutex, 0, 1);
|
||||||
sem_init (&priv->wait, 0, 0);
|
sem_init (&priv->wait, 0, 0);
|
||||||
|
|
||||||
/* Enable I2C system clocks */
|
/* Enable I2C system clocks */
|
||||||
|
|
||||||
lpc313x_enableclock (priv->clkid);
|
lpc31_enableclock (priv->clkid);
|
||||||
|
|
||||||
/* Reset I2C blocks */
|
/* Reset I2C blocks */
|
||||||
|
|
||||||
lpc313x_softreset (priv->rstid);
|
lpc31_softreset (priv->rstid);
|
||||||
|
|
||||||
/* Soft reset the device */
|
/* Soft reset the device */
|
||||||
|
|
||||||
@@ -184,7 +184,7 @@ struct i2c_dev_s *up_i2cinitialize(int port)
|
|||||||
up_enable_irq(priv->irqid);
|
up_enable_irq(priv->irqid);
|
||||||
|
|
||||||
/* Install our operations */
|
/* Install our operations */
|
||||||
priv->dev.ops = &lpc313x_i2c_ops;
|
priv->dev.ops = &lpc31_i2c_ops;
|
||||||
|
|
||||||
return &priv->dev;
|
return &priv->dev;
|
||||||
}
|
}
|
||||||
@@ -197,7 +197,7 @@ struct i2c_dev_s *up_i2cinitialize(int port)
|
|||||||
*
|
*
|
||||||
*******************************************************************************/
|
*******************************************************************************/
|
||||||
|
|
||||||
void up_i2cuninitalize (struct lpc313x_i2cdev_s *priv)
|
void up_i2cuninitalize (struct lpc31_i2cdev_s *priv)
|
||||||
{
|
{
|
||||||
/* Disable All Interrupts, soft reset the device */
|
/* Disable All Interrupts, soft reset the device */
|
||||||
|
|
||||||
@@ -209,15 +209,15 @@ void up_i2cuninitalize (struct lpc313x_i2cdev_s *priv)
|
|||||||
|
|
||||||
/* Reset I2C blocks */
|
/* Reset I2C blocks */
|
||||||
|
|
||||||
lpc313x_softreset (priv->rstid);
|
lpc31_softreset (priv->rstid);
|
||||||
|
|
||||||
/* Disable I2C system clocks */
|
/* Disable I2C system clocks */
|
||||||
|
|
||||||
lpc313x_disableclock (priv->clkid);
|
lpc31_disableclock (priv->clkid);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* Name: lpc313x_i2c_setfrequency
|
* Name: lpc31_i2c_setfrequency
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Set the frequence for the next transfer
|
* Set the frequence for the next transfer
|
||||||
@@ -226,21 +226,21 @@ void up_i2cuninitalize (struct lpc313x_i2cdev_s *priv)
|
|||||||
|
|
||||||
static uint32_t i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency)
|
static uint32_t i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency)
|
||||||
{
|
{
|
||||||
struct lpc313x_i2cdev_s *priv = (struct lpc313x_i2cdev_s *) dev;
|
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) dev;
|
||||||
|
|
||||||
uint32_t freq = lpc313x_clkfreq (priv->clkid, DOMAINID_AHB0APB1);
|
uint32_t freq = lpc31_clkfreq (priv->clkid, DOMAINID_AHB0APB1);
|
||||||
|
|
||||||
if (freq > 100000)
|
if (freq > 100000)
|
||||||
{
|
{
|
||||||
/* asymetric per 400Khz I2C spec */
|
/* asymetric per 400Khz I2C spec */
|
||||||
putreg32 (((47 * freq) / (83 + 47)) / frequency, priv->base + LPC313X_I2C_CLKHI_OFFSET);
|
putreg32 (((47 * freq) / (83 + 47)) / frequency, priv->base + LPC31_I2C_CLKHI_OFFSET);
|
||||||
putreg32 (((83 * freq) / (83 + 47)) / frequency, priv->base + LPC313X_I2C_CLKLO_OFFSET);
|
putreg32 (((83 * freq) / (83 + 47)) / frequency, priv->base + LPC31_I2C_CLKLO_OFFSET);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
/* 50/50 mark space ratio */
|
/* 50/50 mark space ratio */
|
||||||
putreg32 (((50 * freq) / 100) / frequency, priv->base + LPC313X_I2C_CLKLO_OFFSET);
|
putreg32 (((50 * freq) / 100) / frequency, priv->base + LPC31_I2C_CLKLO_OFFSET);
|
||||||
putreg32 (((50 * freq) / 100) / frequency, priv->base + LPC313X_I2C_CLKHI_OFFSET);
|
putreg32 (((50 * freq) / 100) / frequency, priv->base + LPC31_I2C_CLKHI_OFFSET);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* FIXME: This function should return the actual selected frequency */
|
/* FIXME: This function should return the actual selected frequency */
|
||||||
@@ -248,7 +248,7 @@ static uint32_t i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency)
|
|||||||
}
|
}
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* Name: lpc313x_i2c_setaddress
|
* Name: lpc31_i2c_setaddress
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Set the I2C slave address for a subsequent read/write
|
* Set the I2C slave address for a subsequent read/write
|
||||||
@@ -256,7 +256,7 @@ static uint32_t i2c_setfrequency(FAR struct i2c_dev_s *dev, uint32_t frequency)
|
|||||||
*******************************************************************************/
|
*******************************************************************************/
|
||||||
static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits)
|
static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits)
|
||||||
{
|
{
|
||||||
struct lpc313x_i2cdev_s *priv = (struct lpc313x_i2cdev_s *) dev;
|
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) dev;
|
||||||
|
|
||||||
DEBUGASSERT(dev != NULL);
|
DEBUGASSERT(dev != NULL);
|
||||||
DEBUGASSERT(nbits == 7 || nbits == 10);
|
DEBUGASSERT(nbits == 7 || nbits == 10);
|
||||||
@@ -268,7 +268,7 @@ static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits)
|
|||||||
}
|
}
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* Name: lpc313x_i2c_write
|
* Name: lpc31_i2c_write
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Send a block of data on I2C using the previously selected I2C
|
* Send a block of data on I2C using the previously selected I2C
|
||||||
@@ -277,7 +277,7 @@ static int i2c_setaddress(FAR struct i2c_dev_s *dev, int addr, int nbits)
|
|||||||
*******************************************************************************/
|
*******************************************************************************/
|
||||||
static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int buflen)
|
static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int buflen)
|
||||||
{
|
{
|
||||||
struct lpc313x_i2cdev_s *priv = (struct lpc313x_i2cdev_s *) dev;
|
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) dev;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
DEBUGASSERT (dev != NULL);
|
DEBUGASSERT (dev != NULL);
|
||||||
@@ -292,7 +292,7 @@ static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int bufle
|
|||||||
}
|
}
|
||||||
|
|
||||||
/*******************************************************************************
|
/*******************************************************************************
|
||||||
* Name: lpc313x_i2c_read
|
* Name: lpc31_i2c_read
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Receive a block of data on I2C using the previously selected I2C
|
* Receive a block of data on I2C using the previously selected I2C
|
||||||
@@ -301,7 +301,7 @@ static int i2c_write(FAR struct i2c_dev_s *dev, const uint8_t *buffer, int bufle
|
|||||||
*******************************************************************************/
|
*******************************************************************************/
|
||||||
static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen)
|
static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen)
|
||||||
{
|
{
|
||||||
struct lpc313x_i2cdev_s *priv = (struct lpc313x_i2cdev_s *) dev;
|
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) dev;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
DEBUGASSERT (dev != NULL);
|
DEBUGASSERT (dev != NULL);
|
||||||
@@ -325,7 +325,7 @@ static int i2c_read(FAR struct i2c_dev_s *dev, uint8_t *buffer, int buflen)
|
|||||||
|
|
||||||
static int i2c_transfer (FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int count)
|
static int i2c_transfer (FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs, int count)
|
||||||
{
|
{
|
||||||
struct lpc313x_i2cdev_s *priv = (struct lpc313x_i2cdev_s *) dev;
|
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) dev;
|
||||||
irqstate_t flags;
|
irqstate_t flags;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
@@ -367,12 +367,12 @@ static int i2c_transfer (FAR struct i2c_dev_s *dev, FAR struct i2c_msg_s *msgs,
|
|||||||
|
|
||||||
static int i2c_interrupt (int irq, FAR void *context)
|
static int i2c_interrupt (int irq, FAR void *context)
|
||||||
{
|
{
|
||||||
if (irq == LPC313X_IRQ_I2C0)
|
if (irq == LPC31_IRQ_I2C0)
|
||||||
{
|
{
|
||||||
i2c_progress (&i2cdevices[0]);
|
i2c_progress (&i2cdevices[0]);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (irq == LPC313X_IRQ_I2C1)
|
if (irq == LPC31_IRQ_I2C1)
|
||||||
{
|
{
|
||||||
i2c_progress (&i2cdevices[1]);
|
i2c_progress (&i2cdevices[1]);
|
||||||
}
|
}
|
||||||
@@ -388,12 +388,12 @@ static int i2c_interrupt (int irq, FAR void *context)
|
|||||||
*
|
*
|
||||||
*******************************************************************************/
|
*******************************************************************************/
|
||||||
|
|
||||||
static void i2c_progress (struct lpc313x_i2cdev_s *priv)
|
static void i2c_progress (struct lpc31_i2cdev_s *priv)
|
||||||
{
|
{
|
||||||
struct i2c_msg_s *msg;
|
struct i2c_msg_s *msg;
|
||||||
uint32_t stat, ctrl;
|
uint32_t stat, ctrl;
|
||||||
|
|
||||||
stat = getreg32 (priv->base + LPC313X_I2C_STAT_OFFSET);
|
stat = getreg32 (priv->base + LPC31_I2C_STAT_OFFSET);
|
||||||
|
|
||||||
/* Were there arbitration problems? */
|
/* Were there arbitration problems? */
|
||||||
if ((stat & I2C_STAT_AFI) != 0)
|
if ((stat & I2C_STAT_AFI) != 0)
|
||||||
@@ -433,7 +433,7 @@ static void i2c_progress (struct lpc313x_i2cdev_s *priv)
|
|||||||
priv->hdrcnt = 1;
|
priv->hdrcnt = 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
putreg32 (ctrl, priv->base + LPC313X_I2C_CTRL_OFFSET);
|
putreg32 (ctrl, priv->base + LPC31_I2C_CTRL_OFFSET);
|
||||||
|
|
||||||
priv->state = I2C_STATE_HEADER;
|
priv->state = I2C_STATE_HEADER;
|
||||||
priv->wrcnt = 0;
|
priv->wrcnt = 0;
|
||||||
@@ -442,16 +442,16 @@ static void i2c_progress (struct lpc313x_i2cdev_s *priv)
|
|||||||
case I2C_STATE_HEADER:
|
case I2C_STATE_HEADER:
|
||||||
while ((priv->wrcnt != priv->hdrcnt) && (stat & I2C_STAT_TFF) == 0)
|
while ((priv->wrcnt != priv->hdrcnt) && (stat & I2C_STAT_TFF) == 0)
|
||||||
{
|
{
|
||||||
putreg32(priv->header[priv->wrcnt], priv->base + LPC313X_I2C_TX_OFFSET);
|
putreg32(priv->header[priv->wrcnt], priv->base + LPC31_I2C_TX_OFFSET);
|
||||||
priv->wrcnt++;
|
priv->wrcnt++;
|
||||||
|
|
||||||
stat = getreg32 (priv->base + LPC313X_I2C_STAT_OFFSET);
|
stat = getreg32 (priv->base + LPC31_I2C_STAT_OFFSET);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (priv->wrcnt < priv->hdrcnt)
|
if (priv->wrcnt < priv->hdrcnt)
|
||||||
{
|
{
|
||||||
/* Enable Tx FIFO Not Full Interrupt */
|
/* Enable Tx FIFO Not Full Interrupt */
|
||||||
putreg32 (ctrl | I2C_CTRL_TFFIE, priv->base + LPC313X_I2C_CTRL_OFFSET);
|
putreg32 (ctrl | I2C_CTRL_TFFIE, priv->base + LPC31_I2C_CTRL_OFFSET);
|
||||||
goto out;
|
goto out;
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -465,10 +465,10 @@ static void i2c_progress (struct lpc313x_i2cdev_s *priv)
|
|||||||
{
|
{
|
||||||
while ((priv->rdcnt != msg->length) && (stat & I2C_STAT_RFE) == 0)
|
while ((priv->rdcnt != msg->length) && (stat & I2C_STAT_RFE) == 0)
|
||||||
{
|
{
|
||||||
msg->buffer[priv->rdcnt] = getreg32 (priv->base + LPC313X_I2C_RX_OFFSET);
|
msg->buffer[priv->rdcnt] = getreg32 (priv->base + LPC31_I2C_RX_OFFSET);
|
||||||
priv->rdcnt++;
|
priv->rdcnt++;
|
||||||
|
|
||||||
stat = getreg32 (priv->base + LPC313X_I2C_STAT_OFFSET);
|
stat = getreg32 (priv->base + LPC31_I2C_STAT_OFFSET);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (priv->rdcnt < msg->length)
|
if (priv->rdcnt < msg->length)
|
||||||
@@ -477,23 +477,23 @@ static void i2c_progress (struct lpc313x_i2cdev_s *priv)
|
|||||||
while ((priv->wrcnt != msg->length) && (stat & I2C_STAT_TFF) == 0)
|
while ((priv->wrcnt != msg->length) && (stat & I2C_STAT_TFF) == 0)
|
||||||
{
|
{
|
||||||
if ((priv->wrcnt + 1) == msg->length && priv->nmsg == 1)
|
if ((priv->wrcnt + 1) == msg->length && priv->nmsg == 1)
|
||||||
putreg32 (I2C_TX_STOP, priv->base + LPC313X_I2C_TX_OFFSET);
|
putreg32 (I2C_TX_STOP, priv->base + LPC31_I2C_TX_OFFSET);
|
||||||
else
|
else
|
||||||
putreg32 (0, priv->base + LPC313X_I2C_TX_OFFSET);
|
putreg32 (0, priv->base + LPC31_I2C_TX_OFFSET);
|
||||||
priv->wrcnt++;
|
priv->wrcnt++;
|
||||||
|
|
||||||
stat = getreg32 (priv->base + LPC313X_I2C_STAT_OFFSET);
|
stat = getreg32 (priv->base + LPC31_I2C_STAT_OFFSET);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (priv->wrcnt < msg->length)
|
if (priv->wrcnt < msg->length)
|
||||||
{
|
{
|
||||||
/* Enable Tx FIFO not full and Rx Fifo Avail Interrupts */
|
/* Enable Tx FIFO not full and Rx Fifo Avail Interrupts */
|
||||||
putreg32 (ctrl | I2C_CTRL_TFFIE | I2C_CTRL_RFDAIE, priv->base + LPC313X_I2C_CTRL_OFFSET);
|
putreg32 (ctrl | I2C_CTRL_TFFIE | I2C_CTRL_RFDAIE, priv->base + LPC31_I2C_CTRL_OFFSET);
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
/* Enable Rx Fifo Avail Interrupts */
|
/* Enable Rx Fifo Avail Interrupts */
|
||||||
putreg32 (ctrl | I2C_CTRL_RFDAIE, priv->base + LPC313X_I2C_CTRL_OFFSET);
|
putreg32 (ctrl | I2C_CTRL_RFDAIE, priv->base + LPC31_I2C_CTRL_OFFSET);
|
||||||
}
|
}
|
||||||
goto out;
|
goto out;
|
||||||
}
|
}
|
||||||
@@ -503,19 +503,19 @@ static void i2c_progress (struct lpc313x_i2cdev_s *priv)
|
|||||||
while ((priv->wrcnt != msg->length) && (stat & I2C_STAT_TFF) == 0)
|
while ((priv->wrcnt != msg->length) && (stat & I2C_STAT_TFF) == 0)
|
||||||
{
|
{
|
||||||
if ((priv->wrcnt + 1) == msg->length && priv->nmsg == 1)
|
if ((priv->wrcnt + 1) == msg->length && priv->nmsg == 1)
|
||||||
putreg32 (I2C_TX_STOP | msg->buffer[priv->wrcnt], priv->base + LPC313X_I2C_TX_OFFSET);
|
putreg32 (I2C_TX_STOP | msg->buffer[priv->wrcnt], priv->base + LPC31_I2C_TX_OFFSET);
|
||||||
else
|
else
|
||||||
putreg32 (msg->buffer[priv->wrcnt], priv->base + LPC313X_I2C_TX_OFFSET);
|
putreg32 (msg->buffer[priv->wrcnt], priv->base + LPC31_I2C_TX_OFFSET);
|
||||||
|
|
||||||
priv->wrcnt++;
|
priv->wrcnt++;
|
||||||
|
|
||||||
stat = getreg32 (priv->base + LPC313X_I2C_STAT_OFFSET);
|
stat = getreg32 (priv->base + LPC31_I2C_STAT_OFFSET);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (priv->wrcnt < msg->length)
|
if (priv->wrcnt < msg->length)
|
||||||
{
|
{
|
||||||
/* Enable Tx Fifo not full Interrupt */
|
/* Enable Tx Fifo not full Interrupt */
|
||||||
putreg32 (ctrl | I2C_CTRL_TFFIE, priv->base + LPC313X_I2C_CTRL_OFFSET);
|
putreg32 (ctrl | I2C_CTRL_TFFIE, priv->base + LPC31_I2C_CTRL_OFFSET);
|
||||||
goto out;
|
goto out;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@@ -526,7 +526,7 @@ static void i2c_progress (struct lpc313x_i2cdev_s *priv)
|
|||||||
if (--priv->nmsg == 0)
|
if (--priv->nmsg == 0)
|
||||||
{
|
{
|
||||||
/* Final transfer, wait for Transmit Done Interrupt */
|
/* Final transfer, wait for Transmit Done Interrupt */
|
||||||
putreg32 (ctrl, priv->base + LPC313X_I2C_CTRL_OFFSET);
|
putreg32 (ctrl, priv->base + LPC31_I2C_CTRL_OFFSET);
|
||||||
goto out;
|
goto out;
|
||||||
}
|
}
|
||||||
priv->msgs++;
|
priv->msgs++;
|
||||||
@@ -537,13 +537,13 @@ static void i2c_progress (struct lpc313x_i2cdev_s *priv)
|
|||||||
out:
|
out:
|
||||||
if (stat & I2C_STAT_TDI)
|
if (stat & I2C_STAT_TDI)
|
||||||
{
|
{
|
||||||
putreg32 (I2C_STAT_TDI, priv->base + LPC313X_I2C_STAT_OFFSET);
|
putreg32 (I2C_STAT_TDI, priv->base + LPC31_I2C_STAT_OFFSET);
|
||||||
|
|
||||||
/* You'd expect the NAI bit to be set when no acknowledge was
|
/* You'd expect the NAI bit to be set when no acknowledge was
|
||||||
* received - but it gets cleared whenever a write it done to
|
* received - but it gets cleared whenever a write it done to
|
||||||
* the TXFIFO - so we've gone and cleared it while priming the
|
* the TXFIFO - so we've gone and cleared it while priming the
|
||||||
* rest of the transfer! */
|
* rest of the transfer! */
|
||||||
if ((stat = getreg32 (priv->base + LPC313X_I2C_TXFL_OFFSET)) != 0)
|
if ((stat = getreg32 (priv->base + LPC31_I2C_TXFL_OFFSET)) != 0)
|
||||||
{
|
{
|
||||||
if (priv->nmsg == 0)
|
if (priv->nmsg == 0)
|
||||||
priv->nmsg++;
|
priv->nmsg++;
|
||||||
@@ -565,7 +565,7 @@ out:
|
|||||||
|
|
||||||
static void i2c_timeout (int argc, uint32_t arg, ...)
|
static void i2c_timeout (int argc, uint32_t arg, ...)
|
||||||
{
|
{
|
||||||
struct lpc313x_i2cdev_s *priv = (struct lpc313x_i2cdev_s *) arg;
|
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) arg;
|
||||||
|
|
||||||
irqstate_t flags = irqsave();
|
irqstate_t flags = irqsave();
|
||||||
|
|
||||||
@@ -574,7 +574,7 @@ static void i2c_timeout (int argc, uint32_t arg, ...)
|
|||||||
/* If there's data remaining in the TXFIFO, then ensure at least
|
/* If there's data remaining in the TXFIFO, then ensure at least
|
||||||
* one transfer has failed to complete.. */
|
* one transfer has failed to complete.. */
|
||||||
|
|
||||||
if (getreg32 (priv->base + LPC313X_I2C_TXFL_OFFSET) != 0)
|
if (getreg32 (priv->base + LPC31_I2C_TXFL_OFFSET) != 0)
|
||||||
{
|
{
|
||||||
if (priv->nmsg == 0)
|
if (priv->nmsg == 0)
|
||||||
priv->nmsg++;
|
priv->nmsg++;
|
||||||
@@ -598,11 +598,11 @@ static void i2c_timeout (int argc, uint32_t arg, ...)
|
|||||||
* Perform a soft reset of the I2C controller
|
* Perform a soft reset of the I2C controller
|
||||||
*
|
*
|
||||||
*******************************************************************************/
|
*******************************************************************************/
|
||||||
static void i2c_reset (struct lpc313x_i2cdev_s *priv)
|
static void i2c_reset (struct lpc31_i2cdev_s *priv)
|
||||||
{
|
{
|
||||||
putreg32 (I2C_CTRL_RESET, priv->base + LPC313X_I2C_CTRL_OFFSET);
|
putreg32 (I2C_CTRL_RESET, priv->base + LPC31_I2C_CTRL_OFFSET);
|
||||||
|
|
||||||
/* Wait for Reset to complete */
|
/* Wait for Reset to complete */
|
||||||
while ((getreg32 (priv->base + LPC313X_I2C_CTRL_OFFSET) & I2C_CTRL_RESET) != 0)
|
while ((getreg32 (priv->base + LPC31_I2C_CTRL_OFFSET) & I2C_CTRL_RESET) != 0)
|
||||||
;
|
;
|
||||||
}
|
}
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_i2c.h
|
* arch/arm/src/lpc31xx/lpc31_i2c.h
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -33,15 +33,15 @@
|
|||||||
*
|
*
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#ifndef __ARCH_ARM_SRC_LPC313X_I2C_H
|
#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_I2C_H
|
||||||
#define __ARCH_ARM_SRC_LPC313X_I2C_H
|
#define __ARCH_ARM_SRC_LPC31XX_LPC31_I2C_H
|
||||||
|
|
||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* Included Files
|
* Included Files
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#include <nuttx/config.h>
|
#include <nuttx/config.h>
|
||||||
#include "lpc313x_memorymap.h"
|
#include "lpc31_memorymap.h"
|
||||||
|
|
||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -49,57 +49,57 @@
|
|||||||
|
|
||||||
/* I2C register base address offset into the APB1 domain ****************************************/
|
/* I2C register base address offset into the APB1 domain ****************************************/
|
||||||
|
|
||||||
#define LPC313X_I2C0_VBASE (LPC313X_APB1_VADDR+LPC313X_APB1_I2C0_OFFSET)
|
#define LPC31_I2C0_VBASE (LPC31_APB1_VADDR+LPC31_APB1_I2C0_OFFSET)
|
||||||
#define LPC313X_I2C0_PBASE (LPC313X_APB1_PADDR+LPC313X_APB1_I2C0_OFFSET)
|
#define LPC31_I2C0_PBASE (LPC31_APB1_PADDR+LPC31_APB1_I2C0_OFFSET)
|
||||||
|
|
||||||
#define LPC313X_I2C1_VBASE (LPC313X_APB1_VADDR+LPC313X_APB1_I2C1_OFFSET)
|
#define LPC31_I2C1_VBASE (LPC31_APB1_VADDR+LPC31_APB1_I2C1_OFFSET)
|
||||||
#define LPC313X_I2C1_PBASE (LPC313X_APB1_PADDR+LPC313X_APB1_I2C1_OFFSET)
|
#define LPC31_I2C1_PBASE (LPC31_APB1_PADDR+LPC31_APB1_I2C1_OFFSET)
|
||||||
|
|
||||||
/* I2C register offsets (with respect to the I2C base) ******************************************/
|
/* I2C register offsets (with respect to the I2C base) ******************************************/
|
||||||
|
|
||||||
#define LPC313X_I2C_RX_OFFSET 0x00 /* I2C RX Data FIFO */
|
#define LPC31_I2C_RX_OFFSET 0x00 /* I2C RX Data FIFO */
|
||||||
#define LPC313X_I2C_TX_OFFSET 0x00 /* I2C TX Data FIFO */
|
#define LPC31_I2C_TX_OFFSET 0x00 /* I2C TX Data FIFO */
|
||||||
#define LPC313X_I2C_STAT_OFFSET 0x04 /* I2C Status Register */
|
#define LPC31_I2C_STAT_OFFSET 0x04 /* I2C Status Register */
|
||||||
#define LPC313X_I2C_CTRL_OFFSET 0x08 /* I2C Control Register */
|
#define LPC31_I2C_CTRL_OFFSET 0x08 /* I2C Control Register */
|
||||||
#define LPC313X_I2C_CLKHI_OFFSET 0x0c /* I2C Clock Divider high */
|
#define LPC31_I2C_CLKHI_OFFSET 0x0c /* I2C Clock Divider high */
|
||||||
#define LPC313X_I2C_CLKLO_OFFSET 0x10 /* I2C Clock Divider low */
|
#define LPC31_I2C_CLKLO_OFFSET 0x10 /* I2C Clock Divider low */
|
||||||
#define LPC313X_I2C_ADR_OFFSET 0x14 /* I2C Slave Address */
|
#define LPC31_I2C_ADR_OFFSET 0x14 /* I2C Slave Address */
|
||||||
#define LPC313X_I2C_RXFL_OFFSET 0x18 /* I2C Rx FIFO level */
|
#define LPC31_I2C_RXFL_OFFSET 0x18 /* I2C Rx FIFO level */
|
||||||
#define LPC313X_I2C_TXFL_OFFSET 0x1c /* I2C Tx FIFO level */
|
#define LPC31_I2C_TXFL_OFFSET 0x1c /* I2C Tx FIFO level */
|
||||||
#define LPC313X_I2C_RXB_OFFSET 0x20 /* I2C Number of bytes received */
|
#define LPC31_I2C_RXB_OFFSET 0x20 /* I2C Number of bytes received */
|
||||||
#define LPC313X_I2C_TXB_OFFSET 0x24 /* I2C Number of bytes transmitted */
|
#define LPC31_I2C_TXB_OFFSET 0x24 /* I2C Number of bytes transmitted */
|
||||||
#define LPC313X_I2C_STX_OFFSET 0x28 /* Slave Transmit FIFO */
|
#define LPC31_I2C_STX_OFFSET 0x28 /* Slave Transmit FIFO */
|
||||||
#define LPC313X_I2C_STXFL_OFFSET 0x2c /* Slave Transmit FIFO level */
|
#define LPC31_I2C_STXFL_OFFSET 0x2c /* Slave Transmit FIFO level */
|
||||||
|
|
||||||
/* I2C register (virtual) addresses *************************************************************/
|
/* I2C register (virtual) addresses *************************************************************/
|
||||||
|
|
||||||
#define LPC313X_I2C0_RX (LPC313X_I2C0_VBASE+LPC313X_I2C_RX_OFFSET)
|
#define LPC31_I2C0_RX (LPC31_I2C0_VBASE+LPC31_I2C_RX_OFFSET)
|
||||||
#define LPC313X_I2C0_TX (LPC313X_I2C0_VBASE+LPC313X_I2C_TX_OFFSET)
|
#define LPC31_I2C0_TX (LPC31_I2C0_VBASE+LPC31_I2C_TX_OFFSET)
|
||||||
#define LPC313X_I2C0_STAT (LPC313X_I2C0_VBASE+LPC313X_I2C_STAT_OFFSET)
|
#define LPC31_I2C0_STAT (LPC31_I2C0_VBASE+LPC31_I2C_STAT_OFFSET)
|
||||||
#define LPC313X_I2C0_CTRL (LPC313X_I2C0_VBASE+LPC313X_I2C_CTRL_OFFSET)
|
#define LPC31_I2C0_CTRL (LPC31_I2C0_VBASE+LPC31_I2C_CTRL_OFFSET)
|
||||||
#define LPC313X_I2C0_CLKHI (LPC313X_I2C0_VBASE+LPC313X_I2C_CLKHI_OFFSET)
|
#define LPC31_I2C0_CLKHI (LPC31_I2C0_VBASE+LPC31_I2C_CLKHI_OFFSET)
|
||||||
#define LPC313X_I2C0_CLKLO (LPC313X_I2C0_VBASE+LPC313X_I2C_CLKLO_OFFSET)
|
#define LPC31_I2C0_CLKLO (LPC31_I2C0_VBASE+LPC31_I2C_CLKLO_OFFSET)
|
||||||
#define LPC313X_I2C0_ADR (LPC313X_I2C0_VBASE+LPC313X_I2C_ADR_OFFSET)
|
#define LPC31_I2C0_ADR (LPC31_I2C0_VBASE+LPC31_I2C_ADR_OFFSET)
|
||||||
#define LPC313X_I2C0_RXFL (LPC313X_I2C0_VBASE+LPC313X_I2C_RXFL_OFFSET)
|
#define LPC31_I2C0_RXFL (LPC31_I2C0_VBASE+LPC31_I2C_RXFL_OFFSET)
|
||||||
#define LPC313X_I2C0_TXFL (LPC313X_I2C0_VBASE+LPC313X_I2C_TXFL_OFFSET)
|
#define LPC31_I2C0_TXFL (LPC31_I2C0_VBASE+LPC31_I2C_TXFL_OFFSET)
|
||||||
#define LPC313X_I2C0_RXB (LPC313X_I2C0_VBASE+LPC313X_I2C_RXB_OFFSET)
|
#define LPC31_I2C0_RXB (LPC31_I2C0_VBASE+LPC31_I2C_RXB_OFFSET)
|
||||||
#define LPC313X_I2C0_TXB (LPC313X_I2C0_VBASE+LPC313X_I2C_TXB_OFFSET)
|
#define LPC31_I2C0_TXB (LPC31_I2C0_VBASE+LPC31_I2C_TXB_OFFSET)
|
||||||
#define LPC313X_I2C0_STX (LPC313X_I2C0_VBASE+LPC313X_I2C_STX_OFFSET)
|
#define LPC31_I2C0_STX (LPC31_I2C0_VBASE+LPC31_I2C_STX_OFFSET)
|
||||||
#define LPC313X_I2C0_STXFL (LPC313X_I2C0_VBASE+LPC313X_I2C_STXFL_OFFSET)
|
#define LPC31_I2C0_STXFL (LPC31_I2C0_VBASE+LPC31_I2C_STXFL_OFFSET)
|
||||||
|
|
||||||
#define LPC313X_I2C1_RX (LPC313X_I2C1_VBASE+LPC313X_I2C_RX_OFFSET)
|
#define LPC31_I2C1_RX (LPC31_I2C1_VBASE+LPC31_I2C_RX_OFFSET)
|
||||||
#define LPC313X_I2C1_TX (LPC313X_I2C1_VBASE+LPC313X_I2C_TX_OFFSET)
|
#define LPC31_I2C1_TX (LPC31_I2C1_VBASE+LPC31_I2C_TX_OFFSET)
|
||||||
#define LPC313X_I2C1_STAT (LPC313X_I2C1_VBASE+LPC313X_I2C_STAT_OFFSET)
|
#define LPC31_I2C1_STAT (LPC31_I2C1_VBASE+LPC31_I2C_STAT_OFFSET)
|
||||||
#define LPC313X_I2C1_CTRL (LPC313X_I2C1_VBASE+LPC313X_I2C_CTRL_OFFSET)
|
#define LPC31_I2C1_CTRL (LPC31_I2C1_VBASE+LPC31_I2C_CTRL_OFFSET)
|
||||||
#define LPC313X_I2C1_CLKHI (LPC313X_I2C1_VBASE+LPC313X_I2C_CLKHI_OFFSET)
|
#define LPC31_I2C1_CLKHI (LPC31_I2C1_VBASE+LPC31_I2C_CLKHI_OFFSET)
|
||||||
#define LPC313X_I2C1_CLKLO (LPC313X_I2C1_VBASE+LPC313X_I2C_CLKLO_OFFSET)
|
#define LPC31_I2C1_CLKLO (LPC31_I2C1_VBASE+LPC31_I2C_CLKLO_OFFSET)
|
||||||
#define LPC313X_I2C1_ADR (LPC313X_I2C1_VBASE+LPC313X_I2C_ADR_OFFSET)
|
#define LPC31_I2C1_ADR (LPC31_I2C1_VBASE+LPC31_I2C_ADR_OFFSET)
|
||||||
#define LPC313X_I2C1_RXFL (LPC313X_I2C1_VBASE+LPC313X_I2C_RXFL_OFFSET)
|
#define LPC31_I2C1_RXFL (LPC31_I2C1_VBASE+LPC31_I2C_RXFL_OFFSET)
|
||||||
#define LPC313X_I2C1_TXFL (LPC313X_I2C1_VBASE+LPC313X_I2C_TXFL_OFFSET)
|
#define LPC31_I2C1_TXFL (LPC31_I2C1_VBASE+LPC31_I2C_TXFL_OFFSET)
|
||||||
#define LPC313X_I2C1_RXB (LPC313X_I2C1_VBASE+LPC313X_I2C_RXB_OFFSET)
|
#define LPC31_I2C1_RXB (LPC31_I2C1_VBASE+LPC31_I2C_RXB_OFFSET)
|
||||||
#define LPC313X_I2C1_TXB (LPC313X_I2C1_VBASE+LPC313X_I2C_TXB_OFFSET)
|
#define LPC31_I2C1_TXB (LPC31_I2C1_VBASE+LPC31_I2C_TXB_OFFSET)
|
||||||
#define LPC313X_I2C1_STX (LPC313X_I2C1_VBASE+LPC313X_I2C_STX_OFFSET)
|
#define LPC31_I2C1_STX (LPC31_I2C1_VBASE+LPC31_I2C_STX_OFFSET)
|
||||||
#define LPC313X_I2C1_STXFL (LPC313X_I2C1_VBASE+LPC313X_I2C_STXFL_OFFSET)
|
#define LPC31_I2C1_STXFL (LPC31_I2C1_VBASE+LPC31_I2C_STXFL_OFFSET)
|
||||||
|
|
||||||
/* I2C register bit definitions *****************************************************************/
|
/* I2C register bit definitions *****************************************************************/
|
||||||
|
|
||||||
@@ -204,4 +204,4 @@
|
|||||||
* Public Functions
|
* Public Functions
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#endif /* __ARCH_ARM_SRC_LPC313X_I2C_H */
|
#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_I2C_H */
|
||||||
Executable
+315
@@ -0,0 +1,315 @@
|
|||||||
|
/************************************************************************************************
|
||||||
|
* arch/arm/src/lpc31xx/lpc31_i2s.h
|
||||||
|
*
|
||||||
|
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||||
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||||
|
* used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||||
|
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||||
|
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_I2S_H
|
||||||
|
#define __ARCH_ARM_SRC_LPC31XX_LPC31_I2S_H
|
||||||
|
|
||||||
|
/************************************************************************************************
|
||||||
|
* Included Files
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
#include <nuttx/config.h>
|
||||||
|
#include "lpc31_memorymap.h"
|
||||||
|
|
||||||
|
/************************************************************************************************
|
||||||
|
* Pre-processor Definitions
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
/* I2S register base address offset into the APB3 domain ****************************************/
|
||||||
|
|
||||||
|
#define LPC31_I2SCONFIG_VBASE (LPC31_APB3_VSECTION+LPC31_APB3_I2SCONFIG_OFFSET)
|
||||||
|
#define LPC31_I2SCONFIG_PBASE (LPC31_APB3_PSECTION+LPC31_APB3_I2SCONFIG_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_I2STX0_VBASE (LPC31_APB3_VSECTION+LPC31_APB3_I2STX0_OFFSET)
|
||||||
|
#define LPC31_I2STX0_PBASE (LPC31_APB3_PSECTION+LPC31_APB3_I2STX0_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_I2STX1_VBASE (LPC31_APB3_VSECTION+LPC31_APB3_I2STX1_OFFSET)
|
||||||
|
#define LPC31_I2STX1_PBASE (LPC31_APB3_PSECTION+LPC31_APB3_I2STX1_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_I2SRX0_VBASE (LPC31_APB3_VSECTION+LPC31_APB3_I2SRX0_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_PBASE (LPC31_APB3_PSECTION+LPC31_APB3_I2SRX0_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_I2SRX1_VBASE (LPC31_APB3_VSECTION+LPC31_APB3_I2SRX1_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_PBASE (LPC31_APB3_PSECTION+LPC31_APB3_I2SRX1_OFFSET)
|
||||||
|
|
||||||
|
/* I2S register offsets (with respect to the I2S base) ******************************************/
|
||||||
|
/* I2S configuration module offset */
|
||||||
|
|
||||||
|
#define LPC31_I2SCONFIG_FORMAT_OFFSET 0x000 /* I2S formats */
|
||||||
|
#define LPC31_I2SCONFIG_CFGMUX_OFFSET 0x004 /* Misc controls */
|
||||||
|
/* 0x008-0x00c: Reserved */
|
||||||
|
#define LPC31_I2SCONFIG_NSOFCNTR_OFFSET 0x010 /* NSOF counter control */
|
||||||
|
|
||||||
|
/* I2STX0, I2STX1, I2SRX0, and I2SRX1 module offsets */
|
||||||
|
|
||||||
|
#define LPC31_I2S_L16BIT_OFFSET 0x000 /* 16 bits left channel data */
|
||||||
|
#define LPC31_I2S_R16BIT_OFFSET 0x004 /* 16 bits right channel data */
|
||||||
|
#define LPC31_I2S_L24BIT_OFFSET 0x008 /* 24 bits left channel data */
|
||||||
|
#define LPC31_I2S_R24BIT_OFFSET 0x00c /* 24 bits right channel data */
|
||||||
|
#define LPC31_I2S_INTSTATUS_OFFSET 0x010 /* FIFO status register */
|
||||||
|
#define LPC31_I2S_INTMASK_OFFSET 0x014 /* Interrupt Mask register */
|
||||||
|
#define LPC31_I2S_L32BIT_OFFSET(n) (0x020+((n)<<2))
|
||||||
|
#define LPC31_I2S_L32BIT0_OFFSET 0x020 /* 2x16 bits left channel data */
|
||||||
|
#define LPC31_I2S_L32BIT1_OFFSET 0x024 /* " " " " " " " " " " */
|
||||||
|
#define LPC31_I2S_L32BIT2_OFFSET 0x028 /* " " " " " " " " " " */
|
||||||
|
#define LPC31_I2S_L32BIT3_OFFSET 0x02c /* " " " " " " " " " " */
|
||||||
|
#define LPC31_I2S_L32BIT4_OFFSET 0x030 /* " " " " " " " " " " */
|
||||||
|
#define LPC31_I2S_L32BIT5_OFFSET 0x034 /* " " " " " " " " " " */
|
||||||
|
#define LPC31_I2S_L32BIT6_OFFSET 0x038 /* " " " " " " " " " " */
|
||||||
|
#define LPC31_I2S_L32BIT7_OFFSET 0x03c /* " " " " " " " " " " */
|
||||||
|
#define LPC31_I2S_R32BIT_OFFSET(n) (0x040+((n)<<2))
|
||||||
|
#define LPC31_I2S_R32BIT0_OFFSET 0x040 /* 2x16 bits right channel data */
|
||||||
|
#define LPC31_I2S_R32BIT1_OFFSET 0x044 /* " " " " " " " " " " */
|
||||||
|
#define LPC31_I2S_R32BIT2_OFFSET 0x048 /* " " " " " " " " " " */
|
||||||
|
#define LPC31_I2S_R32BIT3_OFFSET 0x04c /* " " " " " " " " " " */
|
||||||
|
#define LPC31_I2S_R32BIT4_OFFSET 0x050 /* " " " " " " " " " " */
|
||||||
|
#define LPC31_I2S_R32BIT5_OFFSET 0x054 /* " " " " " " " " " " */
|
||||||
|
#define LPC31_I2S_R32BIT6_OFFSET 0x058 /* " " " " " " " " " " */
|
||||||
|
#define LPC31_I2S_R32BIT7_OFFSET 0x05c /* " " " " " " " " " " */
|
||||||
|
#define LPC31_I2S_ILVD_OFFSET(n) (0x060+((n)<<2))
|
||||||
|
#define LPC31_I2S_ILVD0_OFFSET 0x060 /* Interleaved data */
|
||||||
|
#define LPC31_I2S_ILVD1_OFFSET 0x064 /* " " " " */
|
||||||
|
#define LPC31_I2S_ILVD2_OFFSET 0x068 /* " " " " */
|
||||||
|
#define LPC31_I2S_ILVD3_OFFSET 0x06c /* " " " " */
|
||||||
|
#define LPC31_I2S_ILVD4_OFFSET 0x070 /* " " " " */
|
||||||
|
#define LPC31_I2S_ILVD5_OFFSET 0x074 /* " " " " */
|
||||||
|
#define LPC31_I2S_ILVD6_OFFSET 0x078 /* " " " " */
|
||||||
|
#define LPC31_I2S_ILVD7_OFFSET 0x07c /* " " " " */
|
||||||
|
|
||||||
|
/* I2S register (virtual) addresses *************************************************************/
|
||||||
|
/* I2S configuration module registers */
|
||||||
|
|
||||||
|
#define LPC31_I2SCONFIG_FORMAT (LPC31_I2SCONFIG_VBASE+lPC313X_I2SCONFIG_FORMAT_OFFSET)
|
||||||
|
#define LPC31_I2SCONFIG_CFGMUX (LPC31_I2SCONFIG_VBASE+LPC31_I2SCONFIG_CFGMUX_OFFSET)
|
||||||
|
#define LPC31_I2SCONFIG_NSOFCNTR (LPC31_I2SCONFIG_VBASE+LPC31_I2SCONFIG_NSOFCNTR_OFFSET)
|
||||||
|
|
||||||
|
/* I2STX0 module registers */
|
||||||
|
|
||||||
|
#define LPC31_I2STX0_L16BIT (LPC31_I2STX0_VBASE+LPC31_I2S_L16BIT_OFFSET)
|
||||||
|
#define LPC31_I2STX0_R16BIT (LPC31_I2STX0_VBASE+LPC31_I2S_R16BIT_OFFSET)
|
||||||
|
#define LPC31_I2STX0_L24BIT (LPC31_I2STX0_VBASE+LPC31_I2S_L24BIT_OFFSET)
|
||||||
|
#define LPC31_I2STX0_R24BIT (LPC31_I2STX0_VBASE+LPC31_I2S_R24BIT_OFFSET)
|
||||||
|
#define LPC31_I2STX0_INTSTATUS (LPC31_I2STX0_VBASE+LPC31_I2S_INTSTATUS_OFFSET)
|
||||||
|
#define LPC31_I2STX0_INTMASK (LPC31_I2STX0_VBASE+LPC31_I2S_INTMASK_OFFSET)
|
||||||
|
#define LPC31_I2STX0_L32BIT(n) (LPC31_I2STX0_VBASE+LPC31_I2S_L32BIT_OFFSET(n))
|
||||||
|
#define LPC31_I2STX0_L32BIT0 (LPC31_I2STX0_VBASE+LPC31_I2S_L32BIT0_OFFSET)
|
||||||
|
#define LPC31_I2STX0_L32BIT1 (LPC31_I2STX0_VBASE+LPC31_I2S_L32BIT1_OFFSET)
|
||||||
|
#define LPC31_I2STX0_L32BIT2 (LPC31_I2STX0_VBASE+LPC31_I2S_L32BIT2_OFFSET)
|
||||||
|
#define LPC31_I2STX0_L32BIT3 (LPC31_I2STX0_VBASE+LPC31_I2S_L32BIT3_OFFSET)
|
||||||
|
#define LPC31_I2STX0_L32BIT4 (LPC31_I2STX0_VBASE+LPC31_I2S_L32BIT4_OFFSET)
|
||||||
|
#define LPC31_I2STX0_L32BIT5 (LPC31_I2STX0_VBASE+LPC31_I2S_L32BIT5_OFFSET)
|
||||||
|
#define LPC31_I2STX0_L32BIT6 (LPC31_I2STX0_VBASE+LPC31_I2S_L32BIT6_OFFSET)
|
||||||
|
#define LPC31_I2STX0_L32BIT7 (LPC31_I2STX0_VBASE+LPC31_I2S_L32BIT7_OFFSET)
|
||||||
|
#define LPC31_I2STX0_R32BIT(n) (LPC31_I2STX0_VBASE+LPC31_I2S_R32BIT_OFFSET(n))
|
||||||
|
#define LPC31_I2STX0_R32BIT0 (LPC31_I2STX0_VBASE+LPC31_I2S_R32BIT0_OFFSET)
|
||||||
|
#define LPC31_I2STX0_R32BIT1 (LPC31_I2STX0_VBASE+LPC31_I2S_R32BIT1_OFFSET)
|
||||||
|
#define LPC31_I2STX0_R32BIT2 (LPC31_I2STX0_VBASE+LPC31_I2S_R32BIT2_OFFSET)
|
||||||
|
#define LPC31_I2STX0_R32BIT3 (LPC31_I2STX0_VBASE+LPC31_I2S_R32BIT3_OFFSET)
|
||||||
|
#define LPC31_I2STX0_R32BIT4 (LPC31_I2STX0_VBASE+LPC31_I2S_R32BIT4_OFFSET)
|
||||||
|
#define LPC31_I2STX0_R32BIT5 (LPC31_I2STX0_VBASE+LPC31_I2S_R32BIT5_OFFSET)
|
||||||
|
#define LPC31_I2STX0_R32BIT6 (LPC31_I2STX0_VBASE+LPC31_I2S_R32BIT6_OFFSET)
|
||||||
|
#define LPC31_I2STX0_R32BIT7 (LPC31_I2STX0_VBASE+LPC31_I2S_R32BIT7_OFFSET)
|
||||||
|
#define LPC31_I2STX0_ILVD(n) (LPC31_I2STX0_VBASE+LPC31_I2S_ILVD_OFFSET(n))
|
||||||
|
#define LPC31_I2STX0_ILVD0 (LPC31_I2STX0_VBASE+LPC31_I2S_ILVD0_OFFSET)
|
||||||
|
#define LPC31_I2STX0_ILVD1 (LPC31_I2STX0_VBASE+LPC31_I2S_ILVD1_OFFSET)
|
||||||
|
#define LPC31_I2STX0_ILVD2 (LPC31_I2STX0_VBASE+LPC31_I2S_ILVD2_OFFSET)
|
||||||
|
#define LPC31_I2STX0_ILVD3 (LPC31_I2STX0_VBASE+LPC31_I2S_ILVD3_OFFSET)
|
||||||
|
#define LPC31_I2STX0_ILVD4 (LPC31_I2STX0_VBASE+LPC31_I2S_ILVD4_OFFSET)
|
||||||
|
#define LPC31_I2STX0_ILVD5 (LPC31_I2STX0_VBASE+LPC31_I2S_ILVD5_OFFSET)
|
||||||
|
#define LPC31_I2STX0_ILVD6 (LPC31_I2STX0_VBASE+LPC31_I2S_ILVD6_OFFSET)
|
||||||
|
#define LPC31_I2STX0_ILVD7 (LPC31_I2STX0_VBASE+LPC31_I2S_ILVD7_OFFSET)
|
||||||
|
|
||||||
|
/* I2STX1 module registers */
|
||||||
|
|
||||||
|
#define LPC31_I2STX1_L16BIT (LPC31_I2STX1_VBASE+LPC31_I2S_L16BIT_OFFSET)
|
||||||
|
#define LPC31_I2STX1_R16BIT (LPC31_I2STX1_VBASE+LPC31_I2S_R16BIT_OFFSET)
|
||||||
|
#define LPC31_I2STX1_L24BIT (LPC31_I2STX1_VBASE+LPC31_I2S_L24BIT_OFFSET)
|
||||||
|
#define LPC31_I2STX1_R24BIT (LPC31_I2STX1_VBASE+LPC31_I2S_R24BIT_OFFSET)
|
||||||
|
#define LPC31_I2STX1_INTSTATUS (LPC31_I2STX1_VBASE+LPC31_I2S_INTSTATUS_OFFSET)
|
||||||
|
#define LPC31_I2STX1_INTMASK (LPC31_I2STX1_VBASE+LPC31_I2S_INTMASK_OFFSET)
|
||||||
|
#define LPC31_I2STX1_L32BIT(n) (LPC31_I2STX1_VBASE+LPC31_I2S_L32BIT_OFFSET(n))
|
||||||
|
#define LPC31_I2STX1_L32BIT0 (LPC31_I2STX1_VBASE+LPC31_I2S_L32BIT0_OFFSET)
|
||||||
|
#define LPC31_I2STX1_L32BIT1 (LPC31_I2STX1_VBASE+LPC31_I2S_L32BIT1_OFFSET)
|
||||||
|
#define LPC31_I2STX1_L32BIT2 (LPC31_I2STX1_VBASE+LPC31_I2S_L32BIT2_OFFSET)
|
||||||
|
#define LPC31_I2STX1_L32BIT3 (LPC31_I2STX1_VBASE+LPC31_I2S_L32BIT3_OFFSET)
|
||||||
|
#define LPC31_I2STX1_L32BIT4 (LPC31_I2STX1_VBASE+LPC31_I2S_L32BIT4_OFFSET)
|
||||||
|
#define LPC31_I2STX1_L32BIT5 (LPC31_I2STX1_VBASE+LPC31_I2S_L32BIT5_OFFSET)
|
||||||
|
#define LPC31_I2STX1_L32BIT6 (LPC31_I2STX1_VBASE+LPC31_I2S_L32BIT6_OFFSET)
|
||||||
|
#define LPC31_I2STX1_L32BIT7 (LPC31_I2STX1_VBASE+LPC31_I2S_L32BIT7_OFFSET)
|
||||||
|
#define LPC31_I2STX1_R32BIT(n) (LPC31_I2STX1_VBASE+LPC31_I2S_R32BIT_OFFSET(n))
|
||||||
|
#define LPC31_I2STX1_R32BIT0 (LPC31_I2STX1_VBASE+LPC31_I2S_R32BIT0_OFFSET)
|
||||||
|
#define LPC31_I2STX1_R32BIT1 (LPC31_I2STX1_VBASE+LPC31_I2S_R32BIT1_OFFSET)
|
||||||
|
#define LPC31_I2STX1_R32BIT2 (LPC31_I2STX1_VBASE+LPC31_I2S_R32BIT2_OFFSET)
|
||||||
|
#define LPC31_I2STX1_R32BIT3 (LPC31_I2STX1_VBASE+LPC31_I2S_R32BIT3_OFFSET)
|
||||||
|
#define LPC31_I2STX1_R32BIT4 (LPC31_I2STX1_VBASE+LPC31_I2S_R32BIT4_OFFSET)
|
||||||
|
#define LPC31_I2STX1_R32BIT5 (LPC31_I2STX1_VBASE+LPC31_I2S_R32BIT5_OFFSET)
|
||||||
|
#define LPC31_I2STX1_R32BIT6 (LPC31_I2STX1_VBASE+LPC31_I2S_R32BIT6_OFFSET)
|
||||||
|
#define LPC31_I2STX1_R32BIT7 (LPC31_I2STX1_VBASE+LPC31_I2S_R32BIT7_OFFSET)
|
||||||
|
#define LPC31_I2STX1_ILVD(n) (LPC31_I2STX1_VBASE+LPC31_I2S_ILVD_OFFSET(n))
|
||||||
|
#define LPC31_I2STX1_ILVD0 (LPC31_I2STX1_VBASE+LPC31_I2S_ILVD0_OFFSET)
|
||||||
|
#define LPC31_I2STX1_ILVD1 (LPC31_I2STX1_VBASE+LPC31_I2S_ILVD1_OFFSET)
|
||||||
|
#define LPC31_I2STX1_ILVD2 (LPC31_I2STX1_VBASE+LPC31_I2S_ILVD2_OFFSET)
|
||||||
|
#define LPC31_I2STX1_ILVD3 (LPC31_I2STX1_VBASE+LPC31_I2S_ILVD3_OFFSET)
|
||||||
|
#define LPC31_I2STX1_ILVD4 (LPC31_I2STX1_VBASE+LPC31_I2S_ILVD4_OFFSET)
|
||||||
|
#define LPC31_I2STX1_ILVD5 (LPC31_I2STX1_VBASE+LPC31_I2S_ILVD5_OFFSET)
|
||||||
|
#define LPC31_I2STX1_ILVD6 (LPC31_I2STX1_VBASE+LPC31_I2S_ILVD6_OFFSET)
|
||||||
|
#define LPC31_I2STX1_ILVD7 (LPC31_I2STX1_VBASE+LPC31_I2S_ILVD7_OFFSET)
|
||||||
|
|
||||||
|
/* I2SRX0 module registers */
|
||||||
|
|
||||||
|
#define LPC31_I2SRX0_L16BIT (LPC31_I2SRX0_VBASE+LPC31_I2S_L16BIT_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_R16BIT (LPC31_I2SRX0_VBASE+LPC31_I2S_R16BIT_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_L24BIT (LPC31_I2SRX0_VBASE+LPC31_I2S_L24BIT_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_R24BIT (LPC31_I2SRX0_VBASE+LPC31_I2S_R24BIT_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_INTSTATUS (LPC31_I2SRX0_VBASE+LPC31_I2S_INTSTATUS_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_INTMASK (LPC31_I2SRX0_VBASE+LPC31_I2S_INTMASK_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_L32BIT(n) (LPC31_I2SRX0_VBASE+LPC31_I2S_L32BIT_OFFSET(n))
|
||||||
|
#define LPC31_I2SRX0_L32BIT0 (LPC31_I2SRX0_VBASE+LPC31_I2S_L32BIT0_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_L32BIT1 (LPC31_I2SRX0_VBASE+LPC31_I2S_L32BIT1_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_L32BIT2 (LPC31_I2SRX0_VBASE+LPC31_I2S_L32BIT2_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_L32BIT3 (LPC31_I2SRX0_VBASE+LPC31_I2S_L32BIT3_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_L32BIT4 (LPC31_I2SRX0_VBASE+LPC31_I2S_L32BIT4_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_L32BIT5 (LPC31_I2SRX0_VBASE+LPC31_I2S_L32BIT5_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_L32BIT6 (LPC31_I2SRX0_VBASE+LPC31_I2S_L32BIT6_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_L32BIT7 (LPC31_I2SRX0_VBASE+LPC31_I2S_L32BIT7_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_R32BIT(n) (LPC31_I2SRX0_VBASE+LPC31_I2S_R32BIT_OFFSET(n))
|
||||||
|
#define LPC31_I2SRX0_R32BIT0 (LPC31_I2SRX0_VBASE+LPC31_I2S_R32BIT0_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_R32BIT1 (LPC31_I2SRX0_VBASE+LPC31_I2S_R32BIT1_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_R32BIT2 (LPC31_I2SRX0_VBASE+LPC31_I2S_R32BIT2_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_R32BIT3 (LPC31_I2SRX0_VBASE+LPC31_I2S_R32BIT3_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_R32BIT4 (LPC31_I2SRX0_VBASE+LPC31_I2S_R32BIT4_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_R32BIT5 (LPC31_I2SRX0_VBASE+LPC31_I2S_R32BIT5_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_R32BIT6 (LPC31_I2SRX0_VBASE+LPC31_I2S_R32BIT6_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_R32BIT7 (LPC31_I2SRX0_VBASE+LPC31_I2S_R32BIT7_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_ILVD(n) (LPC31_I2SRX0_VBASE+LPC31_I2S_ILVD_OFFSET(n))
|
||||||
|
#define LPC31_I2SRX0_ILVD0 (LPC31_I2SRX0_VBASE+LPC31_I2S_ILVD0_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_ILVD1 (LPC31_I2SRX0_VBASE+LPC31_I2S_ILVD1_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_ILVD2 (LPC31_I2SRX0_VBASE+LPC31_I2S_ILVD2_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_ILVD3 (LPC31_I2SRX0_VBASE+LPC31_I2S_ILVD3_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_ILVD4 (LPC31_I2SRX0_VBASE+LPC31_I2S_ILVD4_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_ILVD5 (LPC31_I2SRX0_VBASE+LPC31_I2S_ILVD5_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_ILVD6 (LPC31_I2SRX0_VBASE+LPC31_I2S_ILVD6_OFFSET)
|
||||||
|
#define LPC31_I2SRX0_ILVD7 (LPC31_I2SRX0_VBASE+LPC31_I2S_ILVD7_OFFSET)
|
||||||
|
|
||||||
|
/* I2SRX1 module registers */
|
||||||
|
|
||||||
|
#define LPC31_I2SRX1_L16BIT (LPC31_I2SRX1_VBASE+LPC31_I2S_L16BIT_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_R16BIT (LPC31_I2SRX1_VBASE+LPC31_I2S_R16BIT_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_L24BIT (LPC31_I2SRX1_VBASE+LPC31_I2S_L24BIT_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_R24BIT (LPC31_I2SRX1_VBASE+LPC31_I2S_R24BIT_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_INTSTATUS (LPC31_I2SRX1_VBASE+LPC31_I2S_INTSTATUS_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_INTMASK (LPC31_I2SRX1_VBASE+LPC31_I2S_INTMASK_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_L32BIT(n) (LPC31_I2SRX1_VBASE+LPC31_I2S_L32BIT_OFFSET(n))
|
||||||
|
#define LPC31_I2SRX1_L32BIT0 (LPC31_I2SRX1_VBASE+LPC31_I2S_L32BIT0_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_L32BIT1 (LPC31_I2SRX1_VBASE+LPC31_I2S_L32BIT1_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_L32BIT2 (LPC31_I2SRX1_VBASE+LPC31_I2S_L32BIT2_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_L32BIT3 (LPC31_I2SRX1_VBASE+LPC31_I2S_L32BIT3_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_L32BIT4 (LPC31_I2SRX1_VBASE+LPC31_I2S_L32BIT4_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_L32BIT5 (LPC31_I2SRX1_VBASE+LPC31_I2S_L32BIT5_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_L32BIT6 (LPC31_I2SRX1_VBASE+LPC31_I2S_L32BIT6_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_L32BIT7 (LPC31_I2SRX1_VBASE+LPC31_I2S_L32BIT7_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_R32BIT(n) (LPC31_I2SRX1_VBASE+LPC31_I2S_R32BIT_OFFSET(n))
|
||||||
|
#define LPC31_I2SRX1_R32BIT0 (LPC31_I2SRX1_VBASE+LPC31_I2S_R32BIT0_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_R32BIT1 (LPC31_I2SRX1_VBASE+LPC31_I2S_R32BIT1_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_R32BIT2 (LPC31_I2SRX1_VBASE+LPC31_I2S_R32BIT2_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_R32BIT3 (LPC31_I2SRX1_VBASE+LPC31_I2S_R32BIT3_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_R32BIT4 (LPC31_I2SRX1_VBASE+LPC31_I2S_R32BIT4_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_R32BIT5 (LPC31_I2SRX1_VBASE+LPC31_I2S_R32BIT5_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_R32BIT6 (LPC31_I2SRX1_VBASE+LPC31_I2S_R32BIT6_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_R32BIT7 (LPC31_I2SRX1_VBASE+LPC31_I2S_R32BIT7_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_ILVD(n) (LPC31_I2SRX1_VBASE+LPC31_I2S_ILVD_OFFSET(n))
|
||||||
|
#define LPC31_I2SRX1_ILVD0 (LPC31_I2SRX1_VBASE+LPC31_I2S_ILVD0_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_ILVD1 (LPC31_I2SRX1_VBASE+LPC31_I2S_ILVD1_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_ILVD2 (LPC31_I2SRX1_VBASE+LPC31_I2S_ILVD2_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_ILVD3 (LPC31_I2SRX1_VBASE+LPC31_I2S_ILVD3_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_ILVD4 (LPC31_I2SRX1_VBASE+LPC31_I2S_ILVD4_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_ILVD5 (LPC31_I2SRX1_VBASE+LPC31_I2S_ILVD5_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_ILVD6 (LPC31_I2SRX1_VBASE+LPC31_I2S_ILVD6_OFFSET)
|
||||||
|
#define LPC31_I2SRX1_ILVD7 (LPC31_I2SRX1_VBASE+LPC31_I2S_ILVD7_OFFSET)
|
||||||
|
|
||||||
|
/* I2S register bit definitions *****************************************************************/
|
||||||
|
/* I2S configuration module offset */
|
||||||
|
|
||||||
|
/* I2SCONFIG_FORMAT address 0x16000000 */
|
||||||
|
|
||||||
|
#define I2SCONFIG_FORMAT_I2SRX1_SHIFT (9) /* Bits 9-11: I2SRX1 I2S output format */
|
||||||
|
#define I2SCONFIG_FORMAT_I2SRX1_MASK (7 << I2SCONFIG_FORMAT_I2SRX1_SHIFT)
|
||||||
|
# define I2SCONFIG_FORMAT_I2SRX1_I2S (3 << I2SCONFIG_FORMAT_I2SRX1_SHIFT) /* I2S */
|
||||||
|
# define I2SCONFIG_FORMAT_I2SRX1_16BIT (4 << I2SCONFIG_FORMAT_I2SRX1_SHIFT) /* LSB justified 16 bits */
|
||||||
|
# define I2SCONFIG_FORMAT_I2SRX1_18BIT (5 << I2SCONFIG_FORMAT_I2SRX1_SHIFT) /* LSB justified 18 bits */
|
||||||
|
# define I2SCONFIG_FORMAT_I2SRX1_20BIT (6 << I2SCONFIG_FORMAT_I2SRX1_SHIFT) /* LSB justified 20 bits */
|
||||||
|
# define I2SCONFIG_FORMAT_I2SRX1_24BIT (7 << I2SCONFIG_FORMAT_I2SRX1_SHIFT) /* LSB justified 24 bits */
|
||||||
|
#define I2SCONFIG_FORMAT_I2SRX0_SHIFT (6) /* Bits 6-8: I2SRX0 I2S output format */
|
||||||
|
#define I2SCONFIG_FORMAT_I2SRX0_MASK (7 << I2SCONFIG_FORMAT_I2SRX0_SHIFT)
|
||||||
|
# define I2SCONFIG_FORMAT_I2SRX0_I2S (3 << I2SCONFIG_FORMAT_I2SRX0_SHIFT) /* I2S */
|
||||||
|
# define I2SCONFIG_FORMAT_I2SRX0_16BIT (4 << I2SCONFIG_FORMAT_I2SRX0_SHIFT) /* LSB justified 16 bits */
|
||||||
|
# define I2SCONFIG_FORMAT_I2SRX0_18BIT (5 << I2SCONFIG_FORMAT_I2SRX0_SHIFT) /* LSB justified 18 bits */
|
||||||
|
# define I2SCONFIG_FORMAT_I2SRX0_20BIT (6 << I2SCONFIG_FORMAT_I2SRX0_SHIFT) /* LSB justified 20 bits */
|
||||||
|
# define I2SCONFIG_FORMAT_I2SRX0_24BIT (7 << I2SCONFIG_FORMAT_I2SRX0_SHIFT) /* LSB justified 24 bits */
|
||||||
|
#define I2SCONFIG_FORMAT_I2STX1_SHIFT (3) /* Bits 3-5: 2STX1 I2S input format */
|
||||||
|
#define I2SCONFIG_FORMAT_I2STX1_MASK (7 << I2SCONFIG_FORMAT_I2STX1_SHIFT)
|
||||||
|
# define I2SCONFIG_FORMAT_I2STX1_I2S (3 << I2SCONFIG_FORMAT_I2STX1_SHIFT) /* I2S */
|
||||||
|
# define I2SCONFIG_FORMAT_I2STX1_16BIT (4 << I2SCONFIG_FORMAT_I2STX1_SHIFT) /* LSB justified 16 bits */
|
||||||
|
# define I2SCONFIG_FORMAT_I2STX1_18BIT (5 << I2SCONFIG_FORMAT_I2STX1_SHIFT) /* LSB justified 18 bits */
|
||||||
|
# define I2SCONFIG_FORMAT_I2STX1_20BIT (6 << I2SCONFIG_FORMAT_I2STX1_SHIFT) /* LSB justified 20 bits */
|
||||||
|
# define I2SCONFIG_FORMAT_I2STX1_24BIT (7 << I2SCONFIG_FORMAT_I2STX1_SHIFT) /* LSB justified 24 bits */
|
||||||
|
#define I2SCONFIG_FORMAT_I2STX0_SHIFT (0) /* Bits 0-2: I2STX0 I2S input format */
|
||||||
|
#define I2SCONFIG_FORMAT_I2STX0_MASK (7 << I2SCONFIG_FORMAT_I2STX0_SHIFT)
|
||||||
|
# define I2SCONFIG_FORMAT_I2STX0_I2S (3 << I2SCONFIG_FORMAT_I2STX0_SHIFT) /* I2S */
|
||||||
|
# define I2SCONFIG_FORMAT_I2STX0_16BIT (4 << I2SCONFIG_FORMAT_I2STX0_SHIFT) /* LSB justified 16 bits */
|
||||||
|
# define I2SCONFIG_FORMAT_I2STX0_18BIT (5 << I2SCONFIG_FORMAT_I2STX0_SHIFT) /* LSB justified 18 bits */
|
||||||
|
# define I2SCONFIG_FORMAT_I2STX0_20BIT (6 << I2SCONFIG_FORMAT_I2STX0_SHIFT) /* LSB justified 20 bits */
|
||||||
|
# define I2SCONFIG_FORMAT_I2STX0_24BIT (7 << I2SCONFIG_FORMAT_I2STX0_SHIFT) /* LSB justified 24 bits */
|
||||||
|
|
||||||
|
/* II2SCONFIG_CFGMUX address 0x16000004 */
|
||||||
|
|
||||||
|
#define I2SCONFIG_CFGMUX_I2SRX1OEN (1 << 2) /* Bit 2: Selects faster mode for I2SRX1 */
|
||||||
|
#define I2SCONFIG_CFGMUX_I2SRX0OEN (1 << 1) /* Bit 1: Slects master mode for I2SRX0 */
|
||||||
|
|
||||||
|
/* I2SCONFIG_NSOFCNT address 0x16000010 */
|
||||||
|
|
||||||
|
/************************************************************************************************
|
||||||
|
* Public Types
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
/************************************************************************************************
|
||||||
|
* Public Data
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
/************************************************************************************************
|
||||||
|
* Public Functions
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_I2S_H */
|
||||||
Executable
+198
@@ -0,0 +1,198 @@
|
|||||||
|
/************************************************************************************************
|
||||||
|
* arch/arm/src/lpc31xx/lpc31_intc.h
|
||||||
|
*
|
||||||
|
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
||||||
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||||
|
* used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||||
|
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||||
|
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_INTC_H
|
||||||
|
#define __ARCH_ARM_SRC_LPC31XX_LPC31_INTC_H
|
||||||
|
|
||||||
|
/************************************************************************************************
|
||||||
|
* Included Files
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
#include <nuttx/config.h>
|
||||||
|
#include "lpc31_memorymap.h"
|
||||||
|
|
||||||
|
/************************************************************************************************
|
||||||
|
* Pre-processor Definitions
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
/* INTC register base address *******************************************************************/
|
||||||
|
|
||||||
|
#define LPC31_INTC_VBASE (LPC31_INTC_VSECTION)
|
||||||
|
#define LPC31_INTC_PBASE (LPC31_INTC_PSECTION)
|
||||||
|
|
||||||
|
/* INTC register offsets (with respect to the base of the INTC domain) **************************/
|
||||||
|
|
||||||
|
#define LPC31_INTC_PRIORITYMASK0_OFFSET 0x000 /* Interrupt target 0 priority threshold */
|
||||||
|
#define LPC31_INTC_PRIORITYMASK1_OFFSET 0x004 /* Interrupt target 0 priority threshold */
|
||||||
|
#define LPC31_INTC_VECTOR0_OFFSET 0x100 /* Vector register for target 0 => nIRQ */
|
||||||
|
#define LPC31_INTC_VECTOR1_OFFSET 0x104 /* Vector register for target 1 => nFIQ */
|
||||||
|
#define LPC31_INTC_PENDING_OFFSET 0x200 /* Status of interrupt request 1..29 */
|
||||||
|
#define LPC31_INTC_FEATURES_OFFSET 0x300 /* Interrupt controller configuration */
|
||||||
|
#define LPC31_INTC_REQUEST_OFFSET(n) (0x400+((n) << 2))
|
||||||
|
#define LPC31_INTC_REQUEST1_OFFSET 0x404 /* Interrupt request 1 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST2_OFFSET 0x408 /* Interrupt request 2 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST3_OFFSET 0x40c /* Interrupt request 3 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST4_OFFSET 0x410 /* Interrupt request 4 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST5_OFFSET 0x414 /* Interrupt request 5 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST6_OFFSET 0x418 /* Interrupt request 6 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST7_OFFSET 0x41c /* Interrupt request 7 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST8_OFFSET 0x420 /* Interrupt request 8 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST9_OFFSET 0x424 /* Interrupt request 9 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST10_OFFSET 0x428 /* Interrupt request 10 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST11_OFFSET 0x42c /* Interrupt request 11 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST12_OFFSET 0x430 /* Interrupt request 12 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST13_OFFSET 0x434 /* Interrupt request 13 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST14_OFFSET 0x438 /* Interrupt request 14 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST15_OFFSET 0x43c /* Interrupt request 15 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST16_OFFSET 0x440 /* Interrupt request 16 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST17_OFFSET 0x444 /* Interrupt request 17 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST18_OFFSET 0x448 /* Interrupt request 18 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST19_OFFSET 0x44c /* Interrupt request 19 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST20_OFFSET 0x450 /* Interrupt request 20 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST21_OFFSET 0x454 /* Interrupt request 21 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST22_OFFSET 0x458 /* Interrupt request 22 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST23_OFFSET 0x45c /* Interrupt request 23 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST24_OFFSET 0x460 /* Interrupt request 24 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST25_OFFSET 0x464 /* Interrupt request 25 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST26_OFFSET 0x468 /* Interrupt request 26 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST27_OFFSET 0x46c /* Interrupt request 27 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST28_OFFSET 0x470 /* Interrupt request 28 configuration */
|
||||||
|
#define LPC31_INTC_REQUEST29_OFFSET 0x474 /* Interrupt request 29 configuration */
|
||||||
|
|
||||||
|
/* INTC register (virtual) addresses ************************************************************/
|
||||||
|
|
||||||
|
#define LPC31_INTC_PRIORITYMASK0 (LPC31_INTC_VBASE+LPC31_INTC_PRIORITYMASK0_OFFSET)
|
||||||
|
#define LPC31_INTC_PRIORITYMASK1 (LPC31_INTC_VBASE+LPC31_INTC_PRIORITYMASK1_OFFSET)
|
||||||
|
#define LPC31_INTC_VECTOR0 (LPC31_INTC_VBASE+LPC31_INTC_VECTOR0_OFFSET)
|
||||||
|
#define LPC31_INTC_VECTOR1 (LPC31_INTC_VBASE+LPC31_INTC_VECTOR1_OFFSET)
|
||||||
|
#define LPC31_INTC_PENDING (LPC31_INTC_VBASE+LPC31_INTC_PENDING_OFFSET)
|
||||||
|
#define LPC31_INTC_FEATURES (LPC31_INTC_VBASE+LPC31_INTC_FEATURES_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST(n) (LPC31_INTC_VBASE+LPC31_INTC_REQUEST_OFFSET(n))
|
||||||
|
#define LPC31_INTC_REQUEST1 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST1_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST2 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST2_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST3 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST3_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST4 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST4_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST5 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST5_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST6 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST6_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST7 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST7_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST8 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST8_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST9 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST9_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST10 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST10_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST11 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST11_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST12 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST12_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST13 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST13_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST14 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST14_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST15 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST15_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST16 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST16_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST17 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST17_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST18 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST18_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST19 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST19_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST20 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST20_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST21 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST21_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST22 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST22_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST23 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST23_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST24 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST24_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST25 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST25_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST26 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST26_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST27 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST27_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST28 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST28_OFFSET)
|
||||||
|
#define LPC31_INTC_REQUEST29 (LPC31_INTC_VBASE+LPC31_INTC_REQUEST29_OFFSET)
|
||||||
|
|
||||||
|
/* INTC register bit definitions ****************************************************************/
|
||||||
|
|
||||||
|
/* Interrupt priority mask register (INT_PRIORITYMASK0 address 0x60000000 and
|
||||||
|
* INTC_PRIORITYMASK1 address 0x60000004)
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define INTC_PRIORITYMASK_PRIOLIMIT_SHIFT (0) /* Bits 0-7: Priority threshold for interrupts */
|
||||||
|
#define INTC_PRIORITYMASK_PRIOLIMIT_MASK (255 << INTC_PRIORITYMASK_PRIOLIMIT_MASK)
|
||||||
|
|
||||||
|
/* Interrupt vector registers (INTC_VECTOR0 address 0x60000100 and INTC_VECTOR1 address
|
||||||
|
* 0x60000104)
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define INTC_VECTOR_TABLEADDR_SHIFT (11) /* Bits 11-31: Table start address */
|
||||||
|
#define INTC_VECTOR_TABLEADDR_MASK (0x001fffff << INTC_VECTOR_TABLEADDR_SHIFT)
|
||||||
|
#define INTC_VECTOR_INDEX_SHIFT (3) /* Bits 3-10: IRQ number of interrupt */
|
||||||
|
#define INTC_VECTOR_INDEX_MASK (255 << INTC_VECTOR_INDEX_SHIFT)
|
||||||
|
|
||||||
|
/* Interrupt pending register (INT_PENDING1_31, address 0x60000200) */
|
||||||
|
|
||||||
|
#define INTC_PENDING_SHIFT (1) /* Bits 1-29: Pending interrupt request */
|
||||||
|
#define INTC_PENDING_MASK (0x1fffffff << INTC_PENDING_SHIFT)
|
||||||
|
|
||||||
|
/* Interrupt controller features register (INT_FEATURES, address 0x60000300) */
|
||||||
|
|
||||||
|
#define INTC_FEATURES_T_SHIFT (16) /* Bits 16-21: Number interrupt targets supported (+1) */
|
||||||
|
#define INTC_FEATURES_T_MASK (63 << INTC_FEATURES_T_SHIFT)
|
||||||
|
#define INTC_FEATURES_P_SHIFT (8) /* Bits 8-15: Number priority levels supported */
|
||||||
|
#define INTC_FEATURES_P_MASK (255 << INTC_FEATURES_P_SHIFT)
|
||||||
|
#define INTC_FEATURES_N_SHIFT (0) /* Bits 0-7: Number interrupt request inputs */
|
||||||
|
#define INTC_FEATURES_N_MASK (255 << INTC_FEATURES_N_SHIFT)
|
||||||
|
|
||||||
|
/* Interrupt request registers (INT_REQUEST1 address 0x60000404 to INTC_REQUEST29 address
|
||||||
|
* 0x60000474)
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define INTC_REQUEST_PENDING (1 << 31) /* Bit 31: Pending interrupt request */
|
||||||
|
#define INTC_REQUEST_SETSWINT (1 << 30) /* Bit 30: Set software interrupt request */
|
||||||
|
#define INTC_REQUEST_CLRSWINT (1 << 29) /* Bit 29: Clear software interrupt request */
|
||||||
|
#define INTC_REQUEST_WEPRIO (1 << 28) /* Bit 28: Write Enable PRIORITY_LEVEL */
|
||||||
|
#define INTC_REQUEST_WETARGET (1 << 27) /* Bit 27: Write Enable TARGET */
|
||||||
|
#define INTC_REQUEST_WEENABLE (1 << 26) /* Bit 26: Write Enable ENABLE */
|
||||||
|
#define INTC_REQUEST_WEACTLOW (1 << 25) /* Bit 25: Write Enable ACTIVE_LOW */
|
||||||
|
#define INTC_REQUEST_ACTLOW (1 << 17) /* Bit 17: Active Low */
|
||||||
|
#define INTC_REQUEST_ENABLE (1 << 16) /* Bit 16: Enable interrupt request */
|
||||||
|
#define INTC_REQUEST_TARGET_SHIFT (8) /* Bits 8-13: Interrupt target */
|
||||||
|
#define INTC_REQUEST_TARGET_MASK (63 << INTC_REQUEST_TARGET_SHIFT)
|
||||||
|
# define INTC_REQUEST_TARGET_IRQ (INTC_REQUEST_WETARGET | (0 << INTC_REQUEST_TARGET_SHIFT)) /* Proc interrupt request 0: IRQ */
|
||||||
|
# define INTC_REQUEST_TARGET_FIQ (INTC_REQUEST_WETARGET | (1 << INTC_REQUEST_TARGET_SHIFT)) /* Proc interrupt request 1: FIQ */
|
||||||
|
#define INTC_REQUEST_PRIOLEVEL_SHIFT (0) /* Bits 0-7: Priority level */
|
||||||
|
#define INTC_REQUEST_PRIOLEVEL_MASK (255 << INTC_REQUEST_PRIOLEVEL_SHIFT)
|
||||||
|
# define INTC_REQUEST_PRIOLEVEL(n) (((n) << INTC_REQUEST_PRIOLEVEL_SHIFT) & INTC_REQUEST_PRIOLEVEL_MASK)
|
||||||
|
|
||||||
|
/************************************************************************************************
|
||||||
|
* Public Types
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
/************************************************************************************************
|
||||||
|
* Public Data
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
/************************************************************************************************
|
||||||
|
* Public Functions
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_INTC_H */
|
||||||
@@ -1,7 +1,7 @@
|
|||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_internal.h
|
* arch/arm/src/lpc31xx/lpc31_internal.h
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
*
|
*
|
||||||
* Redistribution and use in source and binary forms, with or without
|
* Redistribution and use in source and binary forms, with or without
|
||||||
@@ -33,8 +33,8 @@
|
|||||||
*
|
*
|
||||||
************************************************************************************/
|
************************************************************************************/
|
||||||
|
|
||||||
#ifndef __ARCH_ARM_SRC_LPC313X_LPC313X_INTERNAL_H
|
#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_INTERNAL_H
|
||||||
#define __ARCH_ARM_SRC_LPC313X_LPC313X_INTERNAL_H
|
#define __ARCH_ARM_SRC_LPC31XX_LPC31_INTERNAL_H
|
||||||
|
|
||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* Included Files
|
* Included Files
|
||||||
@@ -49,7 +49,7 @@
|
|||||||
#include "up_internal.h"
|
#include "up_internal.h"
|
||||||
#include "up_arch.h"
|
#include "up_arch.h"
|
||||||
#include "chip.h"
|
#include "chip.h"
|
||||||
#include "lpc313x_ioconfig.h"
|
#include "lpc31_ioconfig.h"
|
||||||
|
|
||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* Definitions
|
* Definitions
|
||||||
@@ -91,18 +91,18 @@ static inline void gpio_configinput(uint32_t ioconfig, uint32_t bit)
|
|||||||
{
|
{
|
||||||
uint32_t regaddr;
|
uint32_t regaddr;
|
||||||
|
|
||||||
regaddr = ioconfig + LPC313X_IOCONFIG_MODE0RESET_OFFSET;
|
regaddr = ioconfig + LPC31_IOCONFIG_MODE0RESET_OFFSET;
|
||||||
putreg32(bit, regaddr);
|
putreg32(bit, regaddr);
|
||||||
|
|
||||||
regaddr = ioconfig + LPC313X_IOCONFIG_MODE1RESET_OFFSET;
|
regaddr = ioconfig + LPC31_IOCONFIG_MODE1RESET_OFFSET;
|
||||||
putreg32(bit, regaddr);
|
putreg32(bit, regaddr);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Return the current state of an input GPIO pin */
|
/* Return the current state of an input GPIO pin */
|
||||||
|
|
||||||
static inline bool lpc313x_gpioread(uint32_t ioconfig, uint32_t bit)
|
static inline bool lpc31_gpioread(uint32_t ioconfig, uint32_t bit)
|
||||||
{
|
{
|
||||||
uint32_t regaddr = ioconfig + LPC313X_IOCONFIG_PINS_OFFSET;
|
uint32_t regaddr = ioconfig + LPC31_IOCONFIG_PINS_OFFSET;
|
||||||
return (getreg32(regaddr) & bit) != 0;
|
return (getreg32(regaddr) & bit) != 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -112,10 +112,10 @@ static inline void gpio_configdev(uint32_t ioconfig, uint32_t bit)
|
|||||||
{
|
{
|
||||||
uint32_t regaddr;
|
uint32_t regaddr;
|
||||||
|
|
||||||
regaddr = ioconfig + LPC313X_IOCONFIG_MODE1RESET_OFFSET;
|
regaddr = ioconfig + LPC31_IOCONFIG_MODE1RESET_OFFSET;
|
||||||
putreg32(bit, regaddr);
|
putreg32(bit, regaddr);
|
||||||
|
|
||||||
regaddr = ioconfig + LPC313X_IOCONFIG_MODE0SET_OFFSET;
|
regaddr = ioconfig + LPC31_IOCONFIG_MODE0SET_OFFSET;
|
||||||
putreg32(bit, regaddr);
|
putreg32(bit, regaddr);
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -125,10 +125,10 @@ static inline void gpio_outputlow(uint32_t ioconfig, uint32_t bit)
|
|||||||
{
|
{
|
||||||
uint32_t regaddr;
|
uint32_t regaddr;
|
||||||
|
|
||||||
regaddr = ioconfig + LPC313X_IOCONFIG_MODE1SET_OFFSET;
|
regaddr = ioconfig + LPC31_IOCONFIG_MODE1SET_OFFSET;
|
||||||
putreg32(bit, regaddr);
|
putreg32(bit, regaddr);
|
||||||
|
|
||||||
regaddr = ioconfig + LPC313X_IOCONFIG_MODE0RESET_OFFSET;
|
regaddr = ioconfig + LPC31_IOCONFIG_MODE0RESET_OFFSET;
|
||||||
putreg32(bit, regaddr);
|
putreg32(bit, regaddr);
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -138,10 +138,10 @@ static inline void gpio_outputhigh(uint32_t ioconfig, uint32_t bit)
|
|||||||
{
|
{
|
||||||
uint32_t regaddr;
|
uint32_t regaddr;
|
||||||
|
|
||||||
regaddr = ioconfig + LPC313X_IOCONFIG_MODE1SET_OFFSET;
|
regaddr = ioconfig + LPC31_IOCONFIG_MODE1SET_OFFSET;
|
||||||
putreg32(bit, regaddr);
|
putreg32(bit, regaddr);
|
||||||
|
|
||||||
regaddr = ioconfig + LPC313X_IOCONFIG_MODE0SET_OFFSET;
|
regaddr = ioconfig + LPC31_IOCONFIG_MODE0SET_OFFSET;
|
||||||
putreg32(bit, regaddr);
|
putreg32(bit, regaddr);
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -150,43 +150,43 @@ static inline void gpio_outputhigh(uint32_t ioconfig, uint32_t bit)
|
|||||||
************************************************************************************/
|
************************************************************************************/
|
||||||
|
|
||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* Name: lpc313x_lowsetup
|
* Name: lpc31_lowsetup
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Called early in up_boot. Performs chip-common low level initialization.
|
* Called early in up_boot. Performs chip-common low level initialization.
|
||||||
*
|
*
|
||||||
************************************************************************************/
|
************************************************************************************/
|
||||||
|
|
||||||
EXTERN void lpc313x_lowsetup(void);
|
EXTERN void lpc31_lowsetup(void);
|
||||||
|
|
||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* Name: lpc313x_clockconfig
|
* Name: lpc31_clockconfig
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Called to change to new clock based on settings in board.h
|
* Called to change to new clock based on settings in board.h
|
||||||
*
|
*
|
||||||
************************************************************************************/
|
************************************************************************************/
|
||||||
|
|
||||||
EXTERN void lpc313x_clockconfig(void);
|
EXTERN void lpc31_clockconfig(void);
|
||||||
|
|
||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* Name: lpc313x_spiselect and lpc313x_spistatus
|
* Name: lpc31_spiselect and lpc31_spistatus
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* The external functions, lpc313x_spiselect, lpc313x_spistatus, and
|
* The external functions, lpc31_spiselect, lpc31_spistatus, and
|
||||||
* lpc313x_spicmddata must be provided by board-specific logic. These are
|
* lpc31_spicmddata must be provided by board-specific logic. These are
|
||||||
* implementations of the select, status, and cmddata methods of the SPI interface
|
* implementations of the select, status, and cmddata methods of the SPI interface
|
||||||
* defined by struct spi_ops_s (see include/nuttx/spi.h). All other methods
|
* defined by struct spi_ops_s (see include/nuttx/spi.h). All other methods
|
||||||
* (including up_spiinitialize()) are provided by common LPC313X logic. To use
|
* (including up_spiinitialize()) are provided by common LPC31XX logic. To use
|
||||||
* this common SPI logic on your board:
|
* this common SPI logic on your board:
|
||||||
*
|
*
|
||||||
* 1. Provide logic in lpc313x_boardinitialize() to configure SPI chip select
|
* 1. Provide logic in lpc31_boardinitialize() to configure SPI chip select
|
||||||
* pins.
|
* pins.
|
||||||
* 2. Provide lpc313x_spiselect() and lpc313x_spistatus() functions in your
|
* 2. Provide lpc31_spiselect() and lpc31_spistatus() functions in your
|
||||||
* board-specific logic. These functions will perform chip selection and
|
* board-specific logic. These functions will perform chip selection and
|
||||||
* status operations using GPIOs in the way your board is configured.
|
* status operations using GPIOs in the way your board is configured.
|
||||||
* 3. If CONFIG_SPI_CMDDATA is selected in your NuttX configuration, provide
|
* 3. If CONFIG_SPI_CMDDATA is selected in your NuttX configuration, provide
|
||||||
* the lpc313x_spicmddata() function in your board-specific logic. This
|
* the lpc31_spicmddata() function in your board-specific logic. This
|
||||||
* function will perform cmd/data selection operations using GPIOs in the
|
* function will perform cmd/data selection operations using GPIOs in the
|
||||||
* way your board is configured.
|
* way your board is configured.
|
||||||
* 4. Add a calls to up_spiinitialize() in your low level application
|
* 4. Add a calls to up_spiinitialize() in your low level application
|
||||||
@@ -200,18 +200,18 @@ EXTERN void lpc313x_clockconfig(void);
|
|||||||
|
|
||||||
struct spi_dev_s;
|
struct spi_dev_s;
|
||||||
enum spi_dev_e;
|
enum spi_dev_e;
|
||||||
EXTERN void lpc313x_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
|
EXTERN void lpc31_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
|
||||||
EXTERN uint8_t lpc313x_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
EXTERN uint8_t lpc31_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||||
#ifdef CONFIG_SPI_CMDDATA
|
#ifdef CONFIG_SPI_CMDDATA
|
||||||
EXTERN int lpc313x_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
EXTERN int lpc31_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* Name: lpc313x_usbpullup
|
* Name: lpc31_usbpullup
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* If USB is supported and the board supports a pullup via GPIO (for USB software
|
* If USB is supported and the board supports a pullup via GPIO (for USB software
|
||||||
* connect and disconnect), then the board software must provide lpc313x_pullup.
|
* connect and disconnect), then the board software must provide lpc31_pullup.
|
||||||
* See include/nuttx/usb/usbdev.h for additional description of this method.
|
* See include/nuttx/usb/usbdev.h for additional description of this method.
|
||||||
* Alternatively, if no pull-up GPIO the following EXTERN can be redefined to be
|
* Alternatively, if no pull-up GPIO the following EXTERN can be redefined to be
|
||||||
* NULL.
|
* NULL.
|
||||||
@@ -219,13 +219,13 @@ EXTERN int lpc313x_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, b
|
|||||||
************************************************************************************/
|
************************************************************************************/
|
||||||
|
|
||||||
struct usbdev_s;
|
struct usbdev_s;
|
||||||
EXTERN int lpc313x_usbpullup(FAR struct usbdev_s *dev, bool enable);
|
EXTERN int lpc31_usbpullup(FAR struct usbdev_s *dev, bool enable);
|
||||||
|
|
||||||
/************************************************************************************
|
/************************************************************************************
|
||||||
* Name: lpc313x_usbsuspend
|
* Name: lpc31_usbsuspend
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Board logic must provide the lpc313x_usbsuspend logic if the USBDEV driver is
|
* Board logic must provide the lpc31_usbsuspend logic if the USBDEV driver is
|
||||||
* used. This function is called whenever the USB enters or leaves suspend mode.
|
* used. This function is called whenever the USB enters or leaves suspend mode.
|
||||||
* This is an opportunity for the board logic to shutdown clocks, power, etc.
|
* This is an opportunity for the board logic to shutdown clocks, power, etc.
|
||||||
* while the USB is suspended.
|
* while the USB is suspended.
|
||||||
@@ -233,7 +233,7 @@ EXTERN int lpc313x_usbpullup(FAR struct usbdev_s *dev, bool enable);
|
|||||||
************************************************************************************/
|
************************************************************************************/
|
||||||
|
|
||||||
struct usbdev_s;
|
struct usbdev_s;
|
||||||
EXTERN void lpc313x_usbsuspend(FAR struct usbdev_s *dev, bool resume);
|
EXTERN void lpc31_usbsuspend(FAR struct usbdev_s *dev, bool resume);
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: sdio_initialize
|
* Name: sdio_initialize
|
||||||
@@ -297,4 +297,4 @@ EXTERN void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect);
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif /* __ASSEMBLY__ */
|
#endif /* __ASSEMBLY__ */
|
||||||
#endif /* __ARCH_ARM_SRC_LPC313X_LPC313X_INTERNAL_H */
|
#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_INTERNAL_H */
|
||||||
Executable
+357
@@ -0,0 +1,357 @@
|
|||||||
|
/************************************************************************************************
|
||||||
|
* arch/arm/src/lpc31xx/lpc31_ioconfig.h
|
||||||
|
*
|
||||||
|
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
||||||
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||||
|
* used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||||
|
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||||
|
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_IOCONFIG_H
|
||||||
|
#define __ARCH_ARM_SRC_LPC31XX_LPC31_IOCONFIG_H
|
||||||
|
|
||||||
|
/************************************************************************************************
|
||||||
|
* Included Files
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
#include <nuttx/config.h>
|
||||||
|
#include "lpc31_memorymap.h"
|
||||||
|
|
||||||
|
/************************************************************************************************
|
||||||
|
* Pre-processor Definitions
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
/* IOCONFIG register base address offset into the APB0 domain ***********************************/
|
||||||
|
|
||||||
|
#define LPC31_IOCONFIG_VBASE (LPC31_APB0_VADDR+LPC31_APB0_IOCONFIG_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_PBASE (LPC31_APB0_PADDR+LPC31_APB0_IOCONFIG_OFFSET)
|
||||||
|
|
||||||
|
/* IOCONFIG function block offsets (with respect to the IOCONFIG register base address) *********/
|
||||||
|
|
||||||
|
#define LPC31_IOCONFIG_EBIMCI_OFFSET 0x000 /* First set of 32 multiplexed pads */
|
||||||
|
#define LPC31_IOCONFIG_EBII2STX0_OFFSET 0X040 /* Second set of 32 of multiplexed pads */
|
||||||
|
#define LPC31_IOCONFIG_CGU_OFFSET 0X080 /* Clock Generation Unit function block */
|
||||||
|
#define LPC31_IOCONFIG_I2SRX0_OFFSET 0x0c0 /* I2SRX function block 0 */
|
||||||
|
#define LPC31_IOCONFIG_I2SRX1_OFFSET 0x100 /* I2SRX function block 1 */
|
||||||
|
#define LPC31_IOCONFIG_I2STX1_OFFSET 0x140 /* I2STX function block 1 */
|
||||||
|
#define LPC31_IOCONFIG_EBI_OFFSET 0x180 /* External Bus Interface function block */
|
||||||
|
#define LPC31_IOCONFIG_GPIO_OFFSET 0x1c0 /* General purpose IO */
|
||||||
|
#define LPC31_IOCONFIG_I2C1_OFFSET 0x200 /* I2C function block */
|
||||||
|
#define LPC31_IOCONFIG_SPI_OFFSET 0x240 /* SPI function block */
|
||||||
|
#define LPC31_IOCONFIG_NAND_OFFSET 0x280 /* NANDFLASH function block */
|
||||||
|
#define LPC31_IOCONFIG_PWM_OFFSET 0x2c0 /* PWM function block */
|
||||||
|
#define LPC31_IOCONFIG_UART_OFFSET 0x300 /* UART function block */
|
||||||
|
|
||||||
|
/* IOCONFIG register offsets (with respect to any funcion block base address) *******************/
|
||||||
|
|
||||||
|
#define LPC31_IOCONFIG_PINS_OFFSET 0x000 /* WR: RD: Input pin state */
|
||||||
|
/* 0x004-0x00c: Reserved */
|
||||||
|
#define LPC31_IOCONFIG_MODE0_OFFSET 0x010 /* WR:Load RD: */
|
||||||
|
#define LPC31_IOCONFIG_MODE0SET_OFFSET 0x014 /* WR:Set Bits RD:Read Mode 0 */
|
||||||
|
#define LPC31_IOCONFIG_MODE0RESET_OFFSET 0x018 /* WR:Reset Bits RD: */
|
||||||
|
/* 0x01c: Reserved */
|
||||||
|
#define LPC31_IOCONFIG_MODE1_OFFSET 0x020 /* WR:Load RD: */
|
||||||
|
#define LPC31_IOCONFIG_MODE1SET_OFFSET 0x024 /* WR:Set Bits RD:Read Mode 1 */
|
||||||
|
#define LPC31_IOCONFIG_MODE1RESET_OFFSET 0x028 /* WR:Reset Bits RD: */
|
||||||
|
/* 0x02c-0x3c: Reserved */
|
||||||
|
|
||||||
|
/* IOCONFIG function block (virtual) base addresses *********************************************/
|
||||||
|
|
||||||
|
#define LPC31_IOCONFIG_EBIMCI (LPC31_IOCONFIG_VBASE+LPC31_IOCONFIG_EBIMCI_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_EBII2STX0 (LPC31_IOCONFIG_VBASE+LPC31_IOCONFIG_EBII2STX0_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_CGU (LPC31_IOCONFIG_VBASE+LPC31_IOCONFIG_CGU_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2SRX0 (LPC31_IOCONFIG_VBASE+LPC31_IOCONFIG_I2SRX0_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2SRX1 (LPC31_IOCONFIG_VBASE+LPC31_IOCONFIG_I2SRX1_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2STX1 (LPC31_IOCONFIG_VBASE+LPC31_IOCONFIG_I2STX1_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_EBI (LPC31_IOCONFIG_VBASE+LPC31_IOCONFIG_EBI_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_GPIO (LPC31_IOCONFIG_VBASE+LPC31_IOCONFIG_GPIO_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2C1 (LPC31_IOCONFIG_VBASE+LPC31_IOCONFIG_I2C1_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_SPI (LPC31_IOCONFIG_VBASE+LPC31_IOCONFIG_SPI_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_NAND (LPC31_IOCONFIG_VBASE+LPC31_IOCONFIG_NAND_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_PWM (LPC31_IOCONFIG_VBASE+LPC31_IOCONFIG_PWM_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_UART (LPC31_IOCONFIG_VBASE+LPC31_IOCONFIG_UART_OFFSET)
|
||||||
|
|
||||||
|
/* IOCONFIG register (virtual) addresses ********************************************************/
|
||||||
|
|
||||||
|
#define LPC31_IOCONFIG_EBIMCI_PINS (LPC31_IOCONFIG_EBIMCI+LPC31_IOCONFIG_PINS_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_EBIMCI_MODE0 (LPC31_IOCONFIG_EBIMCI+LPC31_IOCONFIG_MODE0_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_EBIMCI_MODE0SET (LPC31_IOCONFIG_EBIMCI+LPC31_IOCONFIG_MODE0SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_EBIMCI_MODE0RESET (LPC31_IOCONFIG_EBIMCI+LPC31_IOCONFIG_MODE0RESET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_EBIMCI_MODE1 (LPC31_IOCONFIG_EBIMCI+LPC31_IOCONFIG_MODE1_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_EBIMCI_MODE1SET (LPC31_IOCONFIG_EBIMCI+LPC31_IOCONFIG_MODE1SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_EBIMCI_MODE1RESET (LPC31_IOCONFIG_EBIMCI+LPC31_IOCONFIG_MODE1RESET_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_IOCONFIG_EBII2STX0_PINS (LPC31_IOCONFIG_EBII2STX0+LPC31_IOCONFIG_PINS_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_EBII2STX0_MODE0 (LPC31_IOCONFIG_EBII2STX0+LPC31_IOCONFIG_MODE0_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_EBII2STX0_MODE0SET (LPC31_IOCONFIG_EBII2STX0+LPC31_IOCONFIG_MODE0SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_EBII2STX0_MODE0RESET (LPC31_IOCONFIG_EBII2STX0+LPC31_IOCONFIG_MODE0RESET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_EBII2STX0_MODE1 (LPC31_IOCONFIG_EBII2STX0+LPC31_IOCONFIG_MODE1_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_EBII2STX0_MODE1SET (LPC31_IOCONFIG_EBII2STX0+LPC31_IOCONFIG_MODE1SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_EBII2STX0_MODE1RESET (LPC31_IOCONFIG_EBII2STX0+LPC31_IOCONFIG_MODE1RESET_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_IOCONFIG_CGU_PINS (LPC31_IOCONFIG_CGU+LPC31_IOCONFIG_PINS_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_CGU_MODE0 (LPC31_IOCONFIG_CGU+LPC31_IOCONFIG_MODE0_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_CGU_MODE0SET (LPC31_IOCONFIG_CGU+LPC31_IOCONFIG_MODE0SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_CGU_MODE0RESET (LPC31_IOCONFIG_CGU+LPC31_IOCONFIG_MODE0RESET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_CGU_MODE1 (LPC31_IOCONFIG_CGU+LPC31_IOCONFIG_MODE1_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_CGU_MODE1SET (LPC31_IOCONFIG_CGU+LPC31_IOCONFIG_MODE1SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_CGU_MODE1RESET (LPC31_IOCONFIG_CGU+LPC31_IOCONFIG_MODE1RESET_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_IOCONFIG_I2SRX0_PINS (LPC31_IOCONFIG_I2SRX0+LPC31_IOCONFIG_PINS_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2SRX0_MODE0 (LPC31_IOCONFIG_I2SRX0+LPC31_IOCONFIG_MODE0_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2SRX0_MODE0SET (LPC31_IOCONFIG_I2SRX0+LPC31_IOCONFIG_MODE0SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2SRX0_MODE0RESET (LPC31_IOCONFIG_I2SRX0+LPC31_IOCONFIG_MODE0RESET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2SRX0_MODE1 (LPC31_IOCONFIG_I2SRX0+LPC31_IOCONFIG_MODE1_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2SRX0_MODE1SET (LPC31_IOCONFIG_I2SRX0+LPC31_IOCONFIG_MODE1SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2SRX0_MODE1RESET (LPC31_IOCONFIG_I2SRX0+LPC31_IOCONFIG_MODE1RESET_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_IOCONFIG_I2SRX1_PINS (LPC31_IOCONFIG_I2SRX1+LPC31_IOCONFIG_PINS_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2SRX1_MODE0 (LPC31_IOCONFIG_I2SRX1+LPC31_IOCONFIG_MODE0_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2SRX1_MODE0SET (LPC31_IOCONFIG_I2SRX1+LPC31_IOCONFIG_MODE0SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2SRX1_MODE0RESET (LPC31_IOCONFIG_I2SRX1+LPC31_IOCONFIG_MODE0RESET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2SRX1_MODE1 (LPC31_IOCONFIG_I2SRX1+LPC31_IOCONFIG_MODE1_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2SRX1_MODE1SET (LPC31_IOCONFIG_I2SRX1+LPC31_IOCONFIG_MODE1SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2SRX1_MODE1RESET (LPC31_IOCONFIG_I2SRX1+LPC31_IOCONFIG_MODE1RESET_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_IOCONFIG_I2STX1_PINS (LPC31_IOCONFIG_I2STX1+LPC31_IOCONFIG_PINS_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2STX1_MODE0 (LPC31_IOCONFIG_I2STX1+LPC31_IOCONFIG_MODE0_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2STX1_MODE0SET (LPC31_IOCONFIG_I2STX1+LPC31_IOCONFIG_MODE0SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2STX1_MODE0RESET (LPC31_IOCONFIG_I2STX1+LPC31_IOCONFIG_MODE0RESET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2STX1_MODE1 (LPC31_IOCONFIG_I2STX1+LPC31_IOCONFIG_MODE1_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2STX1_MODE1SET (LPC31_IOCONFIG_I2STX1+LPC31_IOCONFIG_MODE1SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2STX1_MODE1RESET (LPC31_IOCONFIG_I2STX1+LPC31_IOCONFIG_MODE1RESET_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_IOCONFIG_EBI_PINS (LPC31_IOCONFIG_EBI+LPC31_IOCONFIG_PINS_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_EBI_MODE0 (LPC31_IOCONFIG_EBI+LPC31_IOCONFIG_MODE0_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_EBI_MODE0SET (LPC31_IOCONFIG_EBI+LPC31_IOCONFIG_MODE0SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_EBI_MODE0RESET (LPC31_IOCONFIG_EBI+LPC31_IOCONFIG_MODE0RESET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_EBI_MODE1 (LPC31_IOCONFIG_EBI+LPC31_IOCONFIG_MODE1_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_EBI_MODE1SET (LPC31_IOCONFIG_EBI+LPC31_IOCONFIG_MODE1SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_EBI_MODE1RESET (LPC31_IOCONFIG_EBI+LPC31_IOCONFIG_MODE1RESET_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_IOCONFIG_GPIO_PINS (LPC31_IOCONFIG_GPIO+LPC31_IOCONFIG_PINS_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_GPIO_MODE0 (LPC31_IOCONFIG_GPIO+LPC31_IOCONFIG_MODE0_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_GPIO_MODE0SET (LPC31_IOCONFIG_GPIO+LPC31_IOCONFIG_MODE0SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_GPIO_MODE0RESET (LPC31_IOCONFIG_GPIO+LPC31_IOCONFIG_MODE0RESET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_GPIO_MODE1 (LPC31_IOCONFIG_GPIO+LPC31_IOCONFIG_MODE1_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_GPIO_MODE1SET (LPC31_IOCONFIG_GPIO+LPC31_IOCONFIG_MODE1SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_GPIO_MODE1RESET (LPC31_IOCONFIG_GPIO+LPC31_IOCONFIG_MODE1RESET_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_IOCONFIG_I2C1_PINS (LPC31_IOCONFIG_I2C1+LPC31_IOCONFIG_PINS_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2C1_MODE0 (LPC31_IOCONFIG_I2C1+LPC31_IOCONFIG_MODE0_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2C1_MODE0SET (LPC31_IOCONFIG_I2C1+LPC31_IOCONFIG_MODE0SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2C1_MODE0RESET (LPC31_IOCONFIG_I2C1+LPC31_IOCONFIG_MODE0RESET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2C1_MODE1 (LPC31_IOCONFIG_I2C1+LPC31_IOCONFIG_MODE1_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2C1_MODE1SET (LPC31_IOCONFIG_I2C1+LPC31_IOCONFIG_MODE1SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_I2C1_MODE1RESET (LPC31_IOCONFIG_I2C1+LPC31_IOCONFIG_MODE1RESET_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_IOCONFIG_SPI_PINS (LPC31_IOCONFIG_SPI+LPC31_IOCONFIG_PINS_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_SPI_MODE0 (LPC31_IOCONFIG_SPI+LPC31_IOCONFIG_MODE0_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_SPI_MODE0SET (LPC31_IOCONFIG_SPI+LPC31_IOCONFIG_MODE0SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_SPI_MODE0RESET (LPC31_IOCONFIG_SPI+LPC31_IOCONFIG_MODE0RESET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_SPI_MODE1 (LPC31_IOCONFIG_SPI+LPC31_IOCONFIG_MODE1_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_SPI_MODE1SET (LPC31_IOCONFIG_SPI+LPC31_IOCONFIG_MODE1SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_SPI_MODE1RESET (LPC31_IOCONFIG_SPI+LPC31_IOCONFIG_MODE1RESET_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_IOCONFIG_NAND_PINS (LPC31_IOCONFIG_NAND+LPC31_IOCONFIG_PINS_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_NAND_MODE0 (LPC31_IOCONFIG_NAND+LPC31_IOCONFIG_MODE0_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_NAND_MODE0SET (LPC31_IOCONFIG_NAND+LPC31_IOCONFIG_MODE0SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_NAND_MODE0RESET (LPC31_IOCONFIG_NAND+LPC31_IOCONFIG_MODE0RESET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_NAND_MODE1 (LPC31_IOCONFIG_NAND+LPC31_IOCONFIG_MODE1_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_NAND_MODE1SET (LPC31_IOCONFIG_NAND+LPC31_IOCONFIG_MODE1SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_NAND_MODE1RESET (LPC31_IOCONFIG_NAND+LPC31_IOCONFIG_MODE1RESET_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_IOCONFIG_PWM_PINS (LPC31_IOCONFIG_PWM+LPC31_IOCONFIG_PINS_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_PWM_MODE0 (LPC31_IOCONFIG_PWM+LPC31_IOCONFIG_MODE0_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_PWM_MODE0SET (LPC31_IOCONFIG_PWM+LPC31_IOCONFIG_MODE0SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_PWM_MODE0RESET (LPC31_IOCONFIG_PWM+LPC31_IOCONFIG_MODE0RESET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_PWM_MODE1 (LPC31_IOCONFIG_PWM+LPC31_IOCONFIG_MODE1_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_PWM_MODE1SET (LPC31_IOCONFIG_PWM+LPC31_IOCONFIG_MODE1SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_PWM_MODE1RESET (LPC31_IOCONFIG_PWM+LPC31_IOCONFIG_MODE1RESET_OFFSET)
|
||||||
|
|
||||||
|
#define LPC31_IOCONFIG_UART_PINS (LPC31_IOCONFIG_UART+LPC31_IOCONFIG_PINS_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_UART_MODE0 (LPC31_IOCONFIG_UART+LPC31_IOCONFIG_MODE0_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_UART_MODE0SET (LPC31_IOCONFIG_UART+LPC31_IOCONFIG_MODE0SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_UART_MODE0RESET (LPC31_IOCONFIG_UART+LPC31_IOCONFIG_MODE0RESET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_UART_MODE1 (LPC31_IOCONFIG_UART+LPC31_IOCONFIG_MODE1_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_UART_MODE1SET (LPC31_IOCONFIG_UART+LPC31_IOCONFIG_MODE1SET_OFFSET)
|
||||||
|
#define LPC31_IOCONFIG_UART_MODE1RESET (LPC31_IOCONFIG_UART+LPC31_IOCONFIG_MODE1RESET_OFFSET)
|
||||||
|
|
||||||
|
/* IOCONFIG register bit definitions ************************************************************/
|
||||||
|
/* EBI_MCI register bit definitions (all registers) */
|
||||||
|
|
||||||
|
|
||||||
|
#define IOCONFIG_EBIMCI_MGPIO9 (1 << 0)
|
||||||
|
#define IOCONFIG_EBIMCI_MGPIO6 (1 << 1)
|
||||||
|
#define IOCONFIG_EBIMCI_MLCDDB7 (1 << 2)
|
||||||
|
#define IOCONFIG_EBIMCI_MLCDDB4 (1 << 3)
|
||||||
|
#define IOCONFIG_EBIMCI_MLCDDB2 (1 << 4)
|
||||||
|
#define IOCONFIG_EBIMCI_MNANDRYBN0 (1 << 5)
|
||||||
|
#define IOCONFIG_EBIMCI_MI2STXCLK0 (1 << 6)
|
||||||
|
#define IOCONFIG_EBIMCI_MI2STXBCK0 (1 << 7)
|
||||||
|
#define IOCONFIG_EBIMCI_EBIA1CLE (1 << 8)
|
||||||
|
#define IOCONFIG_EBIMCI_EBINCASBLOUT0 (1 << 9)
|
||||||
|
#define IOCONFIG_EBIMCI_MLCDDB0 (1 << 10)
|
||||||
|
#define IOCONFIG_EBIMCI_EBIDQM0NOE (1 << 11)
|
||||||
|
#define IOCONFIG_EBIMCI_MLCDCSB (1 << 12)
|
||||||
|
#define IOCONFIG_EBIMCI_MLCDDB1 (1 << 13)
|
||||||
|
#define IOCONFIG_EBIMCI_MLCDERD (1 << 14)
|
||||||
|
#define IOCONFIG_EBIMCI_MLCDRS (1 << 15)
|
||||||
|
#define IOCONFIG_EBIMCI_MLCDRWWR (1 << 16)
|
||||||
|
#define IOCONFIG_EBIMCI_MLCDDB3 (1 << 17)
|
||||||
|
#define IOCONFIG_EBIMCI_MLCDDB5 (1 << 18)
|
||||||
|
#define IOCONFIG_EBIMCI_MLCDDB6 (1 << 19)
|
||||||
|
#define IOCONFIG_EBIMCI_MLCDDB8 (1 << 20)
|
||||||
|
#define IOCONFIG_EBIMCI_MLCDDB9 (1 << 21)
|
||||||
|
#define IOCONFIG_EBIMCI_MLCDDB10 (1 << 22)
|
||||||
|
#define IOCONFIG_EBIMCI_MLCDDB11 (1 << 23)
|
||||||
|
#define IOCONFIG_EBIMCI_MLCDDB12 (1 << 24)
|
||||||
|
#define IOCONFIG_EBIMCI_MLCDDB13 (1 << 25)
|
||||||
|
#define IOCONFIG_EBIMCI_MLCDDB14 (1 << 26)
|
||||||
|
#define IOCONFIG_EBIMCI_MLCDDB15 (1 << 27)
|
||||||
|
#define IOCONFIG_EBIMCI_MGPIO5 (1 << 28)
|
||||||
|
#define IOCONFIG_EBIMCI_MGPIO7 (1 << 29)
|
||||||
|
#define IOCONFIG_EBIMCI_MGPIO8 (1 << 30)
|
||||||
|
#define IOCONFIG_EBIMCI_MGPIO10 (1 << 31)
|
||||||
|
|
||||||
|
/* EBI_I2STX_0 register bit definitions (all registers) */
|
||||||
|
|
||||||
|
#define IOCONFIG_EBII2STX0_MNANDRYBN1 (1 << 0)
|
||||||
|
#define IOCONFIG_EBII2STX0_MNANDRYBN2 (1 << 1)
|
||||||
|
#define IOCONFIG_EBII2STX0_MNANDRYBN3 (1 << 2)
|
||||||
|
#define IOCONFIG_EBII2STX0_MUARTCTSN (1 << 3)
|
||||||
|
#define IOCONFIG_EBII2STX0_MUARTRTSN (1 << 4)
|
||||||
|
#define IOCONFIG_EBII2STX0_MI2STXDATA0 (1 << 5)
|
||||||
|
#define IOCONFIG_EBII2STX0_MI2STXWS0 (1 << 6)
|
||||||
|
#define IOCONFIG_EBII2STX0_EBINRASBLOUT1 (1 << 7)
|
||||||
|
#define IOCONFIG_EBII2STX0_EBIA0ALE (1 << 8)
|
||||||
|
#define IOCONFIG_EBII2STX0_EBINWE (1 << 9)
|
||||||
|
|
||||||
|
/* CGU register bit definitions (all registers) */
|
||||||
|
|
||||||
|
#define IOCONFIG_CGU_SYSCLKO (1 << 0)
|
||||||
|
|
||||||
|
/* I2SRX_0 register bit definitions (all registers) */
|
||||||
|
|
||||||
|
#define IOCONFIG_I2SRX0_BCK (1 << 0)
|
||||||
|
#define IOCONFIG_I2SRX0_DATA (1 << 1)
|
||||||
|
#define IOCONFIG_I2SRX0_WS (1 << 2)
|
||||||
|
|
||||||
|
/* I2SRX_1 register bit definitions (all registers) */
|
||||||
|
|
||||||
|
#define IOCONFIG_I2SRX1_DATA (1 << 0)
|
||||||
|
#define IOCONFIG_I2SRX1_BCK (1 << 1)
|
||||||
|
#define IOCONFIG_I2SRX1_WS (1 << 2)
|
||||||
|
|
||||||
|
/* I2STX_1 register bit definitions (all registers) */
|
||||||
|
|
||||||
|
#define IOCONFIG_I2STX1_DATA (1 << 0)
|
||||||
|
#define IOCONFIG_I2STX1_BCK (1 << 1)
|
||||||
|
#define IOCONFIG_I2STX1_WS (1 << 2)
|
||||||
|
#define IOCONFIG_I2STX1_256FSO (1 << 3)
|
||||||
|
|
||||||
|
/* EBI register bit definitions (all registers) */
|
||||||
|
|
||||||
|
#define IOCONFIG_EBI_D9 (1 << 0)
|
||||||
|
#define IOCONFIG_EBI_D10 (1 << 1)
|
||||||
|
#define IOCONFIG_EBI_D11 (1 << 2)
|
||||||
|
#define IOCONFIG_EBI_D12 (1 << 3)
|
||||||
|
#define IOCONFIG_EBI_D13 (1 << 4)
|
||||||
|
#define IOCONFIG_EBI_D14 (1 << 5)
|
||||||
|
#define IOCONFIG_EBI_D4 (1 << 6)
|
||||||
|
#define IOCONFIG_EBI_D0 (1 << 7)
|
||||||
|
#define IOCONFIG_EBI_D1 (1 << 8)
|
||||||
|
#define IOCONFIG_EBI_D2 (1 << 9)
|
||||||
|
#define IOCONFIG_EBI_D3 (1 << 10)
|
||||||
|
#define IOCONFIG_EBI_D5 (1 << 11)
|
||||||
|
#define IOCONFIG_EBI_D6 (1 << 12)
|
||||||
|
#define IOCONFIG_EBI_D7 (1 << 13)
|
||||||
|
#define IOCONFIG_EBI_D8 (1 << 14)
|
||||||
|
#define IOCONFIG_EBI_D15 (1 << 15)
|
||||||
|
|
||||||
|
/* GPIO register bit definitions (all registers) */
|
||||||
|
|
||||||
|
#define IOCONFIG_GPIO_GPIO1 (1 << 0)
|
||||||
|
#define IOCONFIG_GPIO_GPIO0 (1 << 1)
|
||||||
|
#define IOCONFIG_GPIO_GPIO2 (1 << 2)
|
||||||
|
#define IOCONFIG_GPIO_GPIO3 (1 << 3)
|
||||||
|
#define IOCONFIG_GPIO_GPIO4 (1 << 4)
|
||||||
|
#define IOCONFIG_GPIO_GPIO11 (1 << 5)
|
||||||
|
#define IOCONFIG_GPIO_GPIO12 (1 << 6)
|
||||||
|
#define IOCONFIG_GPIO_GPIO13 (1 << 7)
|
||||||
|
#define IOCONFIG_GPIO_GPIO14 (1 << 8)
|
||||||
|
#define IOCONFIG_GPIO_GPIO15 (1 << 9)
|
||||||
|
#define IOCONFIG_GPIO_GPIO16 (1 << 10)
|
||||||
|
#define IOCONFIG_GPIO_GPIO17 (1 << 11)
|
||||||
|
#define IOCONFIG_GPIO_GPIO18 (1 << 12)
|
||||||
|
#define IOCONFIG_GPIO_GPIO19 (1 << 13)
|
||||||
|
#define IOCONFIG_GPIO_GPIO20 (1 << 14)
|
||||||
|
|
||||||
|
/* I2C1 register bit definitions (all registers) */
|
||||||
|
|
||||||
|
#define IOCONFIG_I2C1_SDA1 (1 << 0)
|
||||||
|
#define IOCONFIG_I2C1_SCL1 (1 << 1)
|
||||||
|
|
||||||
|
/* SPI register bit definitions (all registers) */
|
||||||
|
|
||||||
|
#define IOCONFIG_SPI_MISO (1 << 0)
|
||||||
|
#define IOCONFIG_SPI_MOSI (1 << 1)
|
||||||
|
#define IOCONFIG_SPI_CSIN (1 << 2)
|
||||||
|
#define IOCONFIG_SPI_SCK (1 << 3)
|
||||||
|
#define IOCONFIG_SPI_CSOUT0 (1 << 4)
|
||||||
|
|
||||||
|
/* NAND register bit definitions (all registers) */
|
||||||
|
|
||||||
|
#define IOCONFIG_NAND_NCS3 (1 << 0)
|
||||||
|
#define IOCONFIG_NAND_NCS0 (1 << 1)
|
||||||
|
#define IOCONFIG_NAND_NCS1 (1 << 2)
|
||||||
|
#define IOCONFIG_NAND_NCS2 (1 << 3)
|
||||||
|
|
||||||
|
/* PWM register bit definitions (all registers) */
|
||||||
|
|
||||||
|
#define IOCONFIG_PWM_DATA (1 << 0)
|
||||||
|
|
||||||
|
/* UART register bit definitions (all registers) */
|
||||||
|
|
||||||
|
#define IOCONFIG_UART_RXD (1 << 0)
|
||||||
|
#define IOCONFIG_UART_TXD (1 << 1)
|
||||||
|
|
||||||
|
/************************************************************************************************
|
||||||
|
* Public Types
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
/************************************************************************************************
|
||||||
|
* Public Data
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
/************************************************************************************************
|
||||||
|
* Public Functions
|
||||||
|
************************************************************************************************/
|
||||||
|
|
||||||
|
#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_IOCONFIG_H */
|
||||||
@@ -1,6 +1,6 @@
|
|||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_irq.c
|
* arch/arm/src/lpc31xx/lpc31_irq.c
|
||||||
* arch/arm/src/chip/lpc313x_irq.c
|
* arch/arm/src/chip/lpc31_irq.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -52,9 +52,9 @@
|
|||||||
#include "os_internal.h"
|
#include "os_internal.h"
|
||||||
#include "up_internal.h"
|
#include "up_internal.h"
|
||||||
|
|
||||||
#include "lpc313x_intc.h"
|
#include "lpc31_intc.h"
|
||||||
#include "lpc313x_cgudrvr.h"
|
#include "lpc31_cgudrvr.h"
|
||||||
#include "lpc313x_internal.h"
|
#include "lpc31_internal.h"
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Definitions
|
* Definitions
|
||||||
@@ -88,20 +88,20 @@ void up_irqinitialize(void)
|
|||||||
|
|
||||||
/* Enable clock to interrupt controller */
|
/* Enable clock to interrupt controller */
|
||||||
|
|
||||||
lpc313x_enableclock(CLKID_AHB2INTCCLK); /* AHB_TO_INTC_CLK */
|
lpc31_enableclock(CLKID_AHB2INTCCLK); /* AHB_TO_INTC_CLK */
|
||||||
lpc313x_enableclock(CLKID_INTCCLK); /* INTC_CLK */
|
lpc31_enableclock(CLKID_INTCCLK); /* INTC_CLK */
|
||||||
|
|
||||||
/* Set the vector base. We don't use direct vectoring, so these are set to 0. */
|
/* Set the vector base. We don't use direct vectoring, so these are set to 0. */
|
||||||
|
|
||||||
putreg32(0, LPC313X_INTC_VECTOR0);
|
putreg32(0, LPC31_INTC_VECTOR0);
|
||||||
putreg32(0, LPC313X_INTC_VECTOR1);
|
putreg32(0, LPC31_INTC_VECTOR1);
|
||||||
|
|
||||||
/* Set the priority treshold to 0, i.e. don't mask any interrupt on the
|
/* Set the priority treshold to 0, i.e. don't mask any interrupt on the
|
||||||
* basis of priority level, for both targets (IRQ/FIQ)
|
* basis of priority level, for both targets (IRQ/FIQ)
|
||||||
*/
|
*/
|
||||||
|
|
||||||
putreg32(0, LPC313X_INTC_PRIORITYMASK0); /* Proc interrupt request 0: IRQ */
|
putreg32(0, LPC31_INTC_PRIORITYMASK0); /* Proc interrupt request 0: IRQ */
|
||||||
putreg32(0, LPC313X_INTC_PRIORITYMASK1); /* Proc interrupt request 1: FIQ */
|
putreg32(0, LPC31_INTC_PRIORITYMASK1); /* Proc interrupt request 1: FIQ */
|
||||||
|
|
||||||
/* Disable all interrupts. Start from index 1 since 0 is unused.*/
|
/* Disable all interrupts. Start from index 1 since 0 is unused.*/
|
||||||
|
|
||||||
@@ -111,7 +111,7 @@ void up_irqinitialize(void)
|
|||||||
* Set priority level to 1 (= lowest) for all the interrupt lines
|
* Set priority level to 1 (= lowest) for all the interrupt lines
|
||||||
*/
|
*/
|
||||||
|
|
||||||
uint32_t address = LPC313X_INTC_REQUEST(irq+1);
|
uint32_t address = LPC31_INTC_REQUEST(irq+1);
|
||||||
putreg32(INTC_REQUEST_WEACTLOW|INTC_REQUEST_WEENABLE|INTC_REQUEST_TARGET_IRQ|
|
putreg32(INTC_REQUEST_WEACTLOW|INTC_REQUEST_WEENABLE|INTC_REQUEST_TARGET_IRQ|
|
||||||
INTC_REQUEST_PRIOLEVEL(1)|INTC_REQUEST_WEPRIO, address);
|
INTC_REQUEST_PRIOLEVEL(1)|INTC_REQUEST_WEPRIO, address);
|
||||||
|
|
||||||
@@ -142,7 +142,7 @@ void up_disable_irq(int irq)
|
|||||||
* interrupt source
|
* interrupt source
|
||||||
*/
|
*/
|
||||||
|
|
||||||
uint32_t address = LPC313X_INTC_REQUEST(irq+1);
|
uint32_t address = LPC31_INTC_REQUEST(irq+1);
|
||||||
|
|
||||||
/* Clear the ENABLE bit with WE_ENABLE=1. Configuration settings will be
|
/* Clear the ENABLE bit with WE_ENABLE=1. Configuration settings will be
|
||||||
* preserved because WE_TARGET is zero.
|
* preserved because WE_TARGET is zero.
|
||||||
@@ -165,7 +165,7 @@ void up_enable_irq(int irq)
|
|||||||
* interrupt source
|
* interrupt source
|
||||||
*/
|
*/
|
||||||
|
|
||||||
uint32_t address = LPC313X_INTC_REQUEST(irq+1);
|
uint32_t address = LPC31_INTC_REQUEST(irq+1);
|
||||||
|
|
||||||
/* Set the ENABLE bit with WE_ENABLE=1. Configuration settings will be
|
/* Set the ENABLE bit with WE_ENABLE=1. Configuration settings will be
|
||||||
* preserved because WE_TARGET is zero.
|
* preserved because WE_TARGET is zero.
|
||||||
@@ -188,7 +188,7 @@ void up_maskack_irq(int irq)
|
|||||||
* interrupt source
|
* interrupt source
|
||||||
*/
|
*/
|
||||||
|
|
||||||
uint32_t address = LPC313X_INTC_REQUEST(irq+1);
|
uint32_t address = LPC31_INTC_REQUEST(irq+1);
|
||||||
|
|
||||||
/* Clear the pending interrupt (INTC_REQUEST_CLRSWINT=1) AND disable interrupts
|
/* Clear the pending interrupt (INTC_REQUEST_CLRSWINT=1) AND disable interrupts
|
||||||
* (ENABLE=0 && WE_ENABLE=1). Configuration settings will be preserved because
|
* (ENABLE=0 && WE_ENABLE=1). Configuration settings will be preserved because
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_lcd.h
|
* arch/arm/src/lpc31xx/lpc31_lcd.h
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -33,15 +33,15 @@
|
|||||||
*
|
*
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#ifndef __ARCH_ARM_SRC_LPC313X_LCD_H
|
#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_LCD_H
|
||||||
#define __ARCH_ARM_SRC_LPC313X_LCD_H
|
#define __ARCH_ARM_SRC_LPC31XX_LPC31_LCD_H
|
||||||
|
|
||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* Included Files
|
* Included Files
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#include <nuttx/config.h>
|
#include <nuttx/config.h>
|
||||||
#include "lpc313x_memorymap.h"
|
#include "lpc31_memorymap.h"
|
||||||
|
|
||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -49,34 +49,34 @@
|
|||||||
|
|
||||||
/* LCD register base address offset into the APB2 domain ****************************************/
|
/* LCD register base address offset into the APB2 domain ****************************************/
|
||||||
|
|
||||||
#define LPC313X_LCD_VBASE (LPC313X_APB2_VSECTION+LPC313X_APB2_LCD_OFFSET)
|
#define LPC31_LCD_VBASE (LPC31_APB2_VSECTION+LPC31_APB2_LCD_OFFSET)
|
||||||
#define LPC313X_LCD_PBASE (LPC313X_APB2_PSECTION+LPC313X_APB2_LCD_OFFSET)
|
#define LPC31_LCD_PBASE (LPC31_APB2_PSECTION+LPC31_APB2_LCD_OFFSET)
|
||||||
|
|
||||||
/* LCD register offsets (with respect to the LCD base) ******************************************/
|
/* LCD register offsets (with respect to the LCD base) ******************************************/
|
||||||
|
|
||||||
#define LPC313X_LCD_STATUS_OFFSET 0x000 /* Status register */
|
#define LPC31_LCD_STATUS_OFFSET 0x000 /* Status register */
|
||||||
#define LPC313X_LCD_CONTROL_OFFSET 0x004 /* Control register */
|
#define LPC31_LCD_CONTROL_OFFSET 0x004 /* Control register */
|
||||||
#define LPC313X_LCD_INTRAW_OFFSET 0x008 /* Interrupt Raw register */
|
#define LPC31_LCD_INTRAW_OFFSET 0x008 /* Interrupt Raw register */
|
||||||
#define LPC313X_LCD_INTCLEAR_OFFSET 0x00c /* Interrupt Clear register */
|
#define LPC31_LCD_INTCLEAR_OFFSET 0x00c /* Interrupt Clear register */
|
||||||
#define LPC313X_LCD_INTMASK_OFFSET 0x010 /* Interrupt Mask Register */
|
#define LPC31_LCD_INTMASK_OFFSET 0x010 /* Interrupt Mask Register */
|
||||||
#define LPC313X_LCD_READCMD_OFFSET 0x014 /* Read Command register */
|
#define LPC31_LCD_READCMD_OFFSET 0x014 /* Read Command register */
|
||||||
#define LPC313X_LCD_INSTBYTE_OFFSET 0x020 /* Instruction Byte Register */
|
#define LPC31_LCD_INSTBYTE_OFFSET 0x020 /* Instruction Byte Register */
|
||||||
#define LPC313X_LCD_DATABYTE_OFFSET 0x030 /* Data Byte Register */
|
#define LPC31_LCD_DATABYTE_OFFSET 0x030 /* Data Byte Register */
|
||||||
#define LPC313X_LCD_INSTWORD_OFFSET 0x040 /* Instruction Word register */
|
#define LPC31_LCD_INSTWORD_OFFSET 0x040 /* Instruction Word register */
|
||||||
#define LPC313X_LCD_DATAWORD_OFFSET 0x080 /* Data Word register */
|
#define LPC31_LCD_DATAWORD_OFFSET 0x080 /* Data Word register */
|
||||||
|
|
||||||
/* LCD register (virtual) addresses *************************************************************/
|
/* LCD register (virtual) addresses *************************************************************/
|
||||||
|
|
||||||
#define LPC313X_LCD_STATUS (LPC313X_LCD_VBASE+LPC313X_LCD_STATUS_OFFSET)
|
#define LPC31_LCD_STATUS (LPC31_LCD_VBASE+LPC31_LCD_STATUS_OFFSET)
|
||||||
#define LPC313X_LCD_CONTROL (LPC313X_LCD_VBASE+LPC313X_LCD_CONTROL_OFFSET)
|
#define LPC31_LCD_CONTROL (LPC31_LCD_VBASE+LPC31_LCD_CONTROL_OFFSET)
|
||||||
#define LPC313X_LCD_INTRAW (LPC313X_LCD_VBASE+LPC313X_LCD_INTRAW_OFFSET)
|
#define LPC31_LCD_INTRAW (LPC31_LCD_VBASE+LPC31_LCD_INTRAW_OFFSET)
|
||||||
#define LPC313X_LCD_INTCLEAR (LPC313X_LCD_VBASE+LPC313X_LCD_INTCLEAR_OFFSET)
|
#define LPC31_LCD_INTCLEAR (LPC31_LCD_VBASE+LPC31_LCD_INTCLEAR_OFFSET)
|
||||||
#define LPC313X_LCD_INTMASK (LPC313X_LCD_VBASE+LPC313X_LCD_INTMASK_OFFSET)
|
#define LPC31_LCD_INTMASK (LPC31_LCD_VBASE+LPC31_LCD_INTMASK_OFFSET)
|
||||||
#define LPC313X_LCD_READCMD (LPC313X_LCD_VBASE+LPC313X_LCD_READCMD_OFFSET)
|
#define LPC31_LCD_READCMD (LPC31_LCD_VBASE+LPC31_LCD_READCMD_OFFSET)
|
||||||
#define LPC313X_LCD_INSTBYTE (LPC313X_LCD_VBASE+LPC313X_LCD_INSTBYTE_OFFSET)
|
#define LPC31_LCD_INSTBYTE (LPC31_LCD_VBASE+LPC31_LCD_INSTBYTE_OFFSET)
|
||||||
#define LPC313X_LCD_DATABYTE (LPC313X_LCD_VBASE+LPC313X_LCD_DATABYTE_OFFSET)
|
#define LPC31_LCD_DATABYTE (LPC31_LCD_VBASE+LPC31_LCD_DATABYTE_OFFSET)
|
||||||
#define LPC313X_LCD_INSTWORD (LPC313X_LCD_VBASE+LPC313X_LCD_INSTWORD_OFFSET)
|
#define LPC31_LCD_INSTWORD (LPC31_LCD_VBASE+LPC31_LCD_INSTWORD_OFFSET)
|
||||||
#define LPC313X_LCD_DATAWORD (LPC313X_LCD_VBASE+LPC313X_LCD_DATAWORD_OFFSET)
|
#define LPC31_LCD_DATAWORD (LPC31_LCD_VBASE+LPC31_LCD_DATAWORD_OFFSET)
|
||||||
|
|
||||||
/* LCD register bit definitions *****************************************************************/
|
/* LCD register bit definitions *****************************************************************/
|
||||||
/* LCD interface Status Register LCD_STATUS, address 0x15000400 */
|
/* LCD interface Status Register LCD_STATUS, address 0x15000400 */
|
||||||
@@ -158,4 +158,4 @@
|
|||||||
* Public Functions
|
* Public Functions
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#endif /* __ARCH_ARM_SRC_LPC313X_LCD_H */
|
#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_LCD_H */
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_lowputc.c
|
* arch/arm/src/lpc31xx/lpc31_lowputc.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -48,8 +48,8 @@
|
|||||||
#include "up_arch.h"
|
#include "up_arch.h"
|
||||||
#include "up_internal.h"
|
#include "up_internal.h"
|
||||||
|
|
||||||
#include "lpc313x_cgudrvr.h"
|
#include "lpc31_cgudrvr.h"
|
||||||
#include "lpc313x_uart.h"
|
#include "lpc31_uart.h"
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Definitions
|
* Definitions
|
||||||
@@ -59,7 +59,7 @@
|
|||||||
|
|
||||||
/* Is the UART enabled? */
|
/* Is the UART enabled? */
|
||||||
|
|
||||||
#ifdef CONFIG_LPC313X_UART
|
#ifdef CONFIG_LPC31_UART
|
||||||
# define HAVE_UART 1
|
# define HAVE_UART 1
|
||||||
|
|
||||||
/* Is it a serial console? */
|
/* Is it a serial console? */
|
||||||
@@ -71,7 +71,7 @@
|
|||||||
* initialization suppressed?
|
* initialization suppressed?
|
||||||
*/
|
*/
|
||||||
|
|
||||||
# if defined(CONFIG_USE_EARLYSERIALINIT) || defined(CONFIG_SUPPRESS_LPC313X_UART_CONFIG)
|
# if defined(CONFIG_USE_EARLYSERIALINIT) || defined(CONFIG_SUPPRESS_LPC31_UART_CONFIG)
|
||||||
# undef NEED_LOWSETUP
|
# undef NEED_LOWSETUP
|
||||||
# else
|
# else
|
||||||
# define NEED_LOWSETUP 1
|
# define NEED_LOWSETUP 1
|
||||||
@@ -114,7 +114,7 @@ static inline void up_waittxready(void)
|
|||||||
{
|
{
|
||||||
/* Check if the tranmitter holding register (THR) is empty */
|
/* Check if the tranmitter holding register (THR) is empty */
|
||||||
|
|
||||||
if ((getreg32(LPC313X_UART_LSR) & UART_LSR_THRE) != 0)
|
if ((getreg32(LPC31_UART_LSR) & UART_LSR_THRE) != 0)
|
||||||
{
|
{
|
||||||
/* The THR is empty, return */
|
/* The THR is empty, return */
|
||||||
|
|
||||||
@@ -137,7 +137,7 @@ static inline void up_configbaud(void)
|
|||||||
* file.
|
* file.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef CONFIG_LPC313X_UART_MULVAL
|
#ifndef CONFIG_LPC31_UART_MULVAL
|
||||||
uint32_t qtrclk;
|
uint32_t qtrclk;
|
||||||
uint32_t regval;
|
uint32_t regval;
|
||||||
|
|
||||||
@@ -170,7 +170,7 @@ static inline void up_configbaud(void)
|
|||||||
|
|
||||||
/* Get UART block clock divided by 16 */
|
/* Get UART block clock divided by 16 */
|
||||||
|
|
||||||
qtrclk = lpc313x_clkfreq(CLKID_UARTUCLK, DOMAINID_UART) >> 4;
|
qtrclk = lpc31_clkfreq(CLKID_UARTUCLK, DOMAINID_UART) >> 4;
|
||||||
|
|
||||||
/* Try every valid multiplier, tmulval (or until a perfect
|
/* Try every valid multiplier, tmulval (or until a perfect
|
||||||
* match is found).
|
* match is found).
|
||||||
@@ -223,43 +223,43 @@ static inline void up_configbaud(void)
|
|||||||
|
|
||||||
/* Set the Divisor Latch Access Bit (DLAB) to enable DLL/DLM access */
|
/* Set the Divisor Latch Access Bit (DLAB) to enable DLL/DLM access */
|
||||||
|
|
||||||
regval = getreg32(LPC313X_UART_LCR);
|
regval = getreg32(LPC31_UART_LCR);
|
||||||
regval |= UART_LCR_DLAB;
|
regval |= UART_LCR_DLAB;
|
||||||
putreg32(regval, LPC313X_UART_LCR);
|
putreg32(regval, LPC31_UART_LCR);
|
||||||
|
|
||||||
/* Configure the MS and LS DLAB registers */
|
/* Configure the MS and LS DLAB registers */
|
||||||
|
|
||||||
putreg32(div & UART_DLL_MASK, LPC313X_UART_DLL);
|
putreg32(div & UART_DLL_MASK, LPC31_UART_DLL);
|
||||||
putreg32((div >> 8) & UART_DLL_MASK, LPC313X_UART_DLM);
|
putreg32((div >> 8) & UART_DLL_MASK, LPC31_UART_DLM);
|
||||||
|
|
||||||
regval &= ~UART_LCR_DLAB;
|
regval &= ~UART_LCR_DLAB;
|
||||||
putreg32(regval, LPC313X_UART_LCR);
|
putreg32(regval, LPC31_UART_LCR);
|
||||||
|
|
||||||
/* Configure the Fractional Divider Register (FDR) */
|
/* Configure the Fractional Divider Register (FDR) */
|
||||||
|
|
||||||
putreg32((mulval << UART_FDR_MULVAL_SHIFT) |
|
putreg32((mulval << UART_FDR_MULVAL_SHIFT) |
|
||||||
(divaddval << UART_FDR_DIVADDVAL_SHIFT),
|
(divaddval << UART_FDR_DIVADDVAL_SHIFT),
|
||||||
LPC313X_UART_FDR);
|
LPC31_UART_FDR);
|
||||||
#else
|
#else
|
||||||
/* Set the Divisor Latch Access Bit (DLAB) to enable DLL/DLM access */
|
/* Set the Divisor Latch Access Bit (DLAB) to enable DLL/DLM access */
|
||||||
|
|
||||||
regval = getreg32(LPC313X_UART_LCR);
|
regval = getreg32(LPC31_UART_LCR);
|
||||||
regval |= UART_LCR_DLAB;
|
regval |= UART_LCR_DLAB;
|
||||||
putreg32(regval, LPC313X_UART_LCR);
|
putreg32(regval, LPC31_UART_LCR);
|
||||||
|
|
||||||
/* Configure the MS and LS DLAB registers */
|
/* Configure the MS and LS DLAB registers */
|
||||||
|
|
||||||
putreg32(CONFIG_LPC313X_UART_DIVISOR & UART_DLL_MASK, LPC313X_UART_DLL);
|
putreg32(CONFIG_LPC31_UART_DIVISOR & UART_DLL_MASK, LPC31_UART_DLL);
|
||||||
putreg32((CONFIG_LPC313X_UART_DIVISOR >> 8) & UART_DLL_MASK, LPC313X_UART_DLM);
|
putreg32((CONFIG_LPC31_UART_DIVISOR >> 8) & UART_DLL_MASK, LPC31_UART_DLM);
|
||||||
|
|
||||||
regval &= ~UART_LCR_DLAB;
|
regval &= ~UART_LCR_DLAB;
|
||||||
putreg32(regval, LPC313X_UART_LCR);
|
putreg32(regval, LPC31_UART_LCR);
|
||||||
|
|
||||||
/* Configure the Fractional Divider Register (FDR) */
|
/* Configure the Fractional Divider Register (FDR) */
|
||||||
|
|
||||||
putreg32((CONFIG_LPC313X_UART_MULVAL << UART_FDR_MULVAL_SHIFT) |
|
putreg32((CONFIG_LPC31_UART_MULVAL << UART_FDR_MULVAL_SHIFT) |
|
||||||
(CONFIG_LPC313X_UART_DIVADDVAL << UART_FDR_DIVADDVAL_SHIFT),
|
(CONFIG_LPC31_UART_DIVADDVAL << UART_FDR_DIVADDVAL_SHIFT),
|
||||||
LPC313X_UART_FDR);
|
LPC31_UART_FDR);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
@@ -268,30 +268,30 @@ static inline void up_configbaud(void)
|
|||||||
* Public Functions
|
* Public Functions
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: lpc313x_lowsetup
|
* Name: lpc31_lowsetup
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Called early in up_boot. Performs chip-common low level initialization.
|
* Called early in up_boot. Performs chip-common low level initialization.
|
||||||
*
|
*
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
void lpc313x_lowsetup(void)
|
void lpc31_lowsetup(void)
|
||||||
{
|
{
|
||||||
#ifdef NEED_LOWSETUP
|
#ifdef NEED_LOWSETUP
|
||||||
uint32_t regval;
|
uint32_t regval;
|
||||||
|
|
||||||
/* Enable UART system clock */
|
/* Enable UART system clock */
|
||||||
|
|
||||||
lpc313x_enableclock(CLKID_UARTAPBCLK);
|
lpc31_enableclock(CLKID_UARTAPBCLK);
|
||||||
lpc313x_enableclock(CLKID_UARTUCLK);
|
lpc31_enableclock(CLKID_UARTUCLK);
|
||||||
|
|
||||||
/* Clear fifos */
|
/* Clear fifos */
|
||||||
|
|
||||||
putreg32((UART_FCR_RXFIFORST|UART_FCR_TXFIFORST), LPC313X_UART_FCR);
|
putreg32((UART_FCR_RXFIFORST|UART_FCR_TXFIFORST), LPC31_UART_FCR);
|
||||||
|
|
||||||
/* Set trigger */
|
/* Set trigger */
|
||||||
|
|
||||||
putreg32((UART_FCR_FIFOENABLE|UART_FCR_RXTRIGLEVEL_16), LPC313X_UART_FCR);
|
putreg32((UART_FCR_FIFOENABLE|UART_FCR_RXTRIGLEVEL_16), LPC31_UART_FCR);
|
||||||
|
|
||||||
/* Set up the LCR */
|
/* Set up the LCR */
|
||||||
|
|
||||||
@@ -316,7 +316,7 @@ void lpc313x_lowsetup(void)
|
|||||||
#elif CONFIG_UART_PARITY == 2
|
#elif CONFIG_UART_PARITY == 2
|
||||||
regval |= (UART_LCR_PAREVEN|UART_LCR_PAREN);
|
regval |= (UART_LCR_PAREVEN|UART_LCR_PAREN);
|
||||||
#endif
|
#endif
|
||||||
putreg32(regval, LPC313X_UART_LCR);
|
putreg32(regval, LPC31_UART_LCR);
|
||||||
|
|
||||||
/* Set the BAUD divisor */
|
/* Set the BAUD divisor */
|
||||||
|
|
||||||
@@ -326,7 +326,7 @@ void lpc313x_lowsetup(void)
|
|||||||
|
|
||||||
putreg32((UART_FCR_RXTRIGLEVEL_16|UART_FCR_TXFIFORST|
|
putreg32((UART_FCR_RXTRIGLEVEL_16|UART_FCR_TXFIFORST|
|
||||||
UART_FCR_RXFIFORST|UART_FCR_FIFOENABLE),
|
UART_FCR_RXFIFORST|UART_FCR_FIFOENABLE),
|
||||||
LPC313X_UART_FCR);
|
LPC31_UART_FCR);
|
||||||
|
|
||||||
/* The NuttX serial driver waits for the first THRE interrrupt before
|
/* The NuttX serial driver waits for the first THRE interrrupt before
|
||||||
* sending serial data... However, it appears that the lpc313x hardware
|
* sending serial data... However, it appears that the lpc313x hardware
|
||||||
@@ -335,7 +335,7 @@ void lpc313x_lowsetup(void)
|
|||||||
* startup to kick things off.
|
* startup to kick things off.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
putreg32('\0', LPC313X_UART_THR);
|
putreg32('\0', LPC31_UART_THR);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -351,6 +351,6 @@ void up_lowputc(char ch)
|
|||||||
{
|
{
|
||||||
#ifdef HAVE_CONSOLE
|
#ifdef HAVE_CONSOLE
|
||||||
up_waittxready();
|
up_waittxready();
|
||||||
putreg32((uint32_t)ch, LPC313X_UART_THR);
|
putreg32((uint32_t)ch, LPC31_UART_THR);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_mci.h
|
* arch/arm/src/lpc31xx/lpc31_mci.h
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -33,15 +33,15 @@
|
|||||||
*
|
*
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#ifndef __ARCH_ARM_SRC_LPC313X_MCI_H
|
#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_MCI_H
|
||||||
#define __ARCH_ARM_SRC_LPC313X_MCI_H
|
#define __ARCH_ARM_SRC_LPC31XX_LPC31_MCI_H
|
||||||
|
|
||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* Included Files
|
* Included Files
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#include <nuttx/config.h>
|
#include <nuttx/config.h>
|
||||||
#include "lpc313x_memorymap.h"
|
#include "lpc31_memorymap.h"
|
||||||
|
|
||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -49,66 +49,66 @@
|
|||||||
|
|
||||||
/* MCI register base address offset into the MCI domain *****************************************/
|
/* MCI register base address offset into the MCI domain *****************************************/
|
||||||
|
|
||||||
#define LPC313X_MCI_VBASE (LPC313X_MCI_VSECTION)
|
#define LPC31_MCI_VBASE (LPC31_MCI_VSECTION)
|
||||||
#define LPC313X_MCI_PBASE (LPC313X_MCI_PSECTION)
|
#define LPC31_MCI_PBASE (LPC31_MCI_PSECTION)
|
||||||
|
|
||||||
/* MCI register offsets (with respect to the MCI base) ******************************************/
|
/* MCI register offsets (with respect to the MCI base) ******************************************/
|
||||||
|
|
||||||
#define LPC313X_MCI_CTRL_OFFSET 0x000 /* Control register */
|
#define LPC31_MCI_CTRL_OFFSET 0x000 /* Control register */
|
||||||
#define LPC313X_MCI_PWREN_OFFSET 0x004 /* Reserved */
|
#define LPC31_MCI_PWREN_OFFSET 0x004 /* Reserved */
|
||||||
#define LPC313X_MCI_CLKDIV_OFFSET 0x008 /* Clock-divider register */
|
#define LPC31_MCI_CLKDIV_OFFSET 0x008 /* Clock-divider register */
|
||||||
#define LPC313X_MCI_CLKSRC_OFFSET 0x00c /* Clock-source register */
|
#define LPC31_MCI_CLKSRC_OFFSET 0x00c /* Clock-source register */
|
||||||
#define LPC313X_MCI_CLKENA_OFFSET 0x010 /* Clock-enable register */
|
#define LPC31_MCI_CLKENA_OFFSET 0x010 /* Clock-enable register */
|
||||||
#define LPC313X_MCI_TMOUT_OFFSET 0x014 /* Time-out register */
|
#define LPC31_MCI_TMOUT_OFFSET 0x014 /* Time-out register */
|
||||||
#define LPC313X_MCI_CTYPE_OFFSET 0x018 /* Card-type register */
|
#define LPC31_MCI_CTYPE_OFFSET 0x018 /* Card-type register */
|
||||||
#define LPC313X_MCI_BLKSIZ_OFFSET 0x01c /* Block-size register */
|
#define LPC31_MCI_BLKSIZ_OFFSET 0x01c /* Block-size register */
|
||||||
#define LPC313X_MCI_BYTCNT_OFFSET 0x020 /* Byte-count register */
|
#define LPC31_MCI_BYTCNT_OFFSET 0x020 /* Byte-count register */
|
||||||
#define LPC313X_MCI_INTMASK_OFFSET 0x024 /* Interrupt-mask register */
|
#define LPC31_MCI_INTMASK_OFFSET 0x024 /* Interrupt-mask register */
|
||||||
#define LPC313X_MCI_CMDARG_OFFSET 0x028 /* Command-argument register */
|
#define LPC31_MCI_CMDARG_OFFSET 0x028 /* Command-argument register */
|
||||||
#define LPC313X_MCI_CMD_OFFSET 0x02c /* Command register */
|
#define LPC31_MCI_CMD_OFFSET 0x02c /* Command register */
|
||||||
#define LPC313X_MCI_RESP0_OFFSET 0x030 /* Response-0 register */
|
#define LPC31_MCI_RESP0_OFFSET 0x030 /* Response-0 register */
|
||||||
#define LPC313X_MCI_RESP1_OFFSET 0x034 /* Response-1register */
|
#define LPC31_MCI_RESP1_OFFSET 0x034 /* Response-1register */
|
||||||
#define LPC313X_MCI_RESP2_OFFSET 0x038 /* Response-2 register */
|
#define LPC31_MCI_RESP2_OFFSET 0x038 /* Response-2 register */
|
||||||
#define LPC313X_MCI_RESP3_OFFSET 0x03c /* Response-3 register */
|
#define LPC31_MCI_RESP3_OFFSET 0x03c /* Response-3 register */
|
||||||
#define LPC313X_MCI_MINTSTS_OFFSET 0x040 /* Masked interrupt-status register */
|
#define LPC31_MCI_MINTSTS_OFFSET 0x040 /* Masked interrupt-status register */
|
||||||
#define LPC313X_MCI_RINTSTS_OFFSET 0x044 /* Raw interrupt-status register */
|
#define LPC31_MCI_RINTSTS_OFFSET 0x044 /* Raw interrupt-status register */
|
||||||
#define LPC313X_MCI_STATUS_OFFSET 0x048 /* Status register */
|
#define LPC31_MCI_STATUS_OFFSET 0x048 /* Status register */
|
||||||
#define LPC313X_MCI_FIFOTH_OFFSET 0x04c /* FIFO threshold register */
|
#define LPC31_MCI_FIFOTH_OFFSET 0x04c /* FIFO threshold register */
|
||||||
#define LPC313X_MCI_CDETECT_OFFSET 0x050 /* Card-detect register value */
|
#define LPC31_MCI_CDETECT_OFFSET 0x050 /* Card-detect register value */
|
||||||
#define LPC313X_MCI_WRTPRT_OFFSET 0x054 /* Write-protect register */
|
#define LPC31_MCI_WRTPRT_OFFSET 0x054 /* Write-protect register */
|
||||||
/* 0x58: Reserved */
|
/* 0x58: Reserved */
|
||||||
#define LPC313X_MCI_TCBCNT_OFFSET 0x05c /* Transferred CIU card byte count */
|
#define LPC31_MCI_TCBCNT_OFFSET 0x05c /* Transferred CIU card byte count */
|
||||||
#define LPC313X_MCI_TBBCNT_OFFSET 0x060 /* Transferred cpu/DMA to/from BIU-FIFO byte count */
|
#define LPC31_MCI_TBBCNT_OFFSET 0x060 /* Transferred cpu/DMA to/from BIU-FIFO byte count */
|
||||||
/* 0x064-0x0ff: Reserved */
|
/* 0x064-0x0ff: Reserved */
|
||||||
#define LPC313X_MCI_DATA_OFFSET 0x100 /* Data FIFO read/write (>=) */
|
#define LPC31_MCI_DATA_OFFSET 0x100 /* Data FIFO read/write (>=) */
|
||||||
|
|
||||||
/* MCI register (virtual) addresses *************************************************************/
|
/* MCI register (virtual) addresses *************************************************************/
|
||||||
|
|
||||||
#define LPC313X_MCI_CTRL (LPC313X_MCI_VBASE+LPC313X_MCI_CTRL_OFFSET)
|
#define LPC31_MCI_CTRL (LPC31_MCI_VBASE+LPC31_MCI_CTRL_OFFSET)
|
||||||
#define LPC313X_MCI_PWREN (LPC313X_MCI_VBASE+LPC313X_MCI_PWREN_OFFSET)
|
#define LPC31_MCI_PWREN (LPC31_MCI_VBASE+LPC31_MCI_PWREN_OFFSET)
|
||||||
#define LPC313X_MCI_CLKDIV (LPC313X_MCI_VBASE+LPC313X_MCI_CLKDIV_OFFSET)
|
#define LPC31_MCI_CLKDIV (LPC31_MCI_VBASE+LPC31_MCI_CLKDIV_OFFSET)
|
||||||
#define LPC313X_MCI_CLKSRC (LPC313X_MCI_VBASE+LPC313X_MCI_CLKSRC_OFFSET)
|
#define LPC31_MCI_CLKSRC (LPC31_MCI_VBASE+LPC31_MCI_CLKSRC_OFFSET)
|
||||||
#define LPC313X_MCI_CLKENA (LPC313X_MCI_VBASE+LPC313X_MCI_CLKENA_OFFSET)
|
#define LPC31_MCI_CLKENA (LPC31_MCI_VBASE+LPC31_MCI_CLKENA_OFFSET)
|
||||||
#define LPC313X_MCI_TMOUT (LPC313X_MCI_VBASE+LPC313X_MCI_TMOUT_OFFSET)
|
#define LPC31_MCI_TMOUT (LPC31_MCI_VBASE+LPC31_MCI_TMOUT_OFFSET)
|
||||||
#define LPC313X_MCI_CTYPE (LPC313X_MCI_VBASE+LPC313X_MCI_CTYPE_OFFSET)
|
#define LPC31_MCI_CTYPE (LPC31_MCI_VBASE+LPC31_MCI_CTYPE_OFFSET)
|
||||||
#define LPC313X_MCI_BLKSIZ (LPC313X_MCI_VBASE+LPC313X_MCI_BLKSIZ_OFFSET)
|
#define LPC31_MCI_BLKSIZ (LPC31_MCI_VBASE+LPC31_MCI_BLKSIZ_OFFSET)
|
||||||
#define LPC313X_MCI_BYTCNT (LPC313X_MCI_VBASE+LPC313X_MCI_BYTCNT_OFFSET)
|
#define LPC31_MCI_BYTCNT (LPC31_MCI_VBASE+LPC31_MCI_BYTCNT_OFFSET)
|
||||||
#define LPC313X_MCI_INTMASK (LPC313X_MCI_VBASE+LPC313X_MCI_INTMASK_OFFSET)
|
#define LPC31_MCI_INTMASK (LPC31_MCI_VBASE+LPC31_MCI_INTMASK_OFFSET)
|
||||||
#define LPC313X_MCI_CMDARG (LPC313X_MCI_VBASE+LPC313X_MCI_CMDARG_OFFSET)
|
#define LPC31_MCI_CMDARG (LPC31_MCI_VBASE+LPC31_MCI_CMDARG_OFFSET)
|
||||||
#define LPC313X_MCI_CMD (LPC313X_MCI_VBASE+LPC313X_MCI_CMD_OFFSET)
|
#define LPC31_MCI_CMD (LPC31_MCI_VBASE+LPC31_MCI_CMD_OFFSET)
|
||||||
#define LPC313X_MCI_RESP0 (LPC313X_MCI_VBASE+LPC313X_MCI_RESP0_OFFSET)
|
#define LPC31_MCI_RESP0 (LPC31_MCI_VBASE+LPC31_MCI_RESP0_OFFSET)
|
||||||
#define LPC313X_MCI_RESP1 (LPC313X_MCI_VBASE+LPC313X_MCI_RESP1_OFFSET)
|
#define LPC31_MCI_RESP1 (LPC31_MCI_VBASE+LPC31_MCI_RESP1_OFFSET)
|
||||||
#define LPC313X_MCI_RESP2 (LPC313X_MCI_VBASE+LPC313X_MCI_RESP2_OFFSET)
|
#define LPC31_MCI_RESP2 (LPC31_MCI_VBASE+LPC31_MCI_RESP2_OFFSET)
|
||||||
#define LPC313X_MCI_RESP3 (LPC313X_MCI_VBASE+LPC313X_MCI_RESP3_OFFSET)
|
#define LPC31_MCI_RESP3 (LPC31_MCI_VBASE+LPC31_MCI_RESP3_OFFSET)
|
||||||
#define LPC313X_MCI_MINTSTS (LPC313X_MCI_VBASE+LPC313X_MCI_MINTSTS_OFFSET)
|
#define LPC31_MCI_MINTSTS (LPC31_MCI_VBASE+LPC31_MCI_MINTSTS_OFFSET)
|
||||||
#define LPC313X_MCI_RINTSTS (LPC313X_MCI_VBASE+LPC313X_MCI_RINTSTS_OFFSET)
|
#define LPC31_MCI_RINTSTS (LPC31_MCI_VBASE+LPC31_MCI_RINTSTS_OFFSET)
|
||||||
#define LPC313X_MCI_STATUS (LPC313X_MCI_VBASE+LPC313X_MCI_STATUS_OFFSET)
|
#define LPC31_MCI_STATUS (LPC31_MCI_VBASE+LPC31_MCI_STATUS_OFFSET)
|
||||||
#define LPC313X_MCI_FIFOTH (LPC313X_MCI_VBASE+LPC313X_MCI_FIFOTH_OFFSET)
|
#define LPC31_MCI_FIFOTH (LPC31_MCI_VBASE+LPC31_MCI_FIFOTH_OFFSET)
|
||||||
#define LPC313X_MCI_CDETECT (LPC313X_MCI_VBASE+LPC313X_MCI_CDETECT_OFFSET)
|
#define LPC31_MCI_CDETECT (LPC31_MCI_VBASE+LPC31_MCI_CDETECT_OFFSET)
|
||||||
#define LPC313X_MCI_WRTPRT (LPC313X_MCI_VBASE+LPC313X_MCI_WRTPRT_OFFSET)
|
#define LPC31_MCI_WRTPRT (LPC31_MCI_VBASE+LPC31_MCI_WRTPRT_OFFSET)
|
||||||
#define LPC313X_MCI_TCBCNT (LPC313X_MCI_VBASE+LPC313X_MCI_TCBCNT_OFFSET)
|
#define LPC31_MCI_TCBCNT (LPC31_MCI_VBASE+LPC31_MCI_TCBCNT_OFFSET)
|
||||||
#define LPC313X_MCI_TBBCNT (LPC313X_MCI_VBASE+LPC313X_MCI_TBBCNT_OFFSET)
|
#define LPC31_MCI_TBBCNT (LPC31_MCI_VBASE+LPC31_MCI_TBBCNT_OFFSET)
|
||||||
#define LPC313X_MCI_DATA (LPC313X_MCI_VBASE+LPC313X_MCI_DATA_OFFSET)
|
#define LPC31_MCI_DATA (LPC31_MCI_VBASE+LPC31_MCI_DATA_OFFSET)
|
||||||
|
|
||||||
/* MCI register bit definitions *****************************************************************/
|
/* MCI register bit definitions *****************************************************************/
|
||||||
|
|
||||||
@@ -267,4 +267,4 @@
|
|||||||
* Public Functions
|
* Public Functions
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#endif /* __ARCH_ARM_SRC_LPC313X_MCI_H */
|
#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_MCI_H */
|
||||||
Executable
+414
@@ -0,0 +1,414 @@
|
|||||||
|
/************************************************************************************
|
||||||
|
* arch/arm/src/lpc31xx/lpc31_memorymap.h
|
||||||
|
*
|
||||||
|
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
||||||
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
*
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in
|
||||||
|
* the documentation and/or other materials provided with the
|
||||||
|
* distribution.
|
||||||
|
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||||
|
* used to endorse or promote products derived from this software
|
||||||
|
* without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||||
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||||
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||||
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||||
|
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||||
|
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||||
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||||
|
* POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_MEMORYMAP_H
|
||||||
|
#define __ARCH_ARM_SRC_LPC31XX_LPC31_MEMORYMAP_H
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Included Files
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
#include <nuttx/config.h>
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Pre-processor Definitions
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
/* LPC31XX Physical (unmapped) Memory Map */
|
||||||
|
|
||||||
|
#define LPC31_FIRST_PSECTION 0x00000000 /* Beginning of the physical address space */
|
||||||
|
#define LPC31_SHADOWSPACE_PSECTION 0x00000000 /* 0x00000000-0x00000fff: Shadow Area 4Kb */
|
||||||
|
/* 0x00001000-0xff027fff: Reserved */
|
||||||
|
#define LPC31_INTSRAM_PSECTION 0x11028000 /* Internal SRAM 0+1 192Kb */
|
||||||
|
# define LPC31_INTSRAM0_PADDR 0x11028000 /* 0x11028000-0x1103ffff: Internal SRAM 0 96Kb */
|
||||||
|
# define LPC31_INTSRAM1_PADDR 0x11040000 /* 0x11040000-0x11057fff: Internal SRAM 1 96Kb */
|
||||||
|
/* 0x11058000-11ffffffff: Reserved */
|
||||||
|
#define LPC31_INTSROM0_PSECTION 0x12000000 /* 0x12000000-0x1201ffff: Internal SROM 0 128Kb */
|
||||||
|
/* 0x12020000-0x12ffffff: Reserved */
|
||||||
|
#define LPC31_APB01_PSECTION 0x13000000 /* 0x13000000-0x1300bfff: APB0 32Kb APB1 16Kb */
|
||||||
|
# define LPC31_APB0_PADDR 0x13000000 /* 0x13000000-0x13007fff: APB0 32Kb */
|
||||||
|
# define LPC31_APB1_PADDR 0x13008000 /* 0x13008000-0x1300bfff: APB1 16Kb */
|
||||||
|
/* 0x1300c000-0x14ffffff: Reserved */
|
||||||
|
#define LPC31_APB2_PSECTION 0x15000000 /* 0x15000000-0x15003fff: APB2 16Kb */
|
||||||
|
#define LPC31_APB3_PSECTION 0x16000000 /* 0x16000000-0x160003ff: APB3 1Kb */
|
||||||
|
#define LPC31_APB4MPMC_PSECTION 0x17000000 /* 8Kb */
|
||||||
|
# define LPC31_APB4_PADDR 0x17000000 /* 0x17000000-0x17000fff: APB4 4Kb */
|
||||||
|
# define LPC31_MPMC_PADDR 0x17008000 /* 0x17008000-0x17008fff: MPMC cfg 4Kb */
|
||||||
|
/* 0x17009000-0x17ffffff: Reserved */
|
||||||
|
#define LPC31_MCI_PSECTION 0x18000000 /* 0x18000000 0x180003ff: MCI/SD/SDIO 1Kb */
|
||||||
|
/* 0x18000900-0x18ffffff: Reserved */
|
||||||
|
#define LPC31_USBOTG_PSECTION 0x19000000 /* 0x19000000-0x19000fff: USB OTG 4Kb */
|
||||||
|
/* 0x19001000-0x1fffffff: Reserved */
|
||||||
|
#define LPC31_EXTSRAM_PSECTION 0x20000000 /* 64-128Kb */
|
||||||
|
# define LPC31_EXTSRAM0_PADDR 0x20000000 /* 0x20000000-0x2001ffff: External SRAM 0 64-128Kb */
|
||||||
|
# define LPC31_EXTSRAM1_PADDR 0x20020000 /* 0x20020000-0x2003ffff: External SRAM 1 64-128Kb */
|
||||||
|
#define LPC31_EXTSDRAM0_PSECTION 0x30000000 /* 0x30000000-0x37ffffff: External SDRAM 0 128Mb */
|
||||||
|
/* 0x40000000-0x5fffffff: Reserved */
|
||||||
|
#define LPC31_INTC_PSECTION 0x60000000 /* 0x60000000-0x60000fff: Interrupt controller 4Kb */
|
||||||
|
/* 0x60001000-0x6fffffff: Reserved */
|
||||||
|
#define LPC31_NAND_PSECTION 0x70000000 /* 0x70000000-0x700007ff: NANDFLASH Ctrl 2Kb */
|
||||||
|
/* 0x70000800-0xffffffff: Reserved */
|
||||||
|
#ifdef CONFIG_LPC31_EXTNAND /* End of the physical address space */
|
||||||
|
# define LPC31_LAST_PSECTION (LPC31_NAND_PSECTION + (1 << 20))
|
||||||
|
#else
|
||||||
|
# define LPC31_LAST_PSECTION (LPC31_INTC_PSECTION + (1 << 20))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* APB0-4 Domain Offsets */
|
||||||
|
|
||||||
|
#define LPC31_APB0_EVNTRTR_OFFSET 0x00000000 /* Event Router */
|
||||||
|
#define LPC31_APB0_ADC_OFFSET 0x00002000 /* ADC 10-bit */
|
||||||
|
#define LPC31_APB0_WDT_OFFSET 0x00002400 /* WDT */
|
||||||
|
#define LPC31_APB0_SYSCREG_OFFSET 0x00002800 /* SYSCREG block */
|
||||||
|
#define LPC31_APB0_IOCONFIG_OFFSET 0x00003000 /* IOCONFIG */
|
||||||
|
#define LPC31_APB0_GCU_OFFSET 0x00004000 /* GCU */
|
||||||
|
/* 0x00005000 Reserved */
|
||||||
|
#define LPC31_APB0_RNG_OFFSET 0x00006000 /* RNG */
|
||||||
|
|
||||||
|
#define LPC31_APB1_TIMER0_OFFSET 0x00000000 /* TIMER0 */
|
||||||
|
#define LPC31_APB1_TIMER1_OFFSET 0x00000400 /* TIMER1 */
|
||||||
|
#define LPC31_APB1_TIMER2_OFFSET 0x00000800 /* TIMER2 */
|
||||||
|
#define LPC31_APB1_TIMER3_OFFSET 0x00000c00 /* TIMER3 */
|
||||||
|
#define LPC31_APB1_PWM_OFFSET 0x00001000 /* PWM */
|
||||||
|
#define LPC31_APB1_I2C0_OFFSET 0x00002000 /* I2C0 */
|
||||||
|
#define LPC31_APB1_I2C1_OFFSET 0x00002400 /* I2C1 */
|
||||||
|
|
||||||
|
#define LPC31_APB2_PCM_OFFSET 0x00000000 /* PCM */
|
||||||
|
#define LPC31_APB2_LCD_OFFSET 0x00000400 /* LCD */
|
||||||
|
/* 0x00000800 Reserved */
|
||||||
|
#define LPC31_APB2_UART_OFFSET 0x00001000 /* UART */
|
||||||
|
#define LPC31_APB2_SPI_OFFSET 0x00002000 /* SPI */
|
||||||
|
/* 0x00003000 Reserved */
|
||||||
|
|
||||||
|
#define LPC31_APB3_I2SCONFIG_OFFSET 0x00000000 /* I2S System Configuration */
|
||||||
|
#define LPC31_APB3_I2STX0_OFFSET 0x00000080 /* I2S TX0 */
|
||||||
|
#define LPC31_APB3_I2STX1_OFFSET 0x00000100 /* I2S TX1 */
|
||||||
|
#define LPC31_APB3_I2SRX0_OFFSET 0x00000180 /* I2S RX0 */
|
||||||
|
#define LPC31_APB3_I2SRX1_OFFSET 0x00000200 /* I2S RX1 */
|
||||||
|
/* 0x00000280 Reserved */
|
||||||
|
|
||||||
|
#define LPC31_APB4_DMA_OFFSET 0x00000000 /* DMA */
|
||||||
|
#define LPC31_APB4_NAND_OFFSET 0x00000800 /* NAND FLASH Controller */
|
||||||
|
/* 0x00001000 Reserved */
|
||||||
|
|
||||||
|
/* Sizes of memory regions in bytes */
|
||||||
|
|
||||||
|
#define LPC31_SHADOWSPACE_SIZE (4*1024)
|
||||||
|
#define LPC31_INTSRAM0_SIZE (96*1024)
|
||||||
|
#define LPC31_INTSRAM1_SIZE (96*1024)
|
||||||
|
#define LPC31_INTSROM0_SIZE (128*1024)
|
||||||
|
#define LPC31_APB0_SIZE (32*1024)
|
||||||
|
#define LPC31_APB1_SIZE (16*1024)
|
||||||
|
#define LPC31_APB2_SIZE (16*1024)
|
||||||
|
#define LPC31_APB3_SIZE (1*1024)
|
||||||
|
#define LPC31_APB4_SIZE (4*1024)
|
||||||
|
#define LPC31_MPMC_SIZE (4*1024)
|
||||||
|
#define LPC31_APB4MPMC_SIZE (LPC31_APB4_SIZE+LPC31_MPMC_SIZE)
|
||||||
|
#define LPC31_MCI_SIZE (1*1024)
|
||||||
|
#define LPC31_USBOTG_SIZE (4*1024)
|
||||||
|
#define LPC31_INTC_SIZE (4*1024)
|
||||||
|
#define LPC31_NAND_SIZE (2*1024)
|
||||||
|
|
||||||
|
#if defined(CONFIG_ARCH_CHIP_LPC3131)
|
||||||
|
# define LPC31_ISRAM_SIZE (LPC31_INTSRAM0_SIZE+LPC31_INTSRAM1_SIZE)
|
||||||
|
#elif defined(CONFIG_ARCH_CHIP_LPC3130)
|
||||||
|
# define LPC31_ISRAM_SIZE LPC31_INTSRAM0_SIZE
|
||||||
|
#else
|
||||||
|
# error "Unsupported LPC31XX architecture"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Convert size in bytes to number of sections (in Mb). */
|
||||||
|
|
||||||
|
#define _NSECTIONS(b) (((b)+0x000fffff) >> 20)
|
||||||
|
|
||||||
|
/* Sizes of sections/regions. The boot logic in lpc31_boot.c, will select
|
||||||
|
* 1Mb level 1 MMU mappings to span the entire physical address space.
|
||||||
|
* The definitiions below specifiy the number of 1Mb entries that are
|
||||||
|
* required to span a particular address region.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define LPC31_SHADOWSPACE_NSECTIONS 1 /* 4Kb - <1 section */
|
||||||
|
#define LPC31_INTSRAM_NSECTIONS 1 /* 96 or 192Kb - <1 section */
|
||||||
|
#define LPC31_APB01_NSECTIONS 1 /* 32Kb - <1 section */
|
||||||
|
#define LPC31_INTSROM0_NSECTIONS 1 /* 128Kb - <1 section */
|
||||||
|
#define LPC31_APB1_NSECTIONS 1 /* 16Kb - <1 section */
|
||||||
|
#define LPC31_APB2_NSECTIONS 1 /* 16Kb - <1 section */
|
||||||
|
#define LPC31_APB3_NSECTIONS 1 /* 1Kb - <1 section */
|
||||||
|
#define LPC31_APB4MPMC_NSECTIONS 1 /* 8Kb - <1 section */
|
||||||
|
#define LPC31_MCI_NSECTIONS 1 /* 1Kb - <1 section */
|
||||||
|
#define LPC31_USBOTG_NSECTIONS 1 /* 4Kb - <1 section */
|
||||||
|
#define LPC31_EXTSRAM_NSECTIONS 1 /* 64-128Kb - <1 section */
|
||||||
|
#define LPC31_INTC_NSECTIONS 1 /* 4Kb - <1 section */
|
||||||
|
#define LPC31_NAND_NSECTIONS 1 /* 2Kb - <1 section */
|
||||||
|
|
||||||
|
/* External SDRAM is a special case -- the number of sections depends upon
|
||||||
|
* the size of the SDRAM installed.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(CONFIG_LPC31_EXTSDRAM) && CONFIG_LPC31_EXTSDRAMSIZE > 0
|
||||||
|
# define LPC31_EXTSDRAM0_NSECTIONS _NSECTIONS(CONFIG_LPC31_EXTSDRAMSIZE)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Section MMU Flags */
|
||||||
|
|
||||||
|
#define LPC31_SHADOWSPACE_MMUFLAGS MMU_ROMFLAGS
|
||||||
|
#define LPC31_INTSRAM_MMUFLAGS MMU_MEMFLAGS
|
||||||
|
#define LPC31_INTSROM_MMUFLAGS MMU_MEMFLAGS
|
||||||
|
#define LPC31_APB01_MMUFLAGS MMU_IOFLAGS
|
||||||
|
#define LPC31_APB2_MMUFLAGS MMU_IOFLAGS
|
||||||
|
#define LPC31_APB3_MMUFLAGS MMU_IOFLAGS
|
||||||
|
#define LPC31_APB4MPMC_MMUFLAGS MMU_IOFLAGS
|
||||||
|
#define LPC31_MCI_MMUFLAGS MMU_IOFLAGS
|
||||||
|
#define LPC31_USBOTG_MMUFLAGS MMU_IOFLAGS
|
||||||
|
#define LPC31_EXTSRAM_MMUFLAGS MMU_MEMFLAGS
|
||||||
|
#define LPC31_EXTSDRAM_MMUFLAGS MMU_MEMFLAGS
|
||||||
|
#define LPC31_INTC_MMUFLAGS MMU_IOFLAGS
|
||||||
|
#define LPC31_NAND_MMUFLAGS MMU_IOFLAGS
|
||||||
|
|
||||||
|
/* board_memorymap.h contains special mappings that are needed when a ROM
|
||||||
|
* memory map is used. It is included in this odd location becaue it depends
|
||||||
|
* on some the virtual address definitions provided above.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch/board/board_memorymap.h>
|
||||||
|
|
||||||
|
/* LPC31XX Virtual (mapped) Memory Map. These are the mappings that will
|
||||||
|
* be created if the page table lies in RAM. If the platform has another,
|
||||||
|
* read-only, pre-initialized page table (perhaps in ROM), then the board.h
|
||||||
|
* file must provide these definitions.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef CONFIG_ARCH_ROMPGTABLE
|
||||||
|
# define LPC31_FIRST_VSECTION 0x00000000 /* Beginning of the virtual address space */
|
||||||
|
# define LPC31_SHADOWSPACE_VSECTION 0x00000000 /* 0x00000000-0x00000fff: Shadow Area 4Kb */
|
||||||
|
# define LPC31_INTSRAM_VSECTION 0x11028000 /* Internal SRAM 96Kb-192Kb */
|
||||||
|
# define LPC31_INTSRAM0_VADDR 0x11028000 /* 0x11028000-0x1103ffff: Internal SRAM 0 96Kb */
|
||||||
|
# define LPC31_INTSRAM1_VADDR 0x11040000 /* 0x11040000-0x11057fff: Internal SRAM 1 96Kb */
|
||||||
|
# define LPC31_INTSROM0_VSECTION 0x12000000 /* 0x12000000-0x1201ffff: Internal SROM 0 128Kb */
|
||||||
|
# define LPC31_APB01_VSECTION 0x13000000 /* 0x13000000-0x1300bfff: APB0 32Kb APB0 32Kb */
|
||||||
|
# define LPC31_APB0_VADDR 0x13000000 /* 0x13000000-0x13007fff: APB0 32Kb */
|
||||||
|
# define LPC31_APB1_VADDR 0x13008000 /* 0x13008000-0x1300bfff: APB1 16Kb */
|
||||||
|
# define LPC31_APB2_VSECTION 0x15000000 /* 0x15000000-0x15003fff: APB2 16Kb */
|
||||||
|
# define LPC31_APB3_VSECTION 0x16000000 /* 0x16000000-0x160003ff: APB3 1Kb */
|
||||||
|
# define LPC31_APB4MPMC_VSECTION 0x17000000 /* 8Kb */
|
||||||
|
# define LPC31_APB4_VADDR 0x17000000 /* 0x17000000-0x17000fff: APB4 4Kb */
|
||||||
|
# define LPC31_MPMC_VADDR 0x17008000 /* 0x17008000-0x17008fff: MPMC cfg 4Kb */
|
||||||
|
# define LPC31_MCI_VSECTION 0x18000000 /* 0x18000000 0x180003ff: MCI/SD/SDIO 1Kb */
|
||||||
|
# define LPC31_USBOTG_VSECTION 0x19000000 /* 0x19000000-0x19000fff: USB OTG 4Kb */
|
||||||
|
# define LPC31_EXTSRAM_VSECTION 0x20020000 /* 64-128Kb */
|
||||||
|
# define LPC31_EXTSRAM0_VADDR 0x20000000 /* 0x20000000-0x2001ffff: External SRAM 0 64-128Kb */
|
||||||
|
# define LPC31_EXTSRAM1_VADDR 0x20020000 /* 0x20020000-0x2003ffff: External SRAM 1 64-128Kb */
|
||||||
|
# define LPC31_EXTSDRAM0_VSECTION 0x30000000 /* 0x30000000-0x37ffffff: External SDRAM 0 128Mb */
|
||||||
|
# define LPC31_INTC_VSECTION 0x60000000 /* 0x60000000-0x60000fff: Interrupt controller 4Kb */
|
||||||
|
# define LPC31_NAND_VSECTION 0x70000000 /* 0x70000000-0x700007ff: NANDFLASH Ctrl 2Kb */
|
||||||
|
#
|
||||||
|
# ifdef CONFIG_LPC31_EXTNAND /* End of the virtual address space */
|
||||||
|
# define LPC31_LAST_VSECTION (LPC31_NAND_VSECTION + (1 << 20))
|
||||||
|
# else
|
||||||
|
# define LPC31_LAST_VSECTION (LPC31_INTC_VSECTION + (1 << 20))
|
||||||
|
# endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* The boot logic will create a temporarily mapping based on where NuttX is
|
||||||
|
* executing in memory. In this case, NuttX could be running from NOR FLASH,
|
||||||
|
* SDRAM, external SRAM, or ISRAM.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#if defined(CONFIG_BOOT_RUNFROMFLASH)
|
||||||
|
# define NUTTX_START_VADDR LPC31_MPMC_VADDR
|
||||||
|
#elif defined(CONFIG_BOOT_RUNFROMSDRAM)
|
||||||
|
# define NUTTX_START_VADDR LPC31_EXTSDRAM0_VSECTION
|
||||||
|
#elif defined(CONFIG_BOOT_RUNFROMEXTSRAM)
|
||||||
|
# define NUTTX_START_VADDR LPC31_EXTSRAM0_VADDR
|
||||||
|
#else /* CONFIG_BOOT_RUNFROMISRAM, CONFIG_PAGING */
|
||||||
|
# define NUTTX_START_VADDR LPC31_INTSRAM0_VADDR
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Determine the address of the MMU page table. We will try to place that page
|
||||||
|
* table at the beginng of ISRAM0 if the vectors are at the high address, 0xffff:0000
|
||||||
|
* or at the end of ISRAM1 (or ISRAM0 on a LPC3130) if the vectors are at 0x0000:0000
|
||||||
|
*
|
||||||
|
* Or... the user may specify the address of the page table explicitly be defining
|
||||||
|
* CONFIG_PGTABLE_VADDR and CONFIG_PGTABLE_PADDR in the configuration or board.h file.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#undef PGTABLE_IN_HIGHSRAM
|
||||||
|
#undef PGTABLE_IN_LOWSRAM
|
||||||
|
|
||||||
|
#if !defined(PGTABLE_BASE_PADDR) || !defined(PGTABLE_BASE_VADDR)
|
||||||
|
|
||||||
|
/* Sanity check.. if one is undefined, both should be undefined */
|
||||||
|
|
||||||
|
# if defined(PGTABLE_BASE_PADDR) || defined(PGTABLE_BASE_VADDR)
|
||||||
|
# error "Only one of PGTABLE_BASE_PADDR or PGTABLE_BASE_VADDR is defined"
|
||||||
|
# endif
|
||||||
|
|
||||||
|
/* A sanity check, if the configuration says that the page table is read-only
|
||||||
|
* and pre-initialized (maybe ROM), then it should have also defined both of
|
||||||
|
* the page table base addresses.
|
||||||
|
*/
|
||||||
|
|
||||||
|
# ifdef CONFIG_ARCH_ROMPGTABLE
|
||||||
|
# error "CONFIG_ARCH_ROMPGTABLE defined; PGTABLE_BASE_P/VADDR not defined"
|
||||||
|
# else
|
||||||
|
|
||||||
|
/* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory
|
||||||
|
* map probably do not apply because paging logic will probably partition
|
||||||
|
* the SRAM section differently. In particular, if the page table is located
|
||||||
|
* at the end of SRAM, then the virtual page table address defined below
|
||||||
|
* will probably be in error.
|
||||||
|
*
|
||||||
|
* We work around this header file interdependency by (1) insisting that
|
||||||
|
* pg_macros.h be included AFTER this header file, then (2) allowing the
|
||||||
|
* pg_macros.h header file to redefine PGTABLE_BASE_VADDR.
|
||||||
|
*/
|
||||||
|
|
||||||
|
# if defined(CONFIG_PAGING) && defined(__ARCH_ARM_SRC_ARM_PG_MACROS_H)
|
||||||
|
# error "pg_macros.h must be included AFTER this header file"
|
||||||
|
# endif
|
||||||
|
|
||||||
|
|
||||||
|
/* We must declare the page table in ISRAM0 or 1. We decide depending upon
|
||||||
|
* where the vector table was place.
|
||||||
|
*/
|
||||||
|
|
||||||
|
# ifdef CONFIG_ARCH_LOWVECTORS /* Vectors located at 0x0000:0000 */
|
||||||
|
|
||||||
|
/* In this case, ISRAM0 will be shadowed at address 0x0000:0000. The page
|
||||||
|
* table must lie at the top 16Kb of ISRAM1 (or ISRAM0 if this is a LPC3130)
|
||||||
|
*/
|
||||||
|
|
||||||
|
# if CONFIG_ARCH_CHIP_LPC3131
|
||||||
|
# define PGTABLE_BASE_PADDR (LPC31_INTSRAM1_PADDR+LPC31_INTSRAM1_SIZE-PGTABLE_SIZE)
|
||||||
|
# define PGTABLE_BASE_VADDR (LPC31_INTSRAM1_VADDR+LPC31_INTSRAM1_SIZE-PGTABLE_SIZE)
|
||||||
|
# else
|
||||||
|
# define PGTABLE_BASE_PADDR (LPC31_INTSRAM0_PADDR+LPC31_INTSRAM0_SIZE-PGTABLE_SIZE)
|
||||||
|
# define PGTABLE_BASE_VADDR (LPC31_INTSRAM0_VADDR+LPC31_INTSRAM0_SIZE-PGTABLE_SIZE)
|
||||||
|
# endif
|
||||||
|
# define PGTABLE_IN_HIGHSRAM 1
|
||||||
|
|
||||||
|
/* If CONFIG_PAGING is defined, insist that pg_macros.h assign the virtual
|
||||||
|
* address of the page table.
|
||||||
|
*/
|
||||||
|
|
||||||
|
# ifdef CONFIG_PAGING
|
||||||
|
# undef PGTABLE_BASE_VADDR
|
||||||
|
# endif
|
||||||
|
# else
|
||||||
|
|
||||||
|
/* Otherwise, ISRAM1 (or ISRAM0 for the LPC3130) will be mapped so that
|
||||||
|
* the end of the SRAM region will provide memory for the vectors. The page
|
||||||
|
* table will then be places at the first 16Kb of ISRAM0 (which will be in
|
||||||
|
* the shadow memory region.
|
||||||
|
*/
|
||||||
|
|
||||||
|
# define PGTABLE_BASE_PADDR LPC31_SHADOWSPACE_PSECTION
|
||||||
|
# define PGTABLE_BASE_VADDR LPC31_SHADOWSPACE_VSECTION
|
||||||
|
# define PGTABLE_IN_LOWSRAM 1
|
||||||
|
# endif
|
||||||
|
# endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Page table start addresses:
|
||||||
|
*
|
||||||
|
* 16Kb of memory is reserved hold the page table for the virtual mappings. A
|
||||||
|
* portion of this table is not accessible in the virtual address space (for
|
||||||
|
* normal operation). We will reuse this memory for coarse page tables as follows:
|
||||||
|
*
|
||||||
|
* NOTE: If CONFIG_PAGING is defined, pg_macros.h will re-assign the virtual
|
||||||
|
* address of the page table.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define PGTABLE_L2_COARSE_OFFSET ((((LPC31_LAST_PSECTION >> 20) + 255) & ~255) << 2)
|
||||||
|
#define PGTABLE_L2_COARSE_PBASE (PGTABLE_BASE_PADDR+PGTABLE_L2_COARSE_OFFSET)
|
||||||
|
#define PGTABLE_L2_COARSE_VBASE (PGTABLE_BASE_VADDR+PGTABLE_L2_COARSE_OFFSET)
|
||||||
|
|
||||||
|
#define PGTABLE_L2_FINE_OFFSET ((((LPC31_LAST_PSECTION >> 20) + 1023) & ~1023) << 2)
|
||||||
|
#define PGTABLE_L2_FINE_PBASE (PGTABLE_BASE_PADDR+PGTABLE_L2_FINE_OFFSET)
|
||||||
|
#define PGTABLE_L2_FINE_VBASE (PGTABLE_BASE_VADDR+PGTABLE_L2_FINE_OFFSET)
|
||||||
|
|
||||||
|
/* Page table end addresses: */
|
||||||
|
|
||||||
|
#define PGTABLE_L2_END_PADDR (PGTABLE_BASE_PADDR+PGTABLE_SIZE)
|
||||||
|
#define PGTABLE_L2_END_VADDR (PGTABLE_BASE_VADDR+PGTABLE_SIZE)
|
||||||
|
|
||||||
|
/* Page table sizes */
|
||||||
|
|
||||||
|
#define PGTABLE_L2_COARSE_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_COARSE_VBASE)
|
||||||
|
#define PGTABLE_COARSE_TABLE_SIZE (4*256)
|
||||||
|
#define PGTABLE_NCOARSE_TABLES (PGTABLE_L2_COARSE_ALLOC / PGTABLE_COARSE_TABLE_SIZE)
|
||||||
|
|
||||||
|
#define PGTABLE_L2_FINE_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_FINE_VBASE)
|
||||||
|
#define PGTABLE_FINE_TABLE_SIZE (4*1024)
|
||||||
|
#define PGTABLE_NFINE_TABLES (PGTABLE_L2_FINE_ALLOC / PGTABLE_FINE_TABLE_SIZE)
|
||||||
|
|
||||||
|
/* Determine the base address of the vector table:
|
||||||
|
*
|
||||||
|
* LPC31_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM
|
||||||
|
* LPC31_VECTOR_VSRAM - Virtual address of vector table in SRAM
|
||||||
|
* LPC31_VECTOR_VADDR - Virtual address of vector table (0x00000000 or 0xffff0000)
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define VECTOR_TABLE_SIZE 0x00010000
|
||||||
|
#ifdef CONFIG_ARCH_LOWVECTORS /* Vectors located at 0x0000:0000 */
|
||||||
|
# define LPC31_VECTOR_PADDR LPC31_INTSRAM0_PADDR
|
||||||
|
# define LPC31_VECTOR_VSRAM LPC31_INTSRAM0_VADDR
|
||||||
|
# define LPC31_VECTOR_VADDR 0x00000000
|
||||||
|
# define LPC31_VECTOR_VCOARSE 0x00000000
|
||||||
|
#else /* Vectors located at 0xffff:0000 -- this probably does not work */
|
||||||
|
# if CONFIG_ARCH_CHIP_LPC3131
|
||||||
|
# define LPC31_VECTOR_PADDR (LPC31_INTSRAM1_PADDR+LPC31_INTSRAM1_SIZE-VECTOR_TABLE_SIZE)
|
||||||
|
# define LPC31_VECTOR_VSRAM (LPC31_INTSRAM1_VADDR+LPC31_INTSRAM1_SIZE-VECTOR_TABLE_SIZE)
|
||||||
|
# else
|
||||||
|
# define LPC31_VECTOR_PADDR (LPC31_INTSRAM0_PADDR+LPC31_INTSRAM0_SIZE-VECTOR_TABLE_SIZE)
|
||||||
|
# define LPC31_VECTOR_VSRAM (LPC31_INTSRAM0_VADDR+LPC31_INTSRAM0_SIZE-VECTOR_TABLE_SIZE)
|
||||||
|
# endif
|
||||||
|
# define LPC31_VECTOR_VADDR 0xffff0000
|
||||||
|
# define LPC31_VECTOR_VCOARSE 0xfff00000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Public Types
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Public Data
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
/************************************************************************************
|
||||||
|
* Public Functions
|
||||||
|
************************************************************************************/
|
||||||
|
|
||||||
|
#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_MEMORYMAP_H */
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_mpmc.h
|
* arch/arm/src/lpc31xx/lpc31_mpmc.h
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -33,15 +33,15 @@
|
|||||||
*
|
*
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#ifndef __ARCH_ARM_SRC_LPC313X_MPMC_H
|
#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_MPMC_H
|
||||||
#define __ARCH_ARM_SRC_LPC313X_MPMC_H
|
#define __ARCH_ARM_SRC_LPC31XX_LPC31_MPMC_H
|
||||||
|
|
||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* Included Files
|
* Included Files
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#include <nuttx/config.h>
|
#include <nuttx/config.h>
|
||||||
#include "lpc313x_memorymap.h"
|
#include "lpc31_memorymap.h"
|
||||||
|
|
||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -49,84 +49,84 @@
|
|||||||
|
|
||||||
/* MPMC register base address offset into the MPMC domain ***************************************/
|
/* MPMC register base address offset into the MPMC domain ***************************************/
|
||||||
|
|
||||||
#define LPC313X_MPMC_VBASE (LPC313X_MPMC_VADDR)
|
#define LPC31_MPMC_VBASE (LPC31_MPMC_VADDR)
|
||||||
#define LPC313X_MPMC_PBASE (LPC313X_MPMC_PADDR)
|
#define LPC31_MPMC_PBASE (LPC31_MPMC_PADDR)
|
||||||
|
|
||||||
/* MPMC register offsets (with respect to the base of the MPMC domain) **************************/
|
/* MPMC register offsets (with respect to the base of the MPMC domain) **************************/
|
||||||
|
|
||||||
#define LPC313X_MPMC_CONTROL_OFFSET 0x000 /* Control Register */
|
#define LPC31_MPMC_CONTROL_OFFSET 0x000 /* Control Register */
|
||||||
#define LPC313X_MPMC_STATUS_OFFSET 0x004 /* Status Register */
|
#define LPC31_MPMC_STATUS_OFFSET 0x004 /* Status Register */
|
||||||
#define LPC313X_MPMC_CONFIG_OFFSET 0x008 /* Configuration register */
|
#define LPC31_MPMC_CONFIG_OFFSET 0x008 /* Configuration register */
|
||||||
#define LPC313X_MPMC_DYNCONTROL_OFFSET 0x020 /* Dynamic Memory Control Register */
|
#define LPC31_MPMC_DYNCONTROL_OFFSET 0x020 /* Dynamic Memory Control Register */
|
||||||
#define LPC313X_MPMC_DYNREFRESH_OFFSET 0x024 /* Dynamic Memory Refresh Timer Register */
|
#define LPC31_MPMC_DYNREFRESH_OFFSET 0x024 /* Dynamic Memory Refresh Timer Register */
|
||||||
#define LPC313X_MPMC_DYNREADCONFIG_OFFSET 0x028 /* Dynamic Memory Read Configuration Register */
|
#define LPC31_MPMC_DYNREADCONFIG_OFFSET 0x028 /* Dynamic Memory Read Configuration Register */
|
||||||
#define LPC313X_MPMC_DYNTRP_OFFSET 0x030 /* Dynamic Memory Precharge Command Period Register */
|
#define LPC31_MPMC_DYNTRP_OFFSET 0x030 /* Dynamic Memory Precharge Command Period Register */
|
||||||
#define LPC313X_MPMC_DYNTRAS_OFFSET 0x034 /* Dynamic Memory Active To Precharge Command Period Register */
|
#define LPC31_MPMC_DYNTRAS_OFFSET 0x034 /* Dynamic Memory Active To Precharge Command Period Register */
|
||||||
#define LPC313X_MPMC_DYNTSREX_OFFSET 0x038 /* Dynamic Memory Self-refresh Exit Time Register */
|
#define LPC31_MPMC_DYNTSREX_OFFSET 0x038 /* Dynamic Memory Self-refresh Exit Time Register */
|
||||||
#define LPC313X_MPMC_DYNTAPR_OFFSET 0x03c /* Dynamic Memory Last Data Out To Active Time Register */
|
#define LPC31_MPMC_DYNTAPR_OFFSET 0x03c /* Dynamic Memory Last Data Out To Active Time Register */
|
||||||
#define LPC313X_MPMC_DYNTDAL_OFFSET 0x040 /* Dynamic Memory Data-in To Active Command Time Register */
|
#define LPC31_MPMC_DYNTDAL_OFFSET 0x040 /* Dynamic Memory Data-in To Active Command Time Register */
|
||||||
#define LPC313X_MPMC_DYNTWR_OFFSET 0x044 /* Dynamic Memory Write Recovery Time Register */
|
#define LPC31_MPMC_DYNTWR_OFFSET 0x044 /* Dynamic Memory Write Recovery Time Register */
|
||||||
#define LPC313X_MPMC_DYNTRC_OFFSET 0x048 /* Dynamic Memory Active To Active Command Period Register */
|
#define LPC31_MPMC_DYNTRC_OFFSET 0x048 /* Dynamic Memory Active To Active Command Period Register */
|
||||||
#define LPC313X_MPMC_DYNTRFC_OFFSET 0x04c /* Dynamic Memory Auto-refresh Period Register */
|
#define LPC31_MPMC_DYNTRFC_OFFSET 0x04c /* Dynamic Memory Auto-refresh Period Register */
|
||||||
#define LPC313X_MPMC_DYNTXSR_OFFSET 0x050 /* Dynamic Memory Exit Self-refresh Register */
|
#define LPC31_MPMC_DYNTXSR_OFFSET 0x050 /* Dynamic Memory Exit Self-refresh Register */
|
||||||
#define LPC313X_MPMC_DYNTRRD_OFFSET 0x054 /* Dynamic Memory Active Bank A to Active Bank B Time Register */
|
#define LPC31_MPMC_DYNTRRD_OFFSET 0x054 /* Dynamic Memory Active Bank A to Active Bank B Time Register */
|
||||||
#define LPC313X_MPMC_DYNTMRD_OFFSET 0x058 /* Dynamic Memory Load Mode Register To Active Command Time Register */
|
#define LPC31_MPMC_DYNTMRD_OFFSET 0x058 /* Dynamic Memory Load Mode Register To Active Command Time Register */
|
||||||
#define LPC313X_MPMC_STEXTWAIT_OFFSET 0x080 /* Static Memory Extended Wait Register */
|
#define LPC31_MPMC_STEXTWAIT_OFFSET 0x080 /* Static Memory Extended Wait Register */
|
||||||
#define LPC313X_MPMC_DYNCONFIG0_OFFSET 0x100 /* Dynamic Memory Configuration Registers 0 */
|
#define LPC31_MPMC_DYNCONFIG0_OFFSET 0x100 /* Dynamic Memory Configuration Registers 0 */
|
||||||
#define LPC313X_MPMC_DYNRASCAS0_OFFSET 0x104 /* Dynamic Memory RAS and CAS Delay Registers 0 */
|
#define LPC31_MPMC_DYNRASCAS0_OFFSET 0x104 /* Dynamic Memory RAS and CAS Delay Registers 0 */
|
||||||
/* 0x120-0x164: reserved */
|
/* 0x120-0x164: reserved */
|
||||||
#define LPC313X_MPMC_STCONFIG0_OFFSET 0x200 /* Static Memory Configuration Registers 0 */
|
#define LPC31_MPMC_STCONFIG0_OFFSET 0x200 /* Static Memory Configuration Registers 0 */
|
||||||
#define LPC313X_MPMC_STWAITWEN0_OFFSET 0x204 /* Static Memory Write Enable Delay Registers 0 */
|
#define LPC31_MPMC_STWAITWEN0_OFFSET 0x204 /* Static Memory Write Enable Delay Registers 0 */
|
||||||
#define LPC313X_MPMC_STWAITOEN0_OFFSET 0x208 /* Static Memory Output Enable Delay Registers 0 */
|
#define LPC31_MPMC_STWAITOEN0_OFFSET 0x208 /* Static Memory Output Enable Delay Registers 0 */
|
||||||
#define LPC313X_MPMC_STWAITRD0_OFFSET 0x20c /* Static Memory Read Delay Registers 0 */
|
#define LPC31_MPMC_STWAITRD0_OFFSET 0x20c /* Static Memory Read Delay Registers 0 */
|
||||||
#define LPC313X_MPMC_STWAITPAGE0_OFFSET 0x210 /* Static Memory Page Mode Read Delay Registers 0 */
|
#define LPC31_MPMC_STWAITPAGE0_OFFSET 0x210 /* Static Memory Page Mode Read Delay Registers 0 */
|
||||||
#define LPC313X_MPMC_STWAITWR0_OFFSET 0x214 /* Static Memory Write Delay Registers 0 */
|
#define LPC31_MPMC_STWAITWR0_OFFSET 0x214 /* Static Memory Write Delay Registers 0 */
|
||||||
#define LPC313X_MPMC_STWAITTURN0_OFFSET 0x218 /* Static Memory Turn Round Delay Registers 0 */
|
#define LPC31_MPMC_STWAITTURN0_OFFSET 0x218 /* Static Memory Turn Round Delay Registers 0 */
|
||||||
#define LPC313X_MPMC_STCONFIG1_OFFSET 0x220 /* tatic Memory Configuration Registers 1 */
|
#define LPC31_MPMC_STCONFIG1_OFFSET 0x220 /* tatic Memory Configuration Registers 1 */
|
||||||
#define LPC313X_MPMC_STWAITWEN1_OFFSET 0x224 /* Static Memory Write Enable Delay Registers 1 */
|
#define LPC31_MPMC_STWAITWEN1_OFFSET 0x224 /* Static Memory Write Enable Delay Registers 1 */
|
||||||
#define LPC313X_MPMC_STWAITOEN1_OFFSET 0x228 /* Static Memory Output Enable Delay Registers 1 */
|
#define LPC31_MPMC_STWAITOEN1_OFFSET 0x228 /* Static Memory Output Enable Delay Registers 1 */
|
||||||
#define LPC313X_MPMC_STWAITRD1_OFFSET 0x22c /* Static Memory Read Delay Registers 1 */
|
#define LPC31_MPMC_STWAITRD1_OFFSET 0x22c /* Static Memory Read Delay Registers 1 */
|
||||||
#define LPC313X_MPMC_STWAITPAGE1_OFFSET 0x230 /* Static Memory Page Mode Read Delay Registers 1 */
|
#define LPC31_MPMC_STWAITPAGE1_OFFSET 0x230 /* Static Memory Page Mode Read Delay Registers 1 */
|
||||||
#define LPC313X_MPMC_STWAITWR1_OFFSET 0x234 /* Static Memory Write Delay Registers 1 */
|
#define LPC31_MPMC_STWAITWR1_OFFSET 0x234 /* Static Memory Write Delay Registers 1 */
|
||||||
#define LPC313X_MPMC_STWAITTURN1_OFFSET 0x238 /* Static Memory Turn Round Delay Registers 1 */
|
#define LPC31_MPMC_STWAITTURN1_OFFSET 0x238 /* Static Memory Turn Round Delay Registers 1 */
|
||||||
/* 0x240-0x278: Reserverd */
|
/* 0x240-0x278: Reserverd */
|
||||||
|
|
||||||
/* MPMC register (virtual) addresses ************************************************************/
|
/* MPMC register (virtual) addresses ************************************************************/
|
||||||
|
|
||||||
#define LPC313X_MPMC_CONTROL (LPC313X_MPMC_VBASE+LPC313X_MPMC_CONTROL_OFFSET)
|
#define LPC31_MPMC_CONTROL (LPC31_MPMC_VBASE+LPC31_MPMC_CONTROL_OFFSET)
|
||||||
#define LPC313X_MPMC_STATUS (LPC313X_MPMC_VBASE+LPC313X_MPMC_STATUS_OFFSET)
|
#define LPC31_MPMC_STATUS (LPC31_MPMC_VBASE+LPC31_MPMC_STATUS_OFFSET)
|
||||||
#define LPC313X_MPMC_CONFIG (LPC313X_MPMC_VBASE+LPC313X_MPMC_CONFIG_OFFSET)
|
#define LPC31_MPMC_CONFIG (LPC31_MPMC_VBASE+LPC31_MPMC_CONFIG_OFFSET)
|
||||||
#define LPC313X_MPMC_DYNCONTROL (LPC313X_MPMC_VBASE+LPC313X_MPMC_DYNCONTROL_OFFSET)
|
#define LPC31_MPMC_DYNCONTROL (LPC31_MPMC_VBASE+LPC31_MPMC_DYNCONTROL_OFFSET)
|
||||||
#define LPC313X_MPMC_DYNREFRESH (LPC313X_MPMC_VBASE+LPC313X_MPMC_DYNREFRESH_OFFSET)
|
#define LPC31_MPMC_DYNREFRESH (LPC31_MPMC_VBASE+LPC31_MPMC_DYNREFRESH_OFFSET)
|
||||||
#define LPC313X_MPMC_DYNREADCONFIG (LPC313X_MPMC_VBASE+LPC313X_MPMC_DYNREADCONFIG_OFFSET)
|
#define LPC31_MPMC_DYNREADCONFIG (LPC31_MPMC_VBASE+LPC31_MPMC_DYNREADCONFIG_OFFSET)
|
||||||
#define LPC313X_MPMC_DYNTRP (LPC313X_MPMC_VBASE+LPC313X_MPMC_DYNTRP_OFFSET)
|
#define LPC31_MPMC_DYNTRP (LPC31_MPMC_VBASE+LPC31_MPMC_DYNTRP_OFFSET)
|
||||||
#define LPC313X_MPMC_DYNTRAS (LPC313X_MPMC_VBASE+LPC313X_MPMC_DYNTRAS_OFFSET)
|
#define LPC31_MPMC_DYNTRAS (LPC31_MPMC_VBASE+LPC31_MPMC_DYNTRAS_OFFSET)
|
||||||
#define LPC313X_MPMC_DYNTSREX (LPC313X_MPMC_VBASE+LPC313X_MPMC_DYNTSREX_OFFSET)
|
#define LPC31_MPMC_DYNTSREX (LPC31_MPMC_VBASE+LPC31_MPMC_DYNTSREX_OFFSET)
|
||||||
#define LPC313X_MPMC_DYNTAPR (LPC313X_MPMC_VBASE+LPC313X_MPMC_DYNTAPR_OFFSET)
|
#define LPC31_MPMC_DYNTAPR (LPC31_MPMC_VBASE+LPC31_MPMC_DYNTAPR_OFFSET)
|
||||||
#define LPC313X_MPMC_DYNTDAL (LPC313X_MPMC_VBASE+LPC313X_MPMC_DYNTDAL_OFFSET)
|
#define LPC31_MPMC_DYNTDAL (LPC31_MPMC_VBASE+LPC31_MPMC_DYNTDAL_OFFSET)
|
||||||
#define LPC313X_MPMC_DYNTWR (LPC313X_MPMC_VBASE+LPC313X_MPMC_DYNTWR_OFFSET)
|
#define LPC31_MPMC_DYNTWR (LPC31_MPMC_VBASE+LPC31_MPMC_DYNTWR_OFFSET)
|
||||||
#define LPC313X_MPMC_DYNTRC (LPC313X_MPMC_VBASE+LPC313X_MPMC_DYNTRC_OFFSET)
|
#define LPC31_MPMC_DYNTRC (LPC31_MPMC_VBASE+LPC31_MPMC_DYNTRC_OFFSET)
|
||||||
#define LPC313X_MPMC_DYNTRFC (LPC313X_MPMC_VBASE+LPC313X_MPMC_DYNTRFC_OFFSET)
|
#define LPC31_MPMC_DYNTRFC (LPC31_MPMC_VBASE+LPC31_MPMC_DYNTRFC_OFFSET)
|
||||||
#define LPC313X_MPMC_DYNTXSR (LPC313X_MPMC_VBASE+LPC313X_MPMC_DYNTXSR_OFFSET)
|
#define LPC31_MPMC_DYNTXSR (LPC31_MPMC_VBASE+LPC31_MPMC_DYNTXSR_OFFSET)
|
||||||
#define LPC313X_MPMC_DYNTRRD (LPC313X_MPMC_VBASE+LPC313X_MPMC_DYNTRRD_OFFSET)
|
#define LPC31_MPMC_DYNTRRD (LPC31_MPMC_VBASE+LPC31_MPMC_DYNTRRD_OFFSET)
|
||||||
#define LPC313X_MPMC_DYNTMRD (LPC313X_MPMC_VBASE+LPC313X_MPMC_DYNTMRD_OFFSET)
|
#define LPC31_MPMC_DYNTMRD (LPC31_MPMC_VBASE+LPC31_MPMC_DYNTMRD_OFFSET)
|
||||||
#define LPC313X_MPMC_STEXTWAIT (LPC313X_MPMC_VBASE+LPC313X_MPMC_STEXTWAIT_OFFSET)
|
#define LPC31_MPMC_STEXTWAIT (LPC31_MPMC_VBASE+LPC31_MPMC_STEXTWAIT_OFFSET)
|
||||||
#define LPC313X_MPMC_DYNCONFIG0 (LPC313X_MPMC_VBASE+LPC313X_MPMC_DYNCONFIG0_OFFSET)
|
#define LPC31_MPMC_DYNCONFIG0 (LPC31_MPMC_VBASE+LPC31_MPMC_DYNCONFIG0_OFFSET)
|
||||||
#define LPC313X_MPMC_DYNRASCAS0 (LPC313X_MPMC_VBASE+LPC313X_MPMC_DYNRASCAS0_OFFSET)
|
#define LPC31_MPMC_DYNRASCAS0 (LPC31_MPMC_VBASE+LPC31_MPMC_DYNRASCAS0_OFFSET)
|
||||||
#define LPC313X_MPMC_STCONFIG0 (LPC313X_MPMC_VBASE+LPC313X_MPMC_STCONFIG0_OFFSET)
|
#define LPC31_MPMC_STCONFIG0 (LPC31_MPMC_VBASE+LPC31_MPMC_STCONFIG0_OFFSET)
|
||||||
#define LPC313X_MPMC_STWAITWEN0 (LPC313X_MPMC_VBASE+LPC313X_MPMC_STWAITWEN0_OFFSET)
|
#define LPC31_MPMC_STWAITWEN0 (LPC31_MPMC_VBASE+LPC31_MPMC_STWAITWEN0_OFFSET)
|
||||||
#define LPC313X_MPMC_STWAITOEN0 (LPC313X_MPMC_VBASE+LPC313X_MPMC_STWAITOEN0_OFFSET)
|
#define LPC31_MPMC_STWAITOEN0 (LPC31_MPMC_VBASE+LPC31_MPMC_STWAITOEN0_OFFSET)
|
||||||
#define LPC313X_MPMC_STWAITRD0 (LPC313X_MPMC_VBASE+LPC313X_MPMC_STWAITRD0_OFFSET)
|
#define LPC31_MPMC_STWAITRD0 (LPC31_MPMC_VBASE+LPC31_MPMC_STWAITRD0_OFFSET)
|
||||||
#define LPC313X_MPMC_STWAITPAGE0 (LPC313X_MPMC_VBASE+LPC313X_MPMC_STWAITPAGE0_OFFSET)
|
#define LPC31_MPMC_STWAITPAGE0 (LPC31_MPMC_VBASE+LPC31_MPMC_STWAITPAGE0_OFFSET)
|
||||||
#define LPC313X_MPMC_STWAITWR0 (LPC313X_MPMC_VBASE+LPC313X_MPMC_STWAITWR0_OFFSET)
|
#define LPC31_MPMC_STWAITWR0 (LPC31_MPMC_VBASE+LPC31_MPMC_STWAITWR0_OFFSET)
|
||||||
#define LPC313X_MPMC_STWAITTURN0 (LPC313X_MPMC_VBASE+LPC313X_MPMC_STWAITTURN0_OFFSET)
|
#define LPC31_MPMC_STWAITTURN0 (LPC31_MPMC_VBASE+LPC31_MPMC_STWAITTURN0_OFFSET)
|
||||||
#define LPC313X_MPMC_STCONFIG1 (LPC313X_MPMC_VBASE+LPC313X_MPMC_STCONFIG1_OFFSET)
|
#define LPC31_MPMC_STCONFIG1 (LPC31_MPMC_VBASE+LPC31_MPMC_STCONFIG1_OFFSET)
|
||||||
#define LPC313X_MPMC_STWAITWEN1 (LPC313X_MPMC_VBASE+LPC313X_MPMC_STWAITWEN1_OFFSET)
|
#define LPC31_MPMC_STWAITWEN1 (LPC31_MPMC_VBASE+LPC31_MPMC_STWAITWEN1_OFFSET)
|
||||||
#define LPC313X_MPMC_STWAITOEN1 (LPC313X_MPMC_VBASE+LPC313X_MPMC_STWAITOEN1_OFFSET)
|
#define LPC31_MPMC_STWAITOEN1 (LPC31_MPMC_VBASE+LPC31_MPMC_STWAITOEN1_OFFSET)
|
||||||
#define LPC313X_MPMC_STWAITRD1 (LPC313X_MPMC_VBASE+LPC313X_MPMC_STWAITRD1_OFFSET)
|
#define LPC31_MPMC_STWAITRD1 (LPC31_MPMC_VBASE+LPC31_MPMC_STWAITRD1_OFFSET)
|
||||||
#define LPC313X_MPMC_STWAITPAGE1 (LPC313X_MPMC_VBASE+LPC313X_MPMC_STWAITPAGE1_OFFSET)
|
#define LPC31_MPMC_STWAITPAGE1 (LPC31_MPMC_VBASE+LPC31_MPMC_STWAITPAGE1_OFFSET)
|
||||||
#define LPC313X_MPMC_STWAITWR1 (LPC313X_MPMC_VBASE+LPC313X_MPMC_STWAITWR1_OFFSET)
|
#define LPC31_MPMC_STWAITWR1 (LPC31_MPMC_VBASE+LPC31_MPMC_STWAITWR1_OFFSET)
|
||||||
#define LPC313X_MPMC_STWAITTURN1 (LPC313X_MPMC_VBASE+LPC313X_MPMC_STWAITTURN1_OFFSET)
|
#define LPC31_MPMC_STWAITTURN1 (LPC31_MPMC_VBASE+LPC31_MPMC_STWAITTURN1_OFFSET)
|
||||||
|
|
||||||
/* MPMC register bit definitions ****************************************************************/
|
/* MPMC register bit definitions ****************************************************************/
|
||||||
/* MPMCControl (address 0x17008000) */
|
/* MPMCControl (address 0x17008000) */
|
||||||
@@ -337,4 +337,4 @@
|
|||||||
* Public Functions
|
* Public Functions
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#endif /* __ARCH_ARM_SRC_LPC313X_MPMC_H */
|
#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_MPMC_H */
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_nand.h
|
* arch/arm/src/lpc31xx/lpc31_nand.h
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -33,15 +33,15 @@
|
|||||||
*
|
*
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#ifndef __ARCH_ARM_SRC_LPC313X_NAND_H
|
#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_NAND_H
|
||||||
#define __ARCH_ARM_SRC_LPC313X_NAND_H
|
#define __ARCH_ARM_SRC_LPC31XX_LPC31_NAND_H
|
||||||
|
|
||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* Included Files
|
* Included Files
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#include <nuttx/config.h>
|
#include <nuttx/config.h>
|
||||||
#include "lpc313x_memorymap.h"
|
#include "lpc31_memorymap.h"
|
||||||
|
|
||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -49,54 +49,54 @@
|
|||||||
|
|
||||||
/* NAND FLASH controller register base address offset into the APB4 domain **********************/
|
/* NAND FLASH controller register base address offset into the APB4 domain **********************/
|
||||||
|
|
||||||
#define LPC313X_NAND_VBASE (LPC313X_APB4_VADDR+LPC313X_APB4_NAND_OFFSET)
|
#define LPC31_NAND_VBASE (LPC31_APB4_VADDR+LPC31_APB4_NAND_OFFSET)
|
||||||
#define LPC313X_NAND_PBASE (LPC313X_APB4_PADDR+LPC313X_APB4_NAND_OFFSET)
|
#define LPC31_NAND_PBASE (LPC31_APB4_PADDR+LPC31_APB4_NAND_OFFSET)
|
||||||
|
|
||||||
/* NAND FLASH controller register offsets (with respect to the base of the APB4 domain) *********/
|
/* NAND FLASH controller register offsets (with respect to the base of the APB4 domain) *********/
|
||||||
|
|
||||||
#define LPC313X_NAND_IRQSTATUS1_OFFSET 0x00 /* Interrrupt status register (first 32-bits) */
|
#define LPC31_NAND_IRQSTATUS1_OFFSET 0x00 /* Interrrupt status register (first 32-bits) */
|
||||||
#define LPC313X_NAND_IRQMASK1_OFFSET 0x04 /* Interrupt mask register (first 32-bits) */
|
#define LPC31_NAND_IRQMASK1_OFFSET 0x04 /* Interrupt mask register (first 32-bits) */
|
||||||
#define LPC313X_NAND_IRQSTATUSRAW1_OFFSET 0x08 /* Unmasked register status (first 32-bits) */
|
#define LPC31_NAND_IRQSTATUSRAW1_OFFSET 0x08 /* Unmasked register status (first 32-bits) */
|
||||||
#define LPC313X_NAND_CONFIG_OFFSET 0x0c /* NAND Flash controller configuration register */
|
#define LPC31_NAND_CONFIG_OFFSET 0x0c /* NAND Flash controller configuration register */
|
||||||
#define LPC313X_NAND_IOCONFIG_OFFSET 0x10 /* Default value settings for IO signals */
|
#define LPC31_NAND_IOCONFIG_OFFSET 0x10 /* Default value settings for IO signals */
|
||||||
#define LPC313X_NAND_TIMING1_OFFSET 0x14 /* First NAND FLASH controller timing register */
|
#define LPC31_NAND_TIMING1_OFFSET 0x14 /* First NAND FLASH controller timing register */
|
||||||
#define LPC313X_NAND_TIMING2_OFFSET 0x18 /* Second NAND FLASH controller timing register */
|
#define LPC31_NAND_TIMING2_OFFSET 0x18 /* Second NAND FLASH controller timing register */
|
||||||
#define LPC313X_NAND_SETCMD_OFFSET 0x20 /* NAND FLASH device command register */
|
#define LPC31_NAND_SETCMD_OFFSET 0x20 /* NAND FLASH device command register */
|
||||||
#define LPC313X_NAND_SETADDR_OFFSET 0x24 /* NAND FLASH device address register */
|
#define LPC31_NAND_SETADDR_OFFSET 0x24 /* NAND FLASH device address register */
|
||||||
#define LPC313X_NAND_WRITEDATA_OFFSET 0x28 /* NAND FLASH device write data register */
|
#define LPC31_NAND_WRITEDATA_OFFSET 0x28 /* NAND FLASH device write data register */
|
||||||
#define LPC313X_NAND_SETCE_OFFSET 0x2c /* Set all CE and WP_n signals */
|
#define LPC31_NAND_SETCE_OFFSET 0x2c /* Set all CE and WP_n signals */
|
||||||
#define LPC313X_NAND_READDATA_OFFSET 0x30 /* NAND FLASH device read data register */
|
#define LPC31_NAND_READDATA_OFFSET 0x30 /* NAND FLASH device read data register */
|
||||||
#define LPC313X_NAND_CHECKSTS_OFFSET 0x34 /* Check status of interrupts */
|
#define LPC31_NAND_CHECKSTS_OFFSET 0x34 /* Check status of interrupts */
|
||||||
#define LPC313X_NAND_CONTROLFLOW_OFFSET 0x38 /* Commands to read and write pages */
|
#define LPC31_NAND_CONTROLFLOW_OFFSET 0x38 /* Commands to read and write pages */
|
||||||
#define LPC313X_NAND_GPIO1_OFFSET 0x40 /* Program IO pins that can be used as GPIO */
|
#define LPC31_NAND_GPIO1_OFFSET 0x40 /* Program IO pins that can be used as GPIO */
|
||||||
#define LPC313X_NAND_GPIO2_OFFSET 0x44 /* Program IO pins that can be used as GPIO */
|
#define LPC31_NAND_GPIO2_OFFSET 0x44 /* Program IO pins that can be used as GPIO */
|
||||||
#define LPC313X_NAND_IRQSTATUS2_OFFSET 0x48 /* Interrrupt status register (second 32-bits) */
|
#define LPC31_NAND_IRQSTATUS2_OFFSET 0x48 /* Interrrupt status register (second 32-bits) */
|
||||||
#define LPC313X_NAND_IRQMASK3_OFFSET 0x4c /* Interrupt mask register (second 32-bits) */
|
#define LPC31_NAND_IRQMASK3_OFFSET 0x4c /* Interrupt mask register (second 32-bits) */
|
||||||
#define LPC313X_NAND_IRQSTATUSRAW2_OFFSET 0x50 /* Unmasked register status (second 32-bits) */
|
#define LPC31_NAND_IRQSTATUSRAW2_OFFSET 0x50 /* Unmasked register status (second 32-bits) */
|
||||||
#define LPC313X_NAND_ECCERRSTATUS_OFFSET 0x78 /* ECC error status register */
|
#define LPC31_NAND_ECCERRSTATUS_OFFSET 0x78 /* ECC error status register */
|
||||||
|
|
||||||
/* NAND FLASH controller register (virtual) addresses *******************************************/
|
/* NAND FLASH controller register (virtual) addresses *******************************************/
|
||||||
|
|
||||||
#define LPC313X_NAND_IRQSTATUS1 (LPC313X_NAND_VBASE+LPC313X_NAND_IRQSTATUS1_OFFSET)
|
#define LPC31_NAND_IRQSTATUS1 (LPC31_NAND_VBASE+LPC31_NAND_IRQSTATUS1_OFFSET)
|
||||||
#define LPC313X_NAND_IRQMASK1 (LPC313X_NAND_VBASE+LPC313X_NAND_IRQMASK1_OFFSET)
|
#define LPC31_NAND_IRQMASK1 (LPC31_NAND_VBASE+LPC31_NAND_IRQMASK1_OFFSET)
|
||||||
#define LPC313X_NAND_IRQSTATUSRAW1 (LPC313X_NAND_VBASE+LPC313X_NAND_IRQSTATUSRAW1_OFFSET)
|
#define LPC31_NAND_IRQSTATUSRAW1 (LPC31_NAND_VBASE+LPC31_NAND_IRQSTATUSRAW1_OFFSET)
|
||||||
#define LPC313X_NAND_CONFIG (LPC313X_NAND_VBASE+LPC313X_NAND_CONFIG_OFFSET)
|
#define LPC31_NAND_CONFIG (LPC31_NAND_VBASE+LPC31_NAND_CONFIG_OFFSET)
|
||||||
#define LPC313X_NAND_IOCONFIG (LPC313X_NAND_VBASE+LPC313X_NAND_IOCONFIG_OFFSET)
|
#define LPC31_NAND_IOCONFIG (LPC31_NAND_VBASE+LPC31_NAND_IOCONFIG_OFFSET)
|
||||||
#define LPC313X_NAND_TIMING1 (LPC313X_NAND_VBASE+LPC313X_NAND_TIMING1_OFFSET)
|
#define LPC31_NAND_TIMING1 (LPC31_NAND_VBASE+LPC31_NAND_TIMING1_OFFSET)
|
||||||
#define LPC313X_NAND_TIMING2 (LPC313X_NAND_VBASE+LPC313X_NAND_TIMING2_OFFSET)
|
#define LPC31_NAND_TIMING2 (LPC31_NAND_VBASE+LPC31_NAND_TIMING2_OFFSET)
|
||||||
#define LPC313X_NAND_SETCMD (LPC313X_NAND_VBASE+LPC313X_NAND_SETCMD_OFFSET)
|
#define LPC31_NAND_SETCMD (LPC31_NAND_VBASE+LPC31_NAND_SETCMD_OFFSET)
|
||||||
#define LPC313X_NAND_SETADDR (LPC313X_NAND_VBASE+LPC313X_NAND_SETADDR_OFFSET)
|
#define LPC31_NAND_SETADDR (LPC31_NAND_VBASE+LPC31_NAND_SETADDR_OFFSET)
|
||||||
#define LPC313X_NAND_WRITEDATA (LPC313X_NAND_VBASE+LPC313X_NAND_WRITEDATA_OFFSET)
|
#define LPC31_NAND_WRITEDATA (LPC31_NAND_VBASE+LPC31_NAND_WRITEDATA_OFFSET)
|
||||||
#define LPC313X_NAND_SETCE (LPC313X_NAND_VBASE+LPC313X_NAND_SETCE_OFFSET)
|
#define LPC31_NAND_SETCE (LPC31_NAND_VBASE+LPC31_NAND_SETCE_OFFSET)
|
||||||
#define LPC313X_NAND_READDATA (LPC313X_NAND_VBASE+LPC313X_NAND_READDATA_OFFSET)
|
#define LPC31_NAND_READDATA (LPC31_NAND_VBASE+LPC31_NAND_READDATA_OFFSET)
|
||||||
#define LPC313X_NAND_CHECKSTS (LPC313X_NAND_VBASE+LPC313X_NAND_CHECKSTS_OFFSET)
|
#define LPC31_NAND_CHECKSTS (LPC31_NAND_VBASE+LPC31_NAND_CHECKSTS_OFFSET)
|
||||||
#define LPC313X_NAND_CONTROLFLOW (LPC313X_NAND_VBASE+LPC313X_NAND_CONTROLFLOW_OFFSET)
|
#define LPC31_NAND_CONTROLFLOW (LPC31_NAND_VBASE+LPC31_NAND_CONTROLFLOW_OFFSET)
|
||||||
#define LPC313X_NAND_GPIO1 (LPC313X_NAND_VBASE+LPC313X_NAND_GPIO1_OFFSET)
|
#define LPC31_NAND_GPIO1 (LPC31_NAND_VBASE+LPC31_NAND_GPIO1_OFFSET)
|
||||||
#define LPC313X_NAND_GPIO2 (LPC313X_NAND_VBASE+LPC313X_NAND_GPIO2_OFFSET)
|
#define LPC31_NAND_GPIO2 (LPC31_NAND_VBASE+LPC31_NAND_GPIO2_OFFSET)
|
||||||
#define LPC313X_NAND_IRQSTATUS2 (LPC313X_NAND_VBASE+LPC313X_NAND_IRQSTATUS2_OFFSET)
|
#define LPC31_NAND_IRQSTATUS2 (LPC31_NAND_VBASE+LPC31_NAND_IRQSTATUS2_OFFSET)
|
||||||
#define LPC313X_NAND_IRQMASK3 (LPC313X_NAND_VBASE+LPC313X_NAND_IRQMASK3_OFFSET)
|
#define LPC31_NAND_IRQMASK3 (LPC31_NAND_VBASE+LPC31_NAND_IRQMASK3_OFFSET)
|
||||||
#define LPC313X_NAND_IRQSTATUSRAW2 (LPC313X_NAND_VBASE+LPC313X_NAND_IRQSTATUSRAW2_OFFSET)
|
#define LPC31_NAND_IRQSTATUSRAW2 (LPC31_NAND_VBASE+LPC31_NAND_IRQSTATUSRAW2_OFFSET)
|
||||||
#define LPC313X_NAND_ECCERRSTATUS (LPC313X_NAND_VBASE+LPC313X_NAND_ECCERRSTATUS_OFFSET)
|
#define LPC31_NAND_ECCERRSTATUS (LPC31_NAND_VBASE+LPC31_NAND_ECCERRSTATUS_OFFSET)
|
||||||
|
|
||||||
/* NAND FLASH controller register bit definitions ***********************************************/
|
/* NAND FLASH controller register bit definitions ***********************************************/
|
||||||
/* NandIRQStatus1 register description (NandIRQStatus1, address 0x17000800) */
|
/* NandIRQStatus1 register description (NandIRQStatus1, address 0x17000800) */
|
||||||
@@ -375,4 +375,4 @@
|
|||||||
* Public Functions
|
* Public Functions
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#endif /* __ARCH_ARM_SRC_LPC313X_NAND_H */
|
#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_NAND_H */
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_pcm.h
|
* arch/arm/src/lpc31xx/lpc31_pcm.h
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -33,15 +33,15 @@
|
|||||||
*
|
*
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#ifndef __ARCH_ARM_SRC_LPC313X_PCM_H
|
#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_PCM_H
|
||||||
#define __ARCH_ARM_SRC_LPC313X_PCM_H
|
#define __ARCH_ARM_SRC_LPC31XX_LPC31_PCM_H
|
||||||
|
|
||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* Included Files
|
* Included Files
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#include <nuttx/config.h>
|
#include <nuttx/config.h>
|
||||||
#include "lpc313x_memorymap.h"
|
#include "lpc31_memorymap.h"
|
||||||
|
|
||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -49,50 +49,50 @@
|
|||||||
|
|
||||||
/* PCM register base address offset into the APB2 domain ****************************************/
|
/* PCM register base address offset into the APB2 domain ****************************************/
|
||||||
|
|
||||||
#define LPC313X_PCM_VBASE (LPC313X_APB2_VSECTION+LPC313X_APB2_PCM_OFFSET)
|
#define LPC31_PCM_VBASE (LPC31_APB2_VSECTION+LPC31_APB2_PCM_OFFSET)
|
||||||
#define LPC313X_PCM_PBASE (LPC313X_APB2_PSECTION+LPC313X_APB2_PCM_OFFSET)
|
#define LPC31_PCM_PBASE (LPC31_APB2_PSECTION+LPC31_APB2_PCM_OFFSET)
|
||||||
|
|
||||||
/* PCM register offsets (with respect to the PCM base) ******************************************/
|
/* PCM register offsets (with respect to the PCM base) ******************************************/
|
||||||
|
|
||||||
#define LPC313X_PCM_GLOBAL_OFFSET 0x000 /* Global register */
|
#define LPC31_PCM_GLOBAL_OFFSET 0x000 /* Global register */
|
||||||
#define LPC313X_PCM_CNTL0_OFFSET 0x004 /* Control register 0 */
|
#define LPC31_PCM_CNTL0_OFFSET 0x004 /* Control register 0 */
|
||||||
#define LPC313X_PCM_CNTL1_OFFSET 0x008 /* Control register 1 */
|
#define LPC31_PCM_CNTL1_OFFSET 0x008 /* Control register 1 */
|
||||||
#define LPC313X_PCM_HPOUT_OFFSET(n) (0x00c+((n)<<2)) /* Transmit data register n */
|
#define LPC31_PCM_HPOUT_OFFSET(n) (0x00c+((n)<<2)) /* Transmit data register n */
|
||||||
#define LPC313X_PCM_HPOUT0_OFFSET 0x00c /* Transmit data register 0 */
|
#define LPC31_PCM_HPOUT0_OFFSET 0x00c /* Transmit data register 0 */
|
||||||
#define LPC313X_PCM_HPOUT1_OFFSET 0x010 /* Transmit data register 1 */
|
#define LPC31_PCM_HPOUT1_OFFSET 0x010 /* Transmit data register 1 */
|
||||||
#define LPC313X_PCM_HPOUT2_OFFSET 0x014 /* Transmit data register 2 */
|
#define LPC31_PCM_HPOUT2_OFFSET 0x014 /* Transmit data register 2 */
|
||||||
#define LPC313X_PCM_HPOUT3_OFFSET 0x018 /* Transmit data register 3 */
|
#define LPC31_PCM_HPOUT3_OFFSET 0x018 /* Transmit data register 3 */
|
||||||
#define LPC313X_PCM_HPOUT4_OFFSET 0x01c /* Transmit data register 4 */
|
#define LPC31_PCM_HPOUT4_OFFSET 0x01c /* Transmit data register 4 */
|
||||||
#define LPC313X_PCM_HPOUT5_OFFSET 0x020 /* Transmit data register 5 */
|
#define LPC31_PCM_HPOUT5_OFFSET 0x020 /* Transmit data register 5 */
|
||||||
#define LPC313X_PCM_HPIN_OFFSET(n) (0x024+((n)<<2)) /* Transmit data register n */
|
#define LPC31_PCM_HPIN_OFFSET(n) (0x024+((n)<<2)) /* Transmit data register n */
|
||||||
#define LPC313X_PCM_HPIN0_OFFSET 0x024 /* Receive data register 0 */
|
#define LPC31_PCM_HPIN0_OFFSET 0x024 /* Receive data register 0 */
|
||||||
#define LPC313X_PCM_HPIN1_OFFSET 0x028 /* Receive data register 1 */
|
#define LPC31_PCM_HPIN1_OFFSET 0x028 /* Receive data register 1 */
|
||||||
#define LPC313X_PCM_HPIN2_OFFSET 0x02c /* Receive data register 2 */
|
#define LPC31_PCM_HPIN2_OFFSET 0x02c /* Receive data register 2 */
|
||||||
#define LPC313X_PCM_HPIN3_OFFSET 0x030 /* Receive data register 3 */
|
#define LPC31_PCM_HPIN3_OFFSET 0x030 /* Receive data register 3 */
|
||||||
#define LPC313X_PCM_HPIN4_OFFSET 0x034 /* Receive data register 4 */
|
#define LPC31_PCM_HPIN4_OFFSET 0x034 /* Receive data register 4 */
|
||||||
#define LPC313X_PCM_HPIN5_OFFSET 0x038 /* Receive data register 5 */
|
#define LPC31_PCM_HPIN5_OFFSET 0x038 /* Receive data register 5 */
|
||||||
#define LPC313X_PCM_CNTL2_OFFSET 0x03c /* Control register 2 */
|
#define LPC31_PCM_CNTL2_OFFSET 0x03c /* Control register 2 */
|
||||||
|
|
||||||
/* PCM register (virtual) addresses *************************************************************/
|
/* PCM register (virtual) addresses *************************************************************/
|
||||||
|
|
||||||
#define LPC313X_PCM_GLOBAL (LPC313X_PCM_VBASE+LPC313X_PCM_GLOBAL_OFFSET)
|
#define LPC31_PCM_GLOBAL (LPC31_PCM_VBASE+LPC31_PCM_GLOBAL_OFFSET)
|
||||||
#define LPC313X_PCM_CNTL0 (LPC313X_PCM_VBASE+LPC313X_PCM_CNTL0_OFFSET)
|
#define LPC31_PCM_CNTL0 (LPC31_PCM_VBASE+LPC31_PCM_CNTL0_OFFSET)
|
||||||
#define LPC313X_PCM_CNTL1 (LPC313X_PCM_VBASE+LPC313X_PCM_CNTL1_OFFSET)
|
#define LPC31_PCM_CNTL1 (LPC31_PCM_VBASE+LPC31_PCM_CNTL1_OFFSET)
|
||||||
#define LPC313X_PCM_HPOUT(n) (LPC313X_PCM_VBASE+LPC313X_PCM_HPOUT_OFFSET(n))
|
#define LPC31_PCM_HPOUT(n) (LPC31_PCM_VBASE+LPC31_PCM_HPOUT_OFFSET(n))
|
||||||
#define LPC313X_PCM_HPOUT0 (LPC313X_PCM_VBASE+LPC313X_PCM_HPOUT0_OFFSET)
|
#define LPC31_PCM_HPOUT0 (LPC31_PCM_VBASE+LPC31_PCM_HPOUT0_OFFSET)
|
||||||
#define LPC313X_PCM_HPOUT1 (LPC313X_PCM_VBASE+LPC313X_PCM_HPOUT1_OFFSET)
|
#define LPC31_PCM_HPOUT1 (LPC31_PCM_VBASE+LPC31_PCM_HPOUT1_OFFSET)
|
||||||
#define LPC313X_PCM_HPOUT2 (LPC313X_PCM_VBASE+LPC313X_PCM_HPOUT2_OFFSET)
|
#define LPC31_PCM_HPOUT2 (LPC31_PCM_VBASE+LPC31_PCM_HPOUT2_OFFSET)
|
||||||
#define LPC313X_PCM_HPOUT3 (LPC313X_PCM_VBASE+LPC313X_PCM_HPOUT3_OFFSET)
|
#define LPC31_PCM_HPOUT3 (LPC31_PCM_VBASE+LPC31_PCM_HPOUT3_OFFSET)
|
||||||
#define LPC313X_PCM_HPOUT4 (LPC313X_PCM_VBASE+LPC313X_PCM_HPOUT4_OFFSET)
|
#define LPC31_PCM_HPOUT4 (LPC31_PCM_VBASE+LPC31_PCM_HPOUT4_OFFSET)
|
||||||
#define LPC313X_PCM_HPOUT5 (LPC313X_PCM_VBASE+LPC313X_PCM_HPOUT5_OFFSET)
|
#define LPC31_PCM_HPOUT5 (LPC31_PCM_VBASE+LPC31_PCM_HPOUT5_OFFSET)
|
||||||
#define LPC313X_PCM_HPIN(n) (LPC313X_PCM_VBASE+LPC313X_PCM_HPIN_OFFSET(n))
|
#define LPC31_PCM_HPIN(n) (LPC31_PCM_VBASE+LPC31_PCM_HPIN_OFFSET(n))
|
||||||
#define LPC313X_PCM_HPIN0 (LPC313X_PCM_VBASE+LPC313X_PCM_HPIN0_OFFSET)
|
#define LPC31_PCM_HPIN0 (LPC31_PCM_VBASE+LPC31_PCM_HPIN0_OFFSET)
|
||||||
#define LPC313X_PCM_HPIN1 (LPC313X_PCM_VBASE+LPC313X_PCM_HPIN1_OFFSET)
|
#define LPC31_PCM_HPIN1 (LPC31_PCM_VBASE+LPC31_PCM_HPIN1_OFFSET)
|
||||||
#define LPC313X_PCM_HPIN2 (LPC313X_PCM_VBASE+LPC313X_PCM_HPIN2_OFFSET)
|
#define LPC31_PCM_HPIN2 (LPC31_PCM_VBASE+LPC31_PCM_HPIN2_OFFSET)
|
||||||
#define LPC313X_PCM_HPIN3 (LPC313X_PCM_VBASE+LPC313X_PCM_HPIN3_OFFSET)
|
#define LPC31_PCM_HPIN3 (LPC31_PCM_VBASE+LPC31_PCM_HPIN3_OFFSET)
|
||||||
#define LPC313X_PCM_HPIN4 (LPC313X_PCM_VBASE+LPC313X_PCM_HPIN4_OFFSET)
|
#define LPC31_PCM_HPIN4 (LPC31_PCM_VBASE+LPC31_PCM_HPIN4_OFFSET)
|
||||||
#define LPC313X_PCM_HPIN5 (LPC313X_PCM_VBASE+LPC313X_PCM_HPIN5_OFFSET)
|
#define LPC31_PCM_HPIN5 (LPC31_PCM_VBASE+LPC31_PCM_HPIN5_OFFSET)
|
||||||
#define LPC313X_PCM_CNTL2 (LPC313X_PCM_VBASE+LPC313X_PCM_CNTL2_OFFSET)
|
#define LPC31_PCM_CNTL2 (LPC31_PCM_VBASE+LPC31_PCM_CNTL2_OFFSET)
|
||||||
|
|
||||||
/* PCM register bit definitions *****************************************************************/
|
/* PCM register bit definitions *****************************************************************/
|
||||||
|
|
||||||
@@ -171,4 +171,4 @@
|
|||||||
* Public Functions
|
* Public Functions
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#endif /* __ARCH_ARM_SRC_LPC313X_PCM_H */
|
#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_PCM_H */
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_pllconfig.c
|
* arch/arm/src/lpc31xx/lpc31_pllconfig.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -47,7 +47,7 @@
|
|||||||
|
|
||||||
#include <arch/board/board.h>
|
#include <arch/board/board.h>
|
||||||
|
|
||||||
#include "lpc313x_cgudrvr.h"
|
#include "lpc31_cgudrvr.h"
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -66,7 +66,7 @@
|
|||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: lpc313x_switchdomains
|
* Name: lpc31_switchdomains
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Temporarily switch the referemce clock of all domains whose selected
|
* Temporarily switch the referemce clock of all domains whose selected
|
||||||
@@ -75,7 +75,7 @@
|
|||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
static inline uint16_t
|
static inline uint16_t
|
||||||
lpc313x_switchdomains(const struct lpc313x_pllconfig_s * const cfg)
|
lpc31_switchdomains(const struct lpc31_pllconfig_s * const cfg)
|
||||||
{
|
{
|
||||||
uint32_t hppll = (cfg->hppll ? CGU_SSR_HPPLL1 : CGU_SSR_HPPLL0);
|
uint32_t hppll = (cfg->hppll ? CGU_SSR_HPPLL1 : CGU_SSR_HPPLL0);
|
||||||
uint32_t address;
|
uint32_t address;
|
||||||
@@ -89,7 +89,7 @@ lpc313x_switchdomains(const struct lpc313x_pllconfig_s * const cfg)
|
|||||||
{
|
{
|
||||||
/* Get the switch status registers (SSR) for this frequency input domain */
|
/* Get the switch status registers (SSR) for this frequency input domain */
|
||||||
|
|
||||||
address = LPC313X_CGU_SSR(i);
|
address = LPC31_CGU_SSR(i);
|
||||||
regval = getreg32(address);
|
regval = getreg32(address);
|
||||||
|
|
||||||
/* Check if the current frequency selection is the PLL-to-be-configured */
|
/* Check if the current frequency selection is the PLL-to-be-configured */
|
||||||
@@ -98,7 +98,7 @@ lpc313x_switchdomains(const struct lpc313x_pllconfig_s * const cfg)
|
|||||||
{
|
{
|
||||||
/* Yes.. switch reference clock in to FFAST */
|
/* Yes.. switch reference clock in to FFAST */
|
||||||
|
|
||||||
lpc313x_selectfreqin((enum lpc313x_domainid_e)i, CGU_FS_FFAST);
|
lpc31_selectfreqin((enum lpc31_domainid_e)i, CGU_FS_FFAST);
|
||||||
|
|
||||||
/* Add the domain to the set to be restored after the PLL is configured */
|
/* Add the domain to the set to be restored after the PLL is configured */
|
||||||
|
|
||||||
@@ -110,16 +110,16 @@ lpc313x_switchdomains(const struct lpc313x_pllconfig_s * const cfg)
|
|||||||
}
|
}
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: lpc313x_restoredomains
|
* Name: lpc31_restoredomains
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Restore the PLL reference clock to the domains that were temporarily
|
* Restore the PLL reference clock to the domains that were temporarily
|
||||||
switched to FFAST by lpc313x_switchdomains.
|
switched to FFAST by lpc31_switchdomains.
|
||||||
*
|
*
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
static inline void
|
static inline void
|
||||||
lpc313x_restoredomains(const struct lpc313x_pllconfig_s * const cfg,
|
lpc31_restoredomains(const struct lpc31_pllconfig_s * const cfg,
|
||||||
uint16_t dmnset)
|
uint16_t dmnset)
|
||||||
{
|
{
|
||||||
uint32_t finsel = (cfg->hppll ? CGU_FS_HPPLL1 : CGU_FS_HPPLL0);
|
uint32_t finsel = (cfg->hppll ? CGU_FS_HPPLL1 : CGU_FS_HPPLL0);
|
||||||
@@ -135,7 +135,7 @@ lpc313x_restoredomains(const struct lpc313x_pllconfig_s * const cfg,
|
|||||||
{
|
{
|
||||||
/* Switch input reference clock to newly configured HPLL */
|
/* Switch input reference clock to newly configured HPLL */
|
||||||
|
|
||||||
lpc313x_selectfreqin((enum lpc313x_domainid_e)i, finsel);
|
lpc31_selectfreqin((enum lpc31_domainid_e)i, finsel);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@@ -145,21 +145,21 @@ lpc313x_restoredomains(const struct lpc313x_pllconfig_s * const cfg,
|
|||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: lpc313x_pllconfig
|
* Name: lpc31_pllconfig
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Configure the PLL according to the provided selections.
|
* Configure the PLL according to the provided selections.
|
||||||
*
|
*
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
void lpc313x_pllconfig(const struct lpc313x_pllconfig_s * const cfg)
|
void lpc31_pllconfig(const struct lpc31_pllconfig_s * const cfg)
|
||||||
{
|
{
|
||||||
uint32_t pllbase;
|
uint32_t pllbase;
|
||||||
uint16_t dmnset = 0;
|
uint16_t dmnset = 0;
|
||||||
|
|
||||||
/* Switch domains connected to HPLL to FFAST */
|
/* Switch domains connected to HPLL to FFAST */
|
||||||
|
|
||||||
dmnset = lpc313x_switchdomains(cfg);
|
dmnset = lpc31_switchdomains(cfg);
|
||||||
|
|
||||||
/* Get the PLL register base address */
|
/* Get the PLL register base address */
|
||||||
|
|
||||||
@@ -170,33 +170,33 @@ void lpc313x_pllconfig(const struct lpc313x_pllconfig_s * const cfg)
|
|||||||
* enable up limmiter, disable bypass
|
* enable up limmiter, disable bypass
|
||||||
*/
|
*/
|
||||||
|
|
||||||
putreg32(CGU_HPMODE_PD, pllbase + LPC313X_CGU_HPMODE_OFFSET);
|
putreg32(CGU_HPMODE_PD, pllbase + LPC31_CGU_HPMODE_OFFSET);
|
||||||
|
|
||||||
/* Select PLL input frequency source */
|
/* Select PLL input frequency source */
|
||||||
|
|
||||||
putreg32(cfg->finsel, pllbase + LPC313X_CGU_HPFINSEL_OFFSET);
|
putreg32(cfg->finsel, pllbase + LPC31_CGU_HPFINSEL_OFFSET);
|
||||||
|
|
||||||
/* Set M divider */
|
/* Set M divider */
|
||||||
|
|
||||||
putreg32(cfg->mdec & CGU_HPMDEC_MASK, pllbase + LPC313X_CGU_HPMDEC_OFFSET);
|
putreg32(cfg->mdec & CGU_HPMDEC_MASK, pllbase + LPC31_CGU_HPMDEC_OFFSET);
|
||||||
|
|
||||||
/* Set N divider */
|
/* Set N divider */
|
||||||
|
|
||||||
putreg32(cfg->ndec & CGU_HPNDEC_MASK, pllbase + LPC313X_CGU_HPNDEC_OFFSET);
|
putreg32(cfg->ndec & CGU_HPNDEC_MASK, pllbase + LPC31_CGU_HPNDEC_OFFSET);
|
||||||
|
|
||||||
/* Set P divider */
|
/* Set P divider */
|
||||||
|
|
||||||
putreg32(cfg->pdec & CGU_HPPDEC_MASK, pllbase + LPC313X_CGU_HPPDEC_OFFSET);
|
putreg32(cfg->pdec & CGU_HPPDEC_MASK, pllbase + LPC31_CGU_HPPDEC_OFFSET);
|
||||||
|
|
||||||
/* Set bandwidth */
|
/* Set bandwidth */
|
||||||
|
|
||||||
putreg32(cfg->selr, pllbase + LPC313X_CGU_HPSELR_OFFSET);
|
putreg32(cfg->selr, pllbase + LPC31_CGU_HPSELR_OFFSET);
|
||||||
putreg32(cfg->seli, pllbase + LPC313X_CGU_HPSELI_OFFSET);
|
putreg32(cfg->seli, pllbase + LPC31_CGU_HPSELI_OFFSET);
|
||||||
putreg32(cfg->selp, pllbase + LPC313X_CGU_HPSELP_OFFSET);
|
putreg32(cfg->selp, pllbase + LPC31_CGU_HPSELP_OFFSET);
|
||||||
|
|
||||||
/* Power up pll */
|
/* Power up pll */
|
||||||
|
|
||||||
putreg32((cfg->mode & ~CGU_HPMODE_PD) | CGU_HPMODE_CLKEN, pllbase + LPC313X_CGU_HPMODE_OFFSET);
|
putreg32((cfg->mode & ~CGU_HPMODE_PD) | CGU_HPMODE_CLKEN, pllbase + LPC31_CGU_HPMODE_OFFSET);
|
||||||
|
|
||||||
/* Save the estimated freq in driver data for future clk calcs */
|
/* Save the estimated freq in driver data for future clk calcs */
|
||||||
|
|
||||||
@@ -204,24 +204,24 @@ void lpc313x_pllconfig(const struct lpc313x_pllconfig_s * const cfg)
|
|||||||
|
|
||||||
/* Wait for PLL to lock */
|
/* Wait for PLL to lock */
|
||||||
|
|
||||||
while ((getreg32(pllbase + LPC313X_CGU_HPSTATUS_OFFSET) & CGU_HPSTATUS_LOCK) == 0);
|
while ((getreg32(pllbase + LPC31_CGU_HPSTATUS_OFFSET) & CGU_HPSTATUS_LOCK) == 0);
|
||||||
|
|
||||||
/* Switch the domains that were temporarily switched to FFAST back to the HPPLL */
|
/* Switch the domains that were temporarily switched to FFAST back to the HPPLL */
|
||||||
|
|
||||||
lpc313x_restoredomains(cfg, dmnset);
|
lpc31_restoredomains(cfg, dmnset);
|
||||||
}
|
}
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_hp0pllconfig
|
* Name: lpc31_hp0pllconfig
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Configure the HP0 PLL according to the board.h selections.
|
* Configure the HP0 PLL according to the board.h selections.
|
||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
void lpc313x_hp0pllconfig(void)
|
void lpc31_hp0pllconfig(void)
|
||||||
{
|
{
|
||||||
struct lpc313x_pllconfig_s cfg =
|
struct lpc31_pllconfig_s cfg =
|
||||||
{
|
{
|
||||||
.hppll = CGU_HP0PLL,
|
.hppll = CGU_HP0PLL,
|
||||||
.finsel = BOARD_HPLL0_FINSEL,
|
.finsel = BOARD_HPLL0_FINSEL,
|
||||||
@@ -235,20 +235,20 @@ void lpc313x_hp0pllconfig(void)
|
|||||||
.freq = BOARD_HPLL0_FREQ
|
.freq = BOARD_HPLL0_FREQ
|
||||||
};
|
};
|
||||||
|
|
||||||
lpc313x_pllconfig(&cfg);
|
lpc31_pllconfig(&cfg);
|
||||||
}
|
}
|
||||||
|
|
||||||
/************************************************************************
|
/************************************************************************
|
||||||
* Name: lpc313x_hp1pllconfig
|
* Name: lpc31_hp1pllconfig
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Configure the HP1 PLL according to the board.h selections.
|
* Configure the HP1 PLL according to the board.h selections.
|
||||||
*
|
*
|
||||||
************************************************************************/
|
************************************************************************/
|
||||||
|
|
||||||
void lpc313x_hp1pllconfig(void)
|
void lpc31_hp1pllconfig(void)
|
||||||
{
|
{
|
||||||
struct lpc313x_pllconfig_s cfg =
|
struct lpc31_pllconfig_s cfg =
|
||||||
{
|
{
|
||||||
.hppll = CGU_HP1PLL,
|
.hppll = CGU_HP1PLL,
|
||||||
.finsel = BOARD_HPLL1_FINSEL,
|
.finsel = BOARD_HPLL1_FINSEL,
|
||||||
@@ -262,6 +262,6 @@ void lpc313x_hp1pllconfig(void)
|
|||||||
.freq = BOARD_HPLL1_FREQ
|
.freq = BOARD_HPLL1_FREQ
|
||||||
};
|
};
|
||||||
|
|
||||||
lpc313x_pllconfig(&cfg);
|
lpc31_pllconfig(&cfg);
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_pwm.h
|
* arch/arm/src/lpc31xx/lpc31_pwm.h
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -33,15 +33,15 @@
|
|||||||
*
|
*
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#ifndef __ARCH_ARM_SRC_LPC313X_PWM_H
|
#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_PWM_H
|
||||||
#define __ARCH_ARM_SRC_LPC313X_PWM_H
|
#define __ARCH_ARM_SRC_LPC31XX_LPC31_PWM_H
|
||||||
|
|
||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* Included Files
|
* Included Files
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#include <nuttx/config.h>
|
#include <nuttx/config.h>
|
||||||
#include "lpc313x_memorymap.h"
|
#include "lpc31_memorymap.h"
|
||||||
|
|
||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -49,18 +49,18 @@
|
|||||||
|
|
||||||
/* PWM register base address offset into the APB1 domain ****************************************/
|
/* PWM register base address offset into the APB1 domain ****************************************/
|
||||||
|
|
||||||
#define LPC313X_PWM_VBASE (LPC313X_APB1_VADDR+LPC313X_APB1_PWM_OFFSET)
|
#define LPC31_PWM_VBASE (LPC31_APB1_VADDR+LPC31_APB1_PWM_OFFSET)
|
||||||
#define LPC313X_PWM_PBASE (LPC313X_APB1_PADDR+LPC313X_APB1_PWM_OFFSET)
|
#define LPC31_PWM_PBASE (LPC31_APB1_PADDR+LPC31_APB1_PWM_OFFSET)
|
||||||
|
|
||||||
/* PWM register offsets (with respect to the PWM base) ******************************************/
|
/* PWM register offsets (with respect to the PWM base) ******************************************/
|
||||||
|
|
||||||
#define LPC313X_PWM_TMR_OFFSET 0x000 /* Timer Register */
|
#define LPC31_PWM_TMR_OFFSET 0x000 /* Timer Register */
|
||||||
#define LPC313X_PWM_CNTL_OFFSET 0x004 /* Control Register */
|
#define LPC31_PWM_CNTL_OFFSET 0x004 /* Control Register */
|
||||||
|
|
||||||
/* PWM register (virtual) addresses *************************************************************/
|
/* PWM register (virtual) addresses *************************************************************/
|
||||||
|
|
||||||
#define LPC313X_PWM_TMR (LPC313X_PWM_VBASE+LPC313X_PWM_TMR_OFFSET)
|
#define LPC31_PWM_TMR (LPC31_PWM_VBASE+LPC31_PWM_TMR_OFFSET)
|
||||||
#define LPC313X_PWM_CNTL (LPC313X_PWM_VBASE+LPC313X_PWM_CNTL_OFFSET)
|
#define LPC31_PWM_CNTL (LPC31_PWM_VBASE+LPC31_PWM_CNTL_OFFSET)
|
||||||
|
|
||||||
/* PWM register bit definitions *****************************************************************/
|
/* PWM register bit definitions *****************************************************************/
|
||||||
|
|
||||||
@@ -94,4 +94,4 @@
|
|||||||
* Public Functions
|
* Public Functions
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#endif /* __ARCH_ARM_SRC_LPC313X_PWM_H */
|
#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_PWM_H */
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_resetclks.c
|
* arch/arm/src/lpc31xx/lpc31_resetclks.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -43,7 +43,7 @@
|
|||||||
|
|
||||||
#include <arch/board/board.h>
|
#include <arch/board/board.h>
|
||||||
|
|
||||||
#include "lpc313x_cgudrvr.h"
|
#include "lpc31_cgudrvr.h"
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -66,14 +66,14 @@
|
|||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: lpc313x_resetclks
|
* Name: lpc31_resetclks
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Put all clocks into a known, initial state
|
* Put all clocks into a known, initial state
|
||||||
*
|
*
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
void lpc313x_resetclks(void)
|
void lpc31_resetclks(void)
|
||||||
{
|
{
|
||||||
uint32_t regaddr;
|
uint32_t regaddr;
|
||||||
uint32_t regval;
|
uint32_t regval;
|
||||||
@@ -87,16 +87,16 @@ void lpc313x_resetclks(void)
|
|||||||
{
|
{
|
||||||
/* Switch reference clock in to FFAST */
|
/* Switch reference clock in to FFAST */
|
||||||
|
|
||||||
lpc313x_selectfreqin((enum lpc313x_domainid_e)i, CGU_FS_FFAST);
|
lpc31_selectfreqin((enum lpc31_domainid_e)i, CGU_FS_FFAST);
|
||||||
|
|
||||||
/* Check if the domain has a BCR */
|
/* Check if the domain has a BCR */
|
||||||
|
|
||||||
bcrndx = lpc313x_bcrndx((enum lpc313x_domainid_e)i);
|
bcrndx = lpc31_bcrndx((enum lpc31_domainid_e)i);
|
||||||
if (bcrndx != BCRNDX_INVALID)
|
if (bcrndx != BCRNDX_INVALID)
|
||||||
{
|
{
|
||||||
/* Yes.. disable all BCRs */
|
/* Yes.. disable all BCRs */
|
||||||
|
|
||||||
putreg32(0, LPC313X_CGU_BCR(bcrndx));
|
putreg32(0, LPC31_CGU_BCR(bcrndx));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -106,21 +106,21 @@ void lpc313x_resetclks(void)
|
|||||||
{
|
{
|
||||||
/* Check if this clock has an ESR register */
|
/* Check if this clock has an ESR register */
|
||||||
|
|
||||||
esrndx = lpc313x_esrndx((enum lpc313x_clockid_e)i);
|
esrndx = lpc31_esrndx((enum lpc31_clockid_e)i);
|
||||||
if (esrndx != ESRNDX_INVALID)
|
if (esrndx != ESRNDX_INVALID)
|
||||||
{
|
{
|
||||||
/* Yes.. Clear the clocks ESR to deselect fractional divider */
|
/* Yes.. Clear the clocks ESR to deselect fractional divider */
|
||||||
|
|
||||||
putreg32(0, LPC313X_CGU_ESR(esrndx));
|
putreg32(0, LPC31_CGU_ESR(esrndx));
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Enable external enabling for all possible clocks to conserve power */
|
/* Enable external enabling for all possible clocks to conserve power */
|
||||||
|
|
||||||
lpc313x_enableexten((enum lpc313x_clockid_e)i);
|
lpc31_enableexten((enum lpc31_clockid_e)i);
|
||||||
|
|
||||||
/* Set enable-out's for only the following clocks */
|
/* Set enable-out's for only the following clocks */
|
||||||
|
|
||||||
regaddr = LPC313X_CGU_PCR(i);
|
regaddr = LPC31_CGU_PCR(i);
|
||||||
regval = getreg32(regaddr);
|
regval = getreg32(regaddr);
|
||||||
if (i == (int)CLKID_ARM926BUSIFCLK || i == (int)CLKID_MPMCCFGCLK)
|
if (i == (int)CLKID_ARM926BUSIFCLK || i == (int)CLKID_MPMCCFGCLK)
|
||||||
{
|
{
|
||||||
@@ -136,14 +136,14 @@ void lpc313x_resetclks(void)
|
|||||||
* upon if the clock is needed by the board logic or not
|
* upon if the clock is needed by the board logic or not
|
||||||
*/
|
*/
|
||||||
|
|
||||||
(void)lpc313x_defclk((enum lpc313x_clockid_e)i);
|
(void)lpc31_defclk((enum lpc31_clockid_e)i);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Disable all fractional dividers */
|
/* Disable all fractional dividers */
|
||||||
|
|
||||||
for (i = 0; i < CGU_NFRACDIV; i++)
|
for (i = 0; i < CGU_NFRACDIV; i++)
|
||||||
{
|
{
|
||||||
regaddr = LPC313X_CGU_FDC(i);
|
regaddr = LPC31_CGU_FDC(i);
|
||||||
regval = getreg32(regaddr);
|
regval = getreg32(regaddr);
|
||||||
regval &= ~CGU_FDC_RUN;
|
regval &= ~CGU_FDC_RUN;
|
||||||
putreg32(regval, regaddr);
|
putreg32(regval, regaddr);
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_rng.h
|
* arch/arm/src/lpc31xx/lpc31_rng.h
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -33,15 +33,15 @@
|
|||||||
*
|
*
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#ifndef __ARCH_ARM_SRC_LPC313X_RNG_H
|
#ifndef __ARCH_ARM_SRC_LPC31XX_LPC31_RNG_H
|
||||||
#define __ARCH_ARM_SRC_LPC313X_RNG_H
|
#define __ARCH_ARM_SRC_LPC31XX_LPC31_RNG_H
|
||||||
|
|
||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* Included Files
|
* Included Files
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#include <nuttx/config.h>
|
#include <nuttx/config.h>
|
||||||
#include "lpc313x_memorymap.h"
|
#include "lpc31_memorymap.h"
|
||||||
|
|
||||||
/************************************************************************************************
|
/************************************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -49,18 +49,18 @@
|
|||||||
|
|
||||||
/* RNG register base address offset into the APB0 domain ****************************************/
|
/* RNG register base address offset into the APB0 domain ****************************************/
|
||||||
|
|
||||||
#define LPC313X_RNG_VBASE (LPC313X_APB0_VADDR+LPC313X_APB0_RNG_OFFSET)
|
#define LPC31_RNG_VBASE (LPC31_APB0_VADDR+LPC31_APB0_RNG_OFFSET)
|
||||||
#define LPC313X_RNG_PBASE (LPC313X_APB0_PADDR+LPC313X_APB0_RNG_OFFSET)
|
#define LPC31_RNG_PBASE (LPC31_APB0_PADDR+LPC31_APB0_RNG_OFFSET)
|
||||||
|
|
||||||
/* RNG register offsets (with respect to the RNG base) ******************************************/
|
/* RNG register offsets (with respect to the RNG base) ******************************************/
|
||||||
|
|
||||||
#define LPC313X_RNG_RAND_OFFSET 0x0000 /* Random number */
|
#define LPC31_RNG_RAND_OFFSET 0x0000 /* Random number */
|
||||||
#define LPC313X_RNG_PWRDWN_OFFSET 0x0ff4 /* Power-down mode */
|
#define LPC31_RNG_PWRDWN_OFFSET 0x0ff4 /* Power-down mode */
|
||||||
|
|
||||||
/* RNG register (virtual) addresses *************************************************************/
|
/* RNG register (virtual) addresses *************************************************************/
|
||||||
|
|
||||||
#define LPC313X_RNG_RAND (LPC313X_RNG_VBASE+LPC313X_RNG_RAND_OFFSET)
|
#define LPC31_RNG_RAND (LPC31_RNG_VBASE+LPC31_RNG_RAND_OFFSET)
|
||||||
#define LPC313X_RNG_PWRDWN (LPC313X_RNG_VBASE+LPC313X_RNG_PWRDWN_OFFSET)
|
#define LPC31_RNG_PWRDWN (LPC31_RNG_VBASE+LPC31_RNG_PWRDWN_OFFSET)
|
||||||
|
|
||||||
/* RNG register bit definitions *****************************************************************/
|
/* RNG register bit definitions *****************************************************************/
|
||||||
|
|
||||||
@@ -82,4 +82,4 @@
|
|||||||
* Public Functions
|
* Public Functions
|
||||||
************************************************************************************************/
|
************************************************************************************************/
|
||||||
|
|
||||||
#endif /* __ARCH_ARM_SRC_LPC313X_RNG_H */
|
#endif /* __ARCH_ARM_SRC_LPC31XX_LPC31_RNG_H */
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_serial.c
|
* arch/arm/src/lpc31xx/lpc31_serial.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -57,8 +57,8 @@
|
|||||||
#include "os_internal.h"
|
#include "os_internal.h"
|
||||||
#include "up_internal.h"
|
#include "up_internal.h"
|
||||||
|
|
||||||
#include "lpc313x_cgudrvr.h"
|
#include "lpc31_cgudrvr.h"
|
||||||
#include "lpc313x_uart.h"
|
#include "lpc31_uart.h"
|
||||||
|
|
||||||
#ifdef CONFIG_USE_SERIALDRIVER
|
#ifdef CONFIG_USE_SERIALDRIVER
|
||||||
|
|
||||||
@@ -124,7 +124,7 @@ struct uart_ops_s g_uart_ops =
|
|||||||
static char g_rxbuffer[CONFIG_UART_RXBUFSIZE];
|
static char g_rxbuffer[CONFIG_UART_RXBUFSIZE];
|
||||||
static char g_txbuffer[CONFIG_UART_TXBUFSIZE];
|
static char g_txbuffer[CONFIG_UART_TXBUFSIZE];
|
||||||
|
|
||||||
/* This describes the state of the single LPC313X uart port. */
|
/* This describes the state of the single LPC313XX uart port. */
|
||||||
|
|
||||||
static struct up_dev_s g_uartpriv;
|
static struct up_dev_s g_uartpriv;
|
||||||
static uart_dev_t g_uartport =
|
static uart_dev_t g_uartport =
|
||||||
@@ -159,7 +159,7 @@ static inline void up_disableuartint(struct up_dev_s *priv, uint8_t *ier)
|
|||||||
}
|
}
|
||||||
|
|
||||||
priv->ier &= ~UART_IER_ALLINTS;
|
priv->ier &= ~UART_IER_ALLINTS;
|
||||||
putreg32((uint32_t)priv->ier, LPC313X_UART_IER);
|
putreg32((uint32_t)priv->ier, LPC31_UART_IER);
|
||||||
}
|
}
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
@@ -169,7 +169,7 @@ static inline void up_disableuartint(struct up_dev_s *priv, uint8_t *ier)
|
|||||||
static inline void up_restoreuartint(struct up_dev_s *priv, uint8_t ier)
|
static inline void up_restoreuartint(struct up_dev_s *priv, uint8_t ier)
|
||||||
{
|
{
|
||||||
priv->ier |= ier & UART_IER_ALLINTS;
|
priv->ier |= ier & UART_IER_ALLINTS;
|
||||||
putreg32((uint32_t)priv->ier, LPC313X_UART_IER);
|
putreg32((uint32_t)priv->ier, LPC31_UART_IER);
|
||||||
}
|
}
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
@@ -178,9 +178,9 @@ static inline void up_restoreuartint(struct up_dev_s *priv, uint8_t ier)
|
|||||||
|
|
||||||
static inline void up_enablebreaks(void)
|
static inline void up_enablebreaks(void)
|
||||||
{
|
{
|
||||||
uint32_t lcr = getreg32(LPC313X_UART_LCR);
|
uint32_t lcr = getreg32(LPC31_UART_LCR);
|
||||||
lcr |= UART_LCR_BRKCTRL;
|
lcr |= UART_LCR_BRKCTRL;
|
||||||
putreg32(lcr, LPC313X_UART_LCR);
|
putreg32(lcr, LPC31_UART_LCR);
|
||||||
}
|
}
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
@@ -189,9 +189,9 @@ static inline void up_enablebreaks(void)
|
|||||||
|
|
||||||
static inline void up_disablebreaks(void)
|
static inline void up_disablebreaks(void)
|
||||||
{
|
{
|
||||||
uint32_t lcr = getreg32(LPC313X_UART_LCR);
|
uint32_t lcr = getreg32(LPC31_UART_LCR);
|
||||||
lcr &= ~UART_LCR_BRKCTRL;
|
lcr &= ~UART_LCR_BRKCTRL;
|
||||||
putreg32(lcr, LPC313X_UART_LCR);
|
putreg32(lcr, LPC31_UART_LCR);
|
||||||
}
|
}
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
@@ -206,7 +206,7 @@ static inline void up_configbaud(void)
|
|||||||
* file.
|
* file.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#ifndef CONFIG_LPC313X_UART_MULVAL
|
#ifndef CONFIG_LPC31_UART_MULVAL
|
||||||
uint32_t qtrclk;
|
uint32_t qtrclk;
|
||||||
uint32_t regval;
|
uint32_t regval;
|
||||||
|
|
||||||
@@ -239,7 +239,7 @@ static inline void up_configbaud(void)
|
|||||||
|
|
||||||
/* Get UART block clock divided by 16 */
|
/* Get UART block clock divided by 16 */
|
||||||
|
|
||||||
qtrclk = lpc313x_clkfreq(CLKID_UARTUCLK, DOMAINID_UART) >> 4;
|
qtrclk = lpc31_clkfreq(CLKID_UARTUCLK, DOMAINID_UART) >> 4;
|
||||||
|
|
||||||
/* Try every valid multiplier, tmulval (or until a perfect
|
/* Try every valid multiplier, tmulval (or until a perfect
|
||||||
* match is found).
|
* match is found).
|
||||||
@@ -292,43 +292,43 @@ static inline void up_configbaud(void)
|
|||||||
|
|
||||||
/* Set the Divisor Latch Access Bit (DLAB) to enable DLL/DLM access */
|
/* Set the Divisor Latch Access Bit (DLAB) to enable DLL/DLM access */
|
||||||
|
|
||||||
regval = getreg32(LPC313X_UART_LCR);
|
regval = getreg32(LPC31_UART_LCR);
|
||||||
regval |= UART_LCR_DLAB;
|
regval |= UART_LCR_DLAB;
|
||||||
putreg32(regval, LPC313X_UART_LCR);
|
putreg32(regval, LPC31_UART_LCR);
|
||||||
|
|
||||||
/* Configure the MS and LS DLAB registers */
|
/* Configure the MS and LS DLAB registers */
|
||||||
|
|
||||||
putreg32(div & UART_DLL_MASK, LPC313X_UART_DLL);
|
putreg32(div & UART_DLL_MASK, LPC31_UART_DLL);
|
||||||
putreg32((div >> 8) & UART_DLL_MASK, LPC313X_UART_DLM);
|
putreg32((div >> 8) & UART_DLL_MASK, LPC31_UART_DLM);
|
||||||
|
|
||||||
regval &= ~UART_LCR_DLAB;
|
regval &= ~UART_LCR_DLAB;
|
||||||
putreg32(regval, LPC313X_UART_LCR);
|
putreg32(regval, LPC31_UART_LCR);
|
||||||
|
|
||||||
/* Configure the Fractional Divider Register (FDR) */
|
/* Configure the Fractional Divider Register (FDR) */
|
||||||
|
|
||||||
putreg32((mulval << UART_FDR_MULVAL_SHIFT) |
|
putreg32((mulval << UART_FDR_MULVAL_SHIFT) |
|
||||||
(divaddval << UART_FDR_DIVADDVAL_SHIFT),
|
(divaddval << UART_FDR_DIVADDVAL_SHIFT),
|
||||||
LPC313X_UART_FDR);
|
LPC31_UART_FDR);
|
||||||
#else
|
#else
|
||||||
/* Set the Divisor Latch Access Bit (DLAB) to enable DLL/DLM access */
|
/* Set the Divisor Latch Access Bit (DLAB) to enable DLL/DLM access */
|
||||||
|
|
||||||
regval = getreg32(LPC313X_UART_LCR);
|
regval = getreg32(LPC31_UART_LCR);
|
||||||
regval |= UART_LCR_DLAB;
|
regval |= UART_LCR_DLAB;
|
||||||
putreg32(regval, LPC313X_UART_LCR);
|
putreg32(regval, LPC31_UART_LCR);
|
||||||
|
|
||||||
/* Configure the MS and LS DLAB registers */
|
/* Configure the MS and LS DLAB registers */
|
||||||
|
|
||||||
putreg32(CONFIG_LPC313X_UART_DIVISOR & UART_DLL_MASK, LPC313X_UART_DLL);
|
putreg32(CONFIG_LPC31_UART_DIVISOR & UART_DLL_MASK, LPC31_UART_DLL);
|
||||||
putreg32((CONFIG_LPC313X_UART_DIVISOR >> 8) & UART_DLL_MASK, LPC313X_UART_DLM);
|
putreg32((CONFIG_LPC31_UART_DIVISOR >> 8) & UART_DLL_MASK, LPC31_UART_DLM);
|
||||||
|
|
||||||
regval &= ~UART_LCR_DLAB;
|
regval &= ~UART_LCR_DLAB;
|
||||||
putreg32(regval, LPC313X_UART_LCR);
|
putreg32(regval, LPC31_UART_LCR);
|
||||||
|
|
||||||
/* Configure the Fractional Divider Register (FDR) */
|
/* Configure the Fractional Divider Register (FDR) */
|
||||||
|
|
||||||
putreg32((CONFIG_LPC313X_UART_MULVAL << UART_FDR_MULVAL_SHIFT) |
|
putreg32((CONFIG_LPC31_UART_MULVAL << UART_FDR_MULVAL_SHIFT) |
|
||||||
(CONFIG_LPC313X_UART_DIVADDVAL << UART_FDR_DIVADDVAL_SHIFT),
|
(CONFIG_LPC31_UART_DIVADDVAL << UART_FDR_DIVADDVAL_SHIFT),
|
||||||
LPC313X_UART_FDR);
|
LPC31_UART_FDR);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -343,21 +343,21 @@ static inline void up_configbaud(void)
|
|||||||
|
|
||||||
static int up_setup(struct uart_dev_s *dev)
|
static int up_setup(struct uart_dev_s *dev)
|
||||||
{
|
{
|
||||||
#ifndef CONFIG_SUPPRESS_LPC313X_UART_CONFIG
|
#ifndef CONFIG_SUPPRESS_LPC31_UART_CONFIG
|
||||||
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
||||||
uint32_t regval;
|
uint32_t regval;
|
||||||
|
|
||||||
/* Clear fifos */
|
/* Clear fifos */
|
||||||
|
|
||||||
putreg32((UART_FCR_RXFIFORST|UART_FCR_TXFIFORST), LPC313X_UART_FCR);
|
putreg32((UART_FCR_RXFIFORST|UART_FCR_TXFIFORST), LPC31_UART_FCR);
|
||||||
|
|
||||||
/* Set trigger */
|
/* Set trigger */
|
||||||
|
|
||||||
putreg32((UART_FCR_FIFOENABLE|UART_FCR_RXTRIGLEVEL_16), LPC313X_UART_FCR);
|
putreg32((UART_FCR_FIFOENABLE|UART_FCR_RXTRIGLEVEL_16), LPC31_UART_FCR);
|
||||||
|
|
||||||
/* Set up the IER */
|
/* Set up the IER */
|
||||||
|
|
||||||
priv->ier = getreg32(LPC313X_UART_IER);
|
priv->ier = getreg32(LPC31_UART_IER);
|
||||||
|
|
||||||
/* Set up the LCR */
|
/* Set up the LCR */
|
||||||
|
|
||||||
@@ -382,7 +382,7 @@ static int up_setup(struct uart_dev_s *dev)
|
|||||||
#elif CONFIG_UART_PARITY == 2
|
#elif CONFIG_UART_PARITY == 2
|
||||||
regval |= (UART_LCR_PAREVEN|UART_LCR_PAREN);
|
regval |= (UART_LCR_PAREVEN|UART_LCR_PAREN);
|
||||||
#endif
|
#endif
|
||||||
putreg32(regval, LPC313X_UART_LCR);
|
putreg32(regval, LPC31_UART_LCR);
|
||||||
|
|
||||||
/* Set the BAUD divisor */
|
/* Set the BAUD divisor */
|
||||||
|
|
||||||
@@ -392,7 +392,7 @@ static int up_setup(struct uart_dev_s *dev)
|
|||||||
|
|
||||||
putreg32((UART_FCR_RXTRIGLEVEL_16|UART_FCR_TXFIFORST|
|
putreg32((UART_FCR_RXTRIGLEVEL_16|UART_FCR_TXFIFORST|
|
||||||
UART_FCR_RXFIFORST|UART_FCR_FIFOENABLE),
|
UART_FCR_RXFIFORST|UART_FCR_FIFOENABLE),
|
||||||
LPC313X_UART_FCR);
|
LPC31_UART_FCR);
|
||||||
|
|
||||||
/* The NuttX serial driver waits for the first THRE interrrupt before
|
/* The NuttX serial driver waits for the first THRE interrrupt before
|
||||||
* sending serial data... However, it appears that the lpc313x hardware
|
* sending serial data... However, it appears that the lpc313x hardware
|
||||||
@@ -401,7 +401,7 @@ static int up_setup(struct uart_dev_s *dev)
|
|||||||
* startup to kick things off.
|
* startup to kick things off.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
putreg32('\0', LPC313X_UART_THR);
|
putreg32('\0', LPC31_UART_THR);
|
||||||
#endif
|
#endif
|
||||||
return OK;
|
return OK;
|
||||||
}
|
}
|
||||||
@@ -442,14 +442,14 @@ static int up_attach(struct uart_dev_s *dev)
|
|||||||
|
|
||||||
/* Attach and enable the IRQ */
|
/* Attach and enable the IRQ */
|
||||||
|
|
||||||
ret = irq_attach(LPC313X_IRQ_UART, up_interrupt);
|
ret = irq_attach(LPC31_IRQ_UART, up_interrupt);
|
||||||
if (ret == OK)
|
if (ret == OK)
|
||||||
{
|
{
|
||||||
/* Enable the interrupt (RX and TX interrupts are still disabled
|
/* Enable the interrupt (RX and TX interrupts are still disabled
|
||||||
* in the UART
|
* in the UART
|
||||||
*/
|
*/
|
||||||
|
|
||||||
up_enable_irq(LPC313X_IRQ_UART);
|
up_enable_irq(LPC31_IRQ_UART);
|
||||||
}
|
}
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
@@ -466,8 +466,8 @@ static int up_attach(struct uart_dev_s *dev)
|
|||||||
|
|
||||||
static void up_detach(struct uart_dev_s *dev)
|
static void up_detach(struct uart_dev_s *dev)
|
||||||
{
|
{
|
||||||
up_disable_irq(LPC313X_IRQ_UART);
|
up_disable_irq(LPC31_IRQ_UART);
|
||||||
irq_detach(LPC313X_IRQ_UART);
|
irq_detach(LPC31_IRQ_UART);
|
||||||
}
|
}
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
@@ -496,7 +496,7 @@ static int up_interrupt(int irq, void *context)
|
|||||||
* termination conditions
|
* termination conditions
|
||||||
*/
|
*/
|
||||||
|
|
||||||
status = getreg32(LPC313X_UART_IIR);
|
status = getreg32(LPC31_UART_IIR);
|
||||||
|
|
||||||
/* The NO INTERRUPT should be zero if there are pending
|
/* The NO INTERRUPT should be zero if there are pending
|
||||||
* interrupts
|
* interrupts
|
||||||
@@ -538,7 +538,7 @@ static int up_interrupt(int irq, void *context)
|
|||||||
{
|
{
|
||||||
/* Read the modem status register (MSR) to clear */
|
/* Read the modem status register (MSR) to clear */
|
||||||
|
|
||||||
status = getreg32(LPC313X_UART_MSR);
|
status = getreg32(LPC31_UART_MSR);
|
||||||
fvdbg("MSR: %02x\n", status);
|
fvdbg("MSR: %02x\n", status);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
@@ -549,7 +549,7 @@ static int up_interrupt(int irq, void *context)
|
|||||||
{
|
{
|
||||||
/* Read the line status register (LSR) to clear */
|
/* Read the line status register (LSR) to clear */
|
||||||
|
|
||||||
status = getreg32(LPC313X_UART_LSR);
|
status = getreg32(LPC31_UART_LSR);
|
||||||
fvdbg("LSR: %02x\n", status);
|
fvdbg("LSR: %02x\n", status);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
@@ -636,8 +636,8 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status)
|
|||||||
{
|
{
|
||||||
uint32_t rbr;
|
uint32_t rbr;
|
||||||
|
|
||||||
*status = getreg32(LPC313X_UART_LSR);
|
*status = getreg32(LPC31_UART_LSR);
|
||||||
rbr = getreg32(LPC313X_UART_RBR);
|
rbr = getreg32(LPC31_UART_RBR);
|
||||||
return rbr & 0xff;
|
return rbr & 0xff;
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -662,7 +662,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
|
|||||||
{
|
{
|
||||||
priv->ier &= ~UART_IER_RDAINTEN;
|
priv->ier &= ~UART_IER_RDAINTEN;
|
||||||
}
|
}
|
||||||
putreg32(priv->ier, LPC313X_UART_IER);
|
putreg32(priv->ier, LPC31_UART_IER);
|
||||||
}
|
}
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
@@ -675,7 +675,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
|
|||||||
|
|
||||||
static bool up_rxavailable(struct uart_dev_s *dev)
|
static bool up_rxavailable(struct uart_dev_s *dev)
|
||||||
{
|
{
|
||||||
return ((getreg32(LPC313X_UART_LSR) & UART_LSR_RDR) != 0);
|
return ((getreg32(LPC31_UART_LSR) & UART_LSR_RDR) != 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
@@ -688,7 +688,7 @@ static bool up_rxavailable(struct uart_dev_s *dev)
|
|||||||
|
|
||||||
static void up_send(struct uart_dev_s *dev, int ch)
|
static void up_send(struct uart_dev_s *dev, int ch)
|
||||||
{
|
{
|
||||||
putreg32((uint32_t)ch, LPC313X_UART_THR);
|
putreg32((uint32_t)ch, LPC31_UART_THR);
|
||||||
}
|
}
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
@@ -712,7 +712,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
|
|||||||
{
|
{
|
||||||
priv->ier &= ~UART_IER_THREINTEN;
|
priv->ier &= ~UART_IER_THREINTEN;
|
||||||
}
|
}
|
||||||
putreg32(priv->ier, LPC313X_UART_IER);
|
putreg32(priv->ier, LPC31_UART_IER);
|
||||||
}
|
}
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
@@ -725,7 +725,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
|
|||||||
|
|
||||||
static bool up_txready(struct uart_dev_s *dev)
|
static bool up_txready(struct uart_dev_s *dev)
|
||||||
{
|
{
|
||||||
return ((getreg32(LPC313X_UART_LSR) & UART_LSR_THRE) != 0);
|
return ((getreg32(LPC31_UART_LSR) & UART_LSR_THRE) != 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
@@ -738,7 +738,7 @@ static bool up_txready(struct uart_dev_s *dev)
|
|||||||
|
|
||||||
static bool up_txempty(struct uart_dev_s *dev)
|
static bool up_txempty(struct uart_dev_s *dev)
|
||||||
{
|
{
|
||||||
return ((getreg32(LPC313X_UART_LSR) & UART_LSR_TEMT) != 0);
|
return ((getreg32(LPC31_UART_LSR) & UART_LSR_TEMT) != 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
@@ -759,8 +759,8 @@ void up_earlyserialinit(void)
|
|||||||
{
|
{
|
||||||
/* Enable UART system clock */
|
/* Enable UART system clock */
|
||||||
|
|
||||||
lpc313x_enableclock(CLKID_UARTAPBCLK);
|
lpc31_enableclock(CLKID_UARTAPBCLK);
|
||||||
lpc313x_enableclock(CLKID_UARTUCLK);
|
lpc31_enableclock(CLKID_UARTUCLK);
|
||||||
|
|
||||||
/* Disable UART interrupts */
|
/* Disable UART interrupts */
|
||||||
|
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_setfdiv.c
|
* arch/arm/src/lpc31xx/lpc31_setfdiv.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -44,8 +44,8 @@
|
|||||||
|
|
||||||
#include <arch/board/board.h>
|
#include <arch/board/board.h>
|
||||||
|
|
||||||
#include "lpc313x_cgu.h"
|
#include "lpc31_cgu.h"
|
||||||
#include "lpc313x_cgudrvr.h"
|
#include "lpc31_cgudrvr.h"
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -68,7 +68,7 @@
|
|||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: lpc313x_setfdiv
|
* Name: lpc31_setfdiv
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Set/reset subdomain frequency containing the specified clock using the
|
* Set/reset subdomain frequency containing the specified clock using the
|
||||||
@@ -76,9 +76,9 @@
|
|||||||
*
|
*
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
void lpc313x_setfdiv(enum lpc313x_domainid_e dmnid,
|
void lpc31_setfdiv(enum lpc31_domainid_e dmnid,
|
||||||
enum lpc313x_clockid_e clkid,
|
enum lpc31_clockid_e clkid,
|
||||||
const struct lpc313x_fdivconfig_s *fdiv)
|
const struct lpc31_fdivconfig_s *fdiv)
|
||||||
{
|
{
|
||||||
uint32_t regaddr;
|
uint32_t regaddr;
|
||||||
unsigned int basefreq;
|
unsigned int basefreq;
|
||||||
@@ -87,7 +87,7 @@ void lpc313x_setfdiv(enum lpc313x_domainid_e dmnid,
|
|||||||
|
|
||||||
/* Get the frequency divider associated with this clock */
|
/* Get the frequency divider associated with this clock */
|
||||||
|
|
||||||
fdcndx = lpc313x_fdcndx(clkid, dmnid);
|
fdcndx = lpc31_fdcndx(clkid, dmnid);
|
||||||
|
|
||||||
/* Does this clock have a frequency divicer? */
|
/* Does this clock have a frequency divicer? */
|
||||||
|
|
||||||
@@ -95,41 +95,41 @@ void lpc313x_setfdiv(enum lpc313x_domainid_e dmnid,
|
|||||||
{
|
{
|
||||||
/* Yes.. Save the current reference frequency selection */
|
/* Yes.. Save the current reference frequency selection */
|
||||||
|
|
||||||
regaddr = LPC313X_CGU_SSR((int)dmnid);
|
regaddr = LPC31_CGU_SSR((int)dmnid);
|
||||||
basefreq = (getreg32(regaddr) & CGU_SSR_FS_MASK) >> CGU_SSR_FS_SHIFT;
|
basefreq = (getreg32(regaddr) & CGU_SSR_FS_MASK) >> CGU_SSR_FS_SHIFT;
|
||||||
|
|
||||||
/* Switch domain to FFAST input */
|
/* Switch domain to FFAST input */
|
||||||
|
|
||||||
lpc313x_selectfreqin(dmnid, CGU_FS_FFAST);
|
lpc31_selectfreqin(dmnid, CGU_FS_FFAST);
|
||||||
|
|
||||||
/* Get the index of the associated BCR register. Does this domain
|
/* Get the index of the associated BCR register. Does this domain
|
||||||
* have a BCR?
|
* have a BCR?
|
||||||
*/
|
*/
|
||||||
|
|
||||||
bcrndx = lpc313x_bcrndx(dmnid);
|
bcrndx = lpc31_bcrndx(dmnid);
|
||||||
if (bcrndx != BCRNDX_INVALID)
|
if (bcrndx != BCRNDX_INVALID)
|
||||||
{
|
{
|
||||||
|
|
||||||
/* Yes... Disable the BCR */
|
/* Yes... Disable the BCR */
|
||||||
|
|
||||||
regaddr = LPC313X_CGU_BCR(bcrndx);
|
regaddr = LPC31_CGU_BCR(bcrndx);
|
||||||
putreg32(0, regaddr);
|
putreg32(0, regaddr);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Change fractional divider to the provided settings */
|
/* Change fractional divider to the provided settings */
|
||||||
|
|
||||||
lpc313x_fdivinit(fdcndx, fdiv, true);
|
lpc31_fdivinit(fdcndx, fdiv, true);
|
||||||
|
|
||||||
/* Re-enable the BCR (if one is associated with this domain) */
|
/* Re-enable the BCR (if one is associated with this domain) */
|
||||||
|
|
||||||
if (bcrndx != BCRNDX_INVALID)
|
if (bcrndx != BCRNDX_INVALID)
|
||||||
{
|
{
|
||||||
regaddr = LPC313X_CGU_BCR(bcrndx);
|
regaddr = LPC31_CGU_BCR(bcrndx);
|
||||||
putreg32(CGU_BCR_FDRUN, regaddr);
|
putreg32(CGU_BCR_FDRUN, regaddr);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Switch the domain back to its original base frequency */
|
/* Switch the domain back to its original base frequency */
|
||||||
|
|
||||||
lpc313x_selectfreqin(dmnid, basefreq);
|
lpc31_selectfreqin(dmnid, basefreq);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@@ -1,5 +1,5 @@
|
|||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* arch/arm/src/lpc313x/lpc313x_setfreqin.c
|
* arch/arm/src/lpc31xx/lpc31_setfreqin.c
|
||||||
*
|
*
|
||||||
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
|
||||||
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
||||||
@@ -47,7 +47,7 @@
|
|||||||
|
|
||||||
#include <arch/board/board.h>
|
#include <arch/board/board.h>
|
||||||
|
|
||||||
#include "lpc313x_cgudrvr.h"
|
#include "lpc31_cgudrvr.h"
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Pre-processor Definitions
|
* Pre-processor Definitions
|
||||||
@@ -70,18 +70,18 @@
|
|||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
/****************************************************************************
|
/****************************************************************************
|
||||||
* Name: lpc313x_selectfreqin
|
* Name: lpc31_selectfreqin
|
||||||
*
|
*
|
||||||
* Description:
|
* Description:
|
||||||
* Set the base frequency source selection for with a clock domain
|
* Set the base frequency source selection for with a clock domain
|
||||||
*
|
*
|
||||||
****************************************************************************/
|
****************************************************************************/
|
||||||
|
|
||||||
void lpc313x_selectfreqin(enum lpc313x_domainid_e dmnid, uint32_t finsel)
|
void lpc31_selectfreqin(enum lpc31_domainid_e dmnid, uint32_t finsel)
|
||||||
{
|
{
|
||||||
uint32_t scraddr = LPC313X_CGU_SCR(dmnid);
|
uint32_t scraddr = LPC31_CGU_SCR(dmnid);
|
||||||
uint32_t fs1addr = LPC313X_CGU_FS1(dmnid);
|
uint32_t fs1addr = LPC31_CGU_FS1(dmnid);
|
||||||
uint32_t fs2addr = LPC313X_CGU_FS2(dmnid);
|
uint32_t fs2addr = LPC31_CGU_FS2(dmnid);
|
||||||
uint32_t scrbits;
|
uint32_t scrbits;
|
||||||
|
|
||||||
/* Get the frequency selection from the switch configuration register (SCR)
|
/* Get the frequency selection from the switch configuration register (SCR)
|
||||||
@@ -92,7 +92,7 @@ void lpc313x_selectfreqin(enum lpc313x_domainid_e dmnid, uint32_t finsel)
|
|||||||
|
|
||||||
/* If FS1 is currently enabled set the reference clock to FS2 and enable FS2 */
|
/* If FS1 is currently enabled set the reference clock to FS2 and enable FS2 */
|
||||||
|
|
||||||
if ((getreg32(LPC313X_CGU_SSR(dmnid)) & CGU_SSR_FS1STAT) != 0)
|
if ((getreg32(LPC31_CGU_SSR(dmnid)) & CGU_SSR_FS1STAT) != 0)
|
||||||
{
|
{
|
||||||
/* Check if the selected frequency, FS1, is same as requested */
|
/* Check if the selected frequency, FS1, is same as requested */
|
||||||
|
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user