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arch: xtensa: fix nxstyle errors

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Fix for errors reported by nxstyle tool

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea
2021-04-07 13:59:24 +02:00
committed by Xiang Xiao
parent 55ca83cbc9
commit cb2ecefbf1
6 changed files with 481 additions and 414 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/xtensa/include/esp32/core-isa.h
+38 -15
View File
@@ -31,6 +31,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option
* is configured, and a value of 0 otherwise. These macros are always
* defined.
@@ -64,8 +65,11 @@
#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
#define XCHAL_HAVE_ABS 1 /* ABS instruction */
/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
/* #define XCHAL_HAVE_POPC 0 POPC instruction */
/* #define XCHAL_HAVE_CRC 0 CRC instruction */
#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
#define XCHAL_HAVE_SPECULATION 0 /* speculation */
@@ -121,6 +125,7 @@
#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
#define XCHAL_HAVE_DFP_ACCEL 1 /* double precision FP acceleration pkg */
#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
#define XCHAL_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */
@@ -155,7 +160,11 @@
* (1 = 5-stage, 2 = 7-stage) */
#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
/* In T1050, applies to selected core load and store instructions (see ISA): */
/* In T1050,
* applies to selected core load and store instructions (see ISA):
*/
#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */
#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/
#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */
@@ -166,25 +175,27 @@
#define XCHAL_CORE_ID "esp32_v3_49_prod"
/* alphanum core name
* (CoreID) set in the Xtensa
* Processor Generator */
* Processor Generator
*/
#define XCHAL_BUILD_UNIQUE_ID 0x0005fe96 /* 22-bit sw build ID */
/*
* These definitions describe the hardware targeted by this software.
*/
/* These definitions describe the hardware targeted by this software. */
#define XCHAL_HW_CONFIGID0 0xc2bcfffe /* ConfigID hi 32 bits*/
#define XCHAL_HW_CONFIGID1 0x1cc5fe96 /* ConfigID lo 32 bits*/
#define XCHAL_HW_VERSION_NAME "LX6.0.3" /* full version name */
#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */
#define XCHAL_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */
#define XCHAL_HW_VERSION 260003 /* major*100+minor */
#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */
#define XCHAL_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */
#define XCHAL_HW_VERSION 260003 /* major*100+minor */
#define XCHAL_HW_REL_LX6 1
#define XCHAL_HW_REL_LX6_0 1
#define XCHAL_HW_REL_LX6_0_3 1
#define XCHAL_HW_CONFIGID_RELIABLE 1
/* If software targets a *range* of hardware versions, these are the bounds: */
/* If software targets a *range* of hardware versions,
* these are the bounds:
*/
#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */
#define XCHAL_HW_MIN_VERSION_MINOR 3 /* minor v of earliest tgt hw */
@@ -273,6 +284,7 @@
#define XCHAL_INSTROM0_VADDR 0x40800000 /* virtual address */
#define XCHAL_INSTROM0_PADDR 0x40800000 /* physical address */
#define XCHAL_INSTROM0_SIZE 4194304 /* size in bytes */
#define XCHAL_INSTROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
/* Instruction RAM 0: */
@@ -280,6 +292,7 @@
#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */
#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */
#define XCHAL_INSTRAM0_SIZE 4194304 /* size in bytes */
#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
/* Instruction RAM 1: */
@@ -287,6 +300,7 @@
#define XCHAL_INSTRAM1_VADDR 0x40400000 /* virtual address */
#define XCHAL_INSTRAM1_PADDR 0x40400000 /* physical address */
#define XCHAL_INSTRAM1_SIZE 4194304 /* size in bytes */
#define XCHAL_INSTRAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */
/* Data ROM 0: */
@@ -294,6 +308,7 @@
#define XCHAL_DATAROM0_VADDR 0x3F400000 /* virtual address */
#define XCHAL_DATAROM0_PADDR 0x3F400000 /* physical address */
#define XCHAL_DATAROM0_SIZE 4194304 /* size in bytes */
#define XCHAL_DATAROM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_DATAROM0_BANKS 1 /* number of banks */
@@ -301,6 +316,7 @@
#define XCHAL_DATARAM0_VADDR 0x3FF80000 /* virtual address */
#define XCHAL_DATARAM0_PADDR 0x3FF80000 /* physical address */
#define XCHAL_DATARAM0_SIZE 524288 /* size in bytes */
#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
@@ -309,6 +325,7 @@
#define XCHAL_DATARAM1_VADDR 0x3F800000 /* virtual address */
#define XCHAL_DATARAM1_PADDR 0x3F800000 /* physical address */
#define XCHAL_DATARAM1_SIZE 4194304 /* size in bytes */
#define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_DATARAM1_BANKS 1 /* number of banks */
@@ -316,9 +333,9 @@
#define XCHAL_XLMI0_VADDR 0x3FF00000 /* virtual address */
#define XCHAL_XLMI0_PADDR 0x3FF00000 /* physical address */
#define XCHAL_XLMI0_SIZE 524288 /* size in bytes */
#define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_XLMI0_SIZE 524288 /* size in bytes */
#define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
/* Interrupts and Timers ****************************************************/
@@ -332,9 +349,11 @@
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
#define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */
#define XCHAL_INT_NLEVELS 6 /* number of interrupt levels
(not including level zero) */
* (not including level zero) */
#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
/* (always 1 in XEA1;
* levels 2 .. EXCM_LEVEL are
* "medium priority") */
/* Masks of interrupts at each interrupt level: */
@@ -494,7 +513,9 @@
#define XCHAL_EXTINT23_NUM 28 /* (intlevel 4) */
#define XCHAL_EXTINT24_NUM 30 /* (intlevel 4) */
#define XCHAL_EXTINT25_NUM 31 /* (intlevel 5) */
/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
@@ -537,6 +558,7 @@
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
#define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */
#define XCHAL_VECBASE_RESET_PADDR 0x40000000
#define XCHAL_RESET_VECBASE_OVERLAP 0
@@ -629,6 +651,7 @@
#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
* [autorefill] and protection)
* usable for an MMU-based OS */
/* If none of the above last 4 are set, it's a custom TLB configuration. */
#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
arch/xtensa/include/esp32/tie-asm.h
+235 -230
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File diff suppressed because it is too large Load Diff
arch/xtensa/include/esp32/tie.h
+10 -9
View File
@@ -8,7 +8,8 @@
* that extend basic Xtensa core functionality. It is customized to this
* Xtensa processor configuration.
*
* Customer ID=11657; Build=0x5fe96; Copyright (c) 1999-2016 Cadence Design Systems Inc.
* Customer ID=11657; Build=0x5fe96;
* Copyright (c) 1999-2016 Cadence Design Systems Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
@@ -107,13 +108,13 @@
* To filter out certain registers, e.g. to expand only the non-global
* registers used by the compiler, you can do something like this:
*
* #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
* #define SELCC0(p...)
* #define SELCC1(abikind,p...) SELAK##abikind(p)
* #define SELAK0(p...) REG(p)
* #define SELAK1(p...) REG(p)
* #define SELAK2(p...)
* #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
* #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
* #define SELCC0(p...)
* #define SELCC1(abikind,p...) SELAK##abikind(p)
* #define SELAK0(p...) REG(p)
* #define SELAK1(p...) REG(p)
* #define SELAK2(p...)
* #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
* ...what you want to expand...
*/
@@ -190,4 +191,4 @@
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\
3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3
#endif /*_ARCH_XTENSA_INCLUDE_ESP32_TIE_H*/
#endif /* _ARCH_XTENSA_INCLUDE_ESP32_TIE_H */
arch/xtensa/include/xtensa/core.h
+171 -151
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File diff suppressed because it is too large Load Diff
arch/xtensa/include/xtensa/xtensa_coproc.h
+3 -1
View File
@@ -46,7 +46,9 @@
#if XCHAL_CP_NUM > 0
/* Align a value up/down to nearest n-byte boundary, where n is a power of 2. */
/* Align a value up/down to nearest n-byte boundary,
* where n is a power of 2.
*/
#define _CP_MASK(n) ((n) - 1)
#define _CP_ALIGNUP(n,val) (((val) + _CP_MASK(n)) & ~_CP_MASK(n))
arch/xtensa/include/xtensa/xtensa_corebits.h
+24 -8
View File
@@ -65,25 +65,40 @@
#define EXCCAUSE_SPECULATION 7 /* Use of Failed Speculative Access (not implemented) */
#define EXCCAUSE_PRIVILEGED 8 /* Privileged Instruction */
#define EXCCAUSE_UNALIGNED 9 /* Unaligned Load or Store */
/* Reserved 10-11 */
#define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */
#define EXCCAUSE_INSTR_DATA_ERROR 12 /* PIF Data Error on Instruction Fetch (RB-200x and later) */
#define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 /* PIF Data Error on Load or Store (RB-200x and later) */
#define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */
#define EXCCAUSE_INSTR_ADDR_ERROR 14 /* PIF Address Error on Instruction Fetch (RB-200x and later) */
#define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 /* PIF Address Error on Load or Store (RB-200x and later) */
#define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw refill also missed) */
#define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries match) */
#define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction Fetch */
/* Reserved 19 *//* Size Restriction on IFetch (not implemented) */
#define EXCCAUSE_ITLB_MISS 16 /* ITLB Miss (no ITLB entry matches, hw refill also missed) */
#define EXCCAUSE_ITLB_MULTIHIT 17 /* ITLB Multihit (multiple ITLB entries match) */
#define EXCCAUSE_INSTR_RING 18 /* Ring Privilege Violation on Instruction Fetch */
/* Reserved 19 Size Restriction on IFetch
* (not implemented)
*/
#define EXCCAUSE_INSTR_PROHIBITED 20 /* Cache Attribute does not allow Instruction Fetch */
/* Reserved 21..23 */
#define EXCCAUSE_DTLB_MISS 24 /* DTLB Miss (no DTLB entry matches, hw refill also missed) */
#define EXCCAUSE_DTLB_MULTIHIT 25 /* DTLB Multihit (multiple DTLB entries match) */
#define EXCCAUSE_LOAD_STORE_RING 26 /* Ring Privilege Violation on Load or Store */
/* Reserved 27 *//* Size Restriction on Load/Store (not implemented) */
/* Reserved 27 Size Restriction on Load/Store
* (not implemented)
*/
#define EXCCAUSE_LOAD_PROHIBITED 28 /* Cache Attribute does not allow Load */
#define EXCCAUSE_STORE_PROHIBITED 29 /* Cache Attribute does not allow Store */
/* Reserved 30-31 */
#define EXCCAUSE_CP_DISABLED(n) (32+(n)) /* Access to Coprocessor 'n' when disabled */
# define EXCCAUSE_CP0_DISABLED 32 /* Access to Coprocessor 0 when disabled */
# define EXCCAUSE_CP1_DISABLED 33 /* Access to Coprocessor 1 when disabled */
# define EXCCAUSE_CP2_DISABLED 34 /* Access to Coprocessor 2 when disabled */
@@ -92,6 +107,7 @@
# define EXCCAUSE_CP5_DISABLED 37 /* Access to Coprocessor 5 when disabled */
# define EXCCAUSE_CP6_DISABLED 38 /* Access to Coprocessor 6 when disabled */
# define EXCCAUSE_CP7_DISABLED 39 /* Access to Coprocessor 7 when disabled */
/* Reserved 40..63 */
/* PS register fields: */
@@ -203,4 +219,4 @@
#define MEMCTL_DCW_CLR_MASK (MEMCTL_DCWU_CLR_MASK | MEMCTL_DCWA_CLR_MASK)
#define MEMCTL_IDCW_CLR_MASK (MEMCTL_DCW_CLR_MASK | MEMCTL_ICWU_CLR_MASK)
#endif /*__ARCH_EXTENSA_INCLUDE_XTENSA_XTENSA_COREBITS_H*/
#endif /* __ARCH_EXTENSA_INCLUDE_XTENSA_XTENSA_COREBITS_H */