diff --git a/arch/arm/src/tms570/chip/tms570_sys.h b/arch/arm/src/tms570/chip/tms570_sys.h
index 220998feb7b..02227702e80 100644
--- a/arch/arm/src/tms570/chip/tms570_sys.h
+++ b/arch/arm/src/tms570/chip/tms570_sys.h
@@ -177,23 +177,40 @@
 /* Register Bit-Field Definitions *******************************************************************/
 
 /* SYS Pin Control Register 1 */
-#define SYS_PC1_
+
+#define SYS_PC1_ECPCLKFUN               (1 << 0)  /* Bit 0: ECLK function */
+
 /* SYS Pin Control Register 2 */
-#define SYS_PC2_
+
+#define SYS_PC2_ECPCLKDIR               (1 << 0)  /* Bit 0: ECLK data direction */
+
 /* SYS Pin Control Register 3 */
-#define SYS_PC3_
+
+#define SYS_PC3_ECPCLKDIN               (1 << 0)  /* Bit 0: ECLK data in */
+
 /* SYS Pin Control Register 4 */
-#define SYS_PC4_
+
+#define SYS_PC4_ECPCLKDOUT              (1 << 0)  /* Bit 0: ECLK data out write */
+
 /* SYS Pin Control Register 5 */
-#define SYS_PC5_
+
+#define SYS_PC5_ECPCLKSET               (1 << 0)  /* Bit 0: ECLK data out set */
+
 /* SYS Pin Control Register 6 */
-#define SYS_PC6_
+
+#define SYS_PC6_ECPCLKCLR               (1 << 0)  /* Bit 0: ECLK data out clear */
+
 /* SYS Pin Control Register 7 */
-#define SYS_PC7_
+
+#define SYS_PC7_ECPCLKODE               (1 << 0)  /* Bit 0: ECLK open drain enable */
+
 /* SYS Pin Control Register 8 */
-#define SYS_PC8_
+
+#define SYS_PC8_ECPCLKPUE               (1 << 0)  /* Bit 0: ECLK pull enable */
+
 /* SYS Pin Control Register 9 */
-#define SYS_PC9_
+
+#define SYS_PC9_ECPCLKPS                (1 << 0)  /* Bit 0: ECLK pull up/pull down select */
 
 /* Clock Source Disable Register, Clock Source Disable Set Register, and Clock Source
  * Disable Clear Register
@@ -434,7 +451,9 @@
 #define SYS_PLLCTL2_FMENA               (1 << 31) /* Bit 31:  Frequency Modulation Enable */
 
 /* SYS Pin Control Register 10 */
-#define SYS_PC10_
+
+#define SYS_PC10_ECLCSLEW               (1 << 0)  /* Bit 0: ECLK slew control */
+
 /* Die Identification Register, Lower Word */
 #define SYS_DIEIDL_
 /* Die Identification Register, Upper Word */
@@ -552,7 +571,18 @@
 #  define SYS_CLKCNTL_VCLKR2_DIV2       (1 << SYS_CLKCNTL_VCLKR2_SHIFT)
 
 /* ECP Control Register */
-#define SYS_ECPCNTL_
+
+#define SYS_ECPCNTL_ECPDIV_SHIFT        (0)       /* Bits 0-15: ECP divider value */
+#define SYS_ECPCNTL_ECPDIV_MASK         (0xffff << SYS_ECPCNTL_ECPDIV_SHIFT)
+#  define SYS_ECPCNTL_ECPDIV(n)         ((uint32_t)(n) << SYS_ECPCNTL_ECPDIV_SHIFT)
+#define SYS_ECPCNTL_ECPINSEL_SHIFT      (16)      /* Bits 16-17: Select ECP input clock source */
+#define SYS_ECPCNTL_ECPINSEL_MASK       (3 << SYS_ECPCNTL_ECPINSEL_SHIFT)
+#  define SYS_ECPCNTL_ECPINSEL_LOW      (0 << SYS_ECPCNTL_ECPINSEL_SHIFT) /* Tied Low */
+#  define SYS_ECPCNTL_ECPINSEL_HCLK     (1 << SYS_ECPCNTL_ECPINSEL_SHIFT) /* HCLK */
+#  define SYS_ECPCNTL_ECPINSEL_EXTCLK   (2 << SYS_ECPCNTL_ECPINSEL_SHIFT) /* External clock */
+#define SYS_ECPCNTL_ECPCOS              (1 << 23) /* Bit 23: ECP continue on suspend */
+#define SYS_ECPCNTL_ECPSSEL             (1 << 24) /* Bit 24: Select VCLK os OSCIN as for ECLK */
+
 /* DEV Parity Control Register 1 */
 #define SYS_DEVCR1_
 /* System Exception Control Register */
diff --git a/arch/arm/src/tms570/tms570_clockconfig.c b/arch/arm/src/tms570/tms570_clockconfig.c
index b0bded9fd2e..94c42e8a753 100644
--- a/arch/arm/src/tms570/tms570_clockconfig.c
+++ b/arch/arm/src/tms570/tms570_clockconfig.c
@@ -333,6 +333,39 @@ static void tms570_clocksrc_configure(void)
   putreg32(SYS_VCLKASRC_VCLKA1S_VCLK, TMS570_SYS_VCLKASRC);
 }
 
+static void tms570_eclk_configure(void)
+{
+  uint32_t regval;
+
+  /* Configure ECLK pins
+   *
+   * PC1 0=ECLK is in GIO mode
+   * PC4 0=ECLK pin is driven to logic low
+   * PC2 1=ECLK pin is an output
+   * PC7 0=CLK pin is configured in push/pull mode
+   * PC8 0=ECLK pull enable is active
+   * PC9 1=ECLK pull up is selected, when pull up/pull down logic is enabled
+   */
+
+  putreg32(0, TMS570_SYS_PC1);
+  putreg32(0, TMS570_SYS_PC4);
+  putreg32(SYS_PC2_ECPCLKDIR, TMS570_SYS_PC2);
+  putreg32(0, TMS570_SYS_PC7);
+  putreg32(0, TMS570_SYS_PC8);
+  putreg32(SYS_PC9_ECPCLKPS, TMS570_SYS_PC9);
+
+  /* Setup ECLK:
+   *
+   * ECPDIV=7   Bits 0-15, ECP divider value = 8
+   * ECPINSEL=0 Bits 16-17, Select ECP input clock source is tied low
+   * ECPCOS=0   Bit 23, ECLK output is disabled in suspend mode
+   * ECPINSEL=0 Bit 24, VCLK is selected as the ECP clock source
+   */
+
+  regval = SYS_ECPCNTL_ECPDIV(8-1) | SYS_ECPCNTL_ECPINSEL_LOW;
+  putreg32(regval, TMS570_SYS_ECPCNTL);
+}
+
 /****************************************************************************
  * Public Functions
  ****************************************************************************/
@@ -368,7 +401,7 @@ void tms570_clockconfig(void)
   tms570_peripheral_initialize();
 
   /* Configure device-level multiplexing and I/O multiplexing */
-#  warning Missing Logic
+#warning Missing Logic
 
 #ifdef CONFIG_TMS570_SELFTEST
   /* Wait for eFuse controller self-test to complete and check results */
@@ -390,26 +423,7 @@ void tms570_clockconfig(void)
 
   tms570_clocksrc_configure();
 
-#warning Missing Logic
+  /* Configure ECLK */
 
-  /* Set ECLK pins functional mode */
-#warning Missing Logic
-
-  /* Set ECLK pins default output value */
-#warning Missing Logic
-
-  /* Set ECLK pins output direction */
-#warning Missing Logic
-
-  /* Set ECLK pins open drain enable */
-#warning Missing Logic
-
-  /* Set ECLK pins pullup/pulldown enable */
-#warning Missing Logic
-
-  /* Set ECLK pins pullup/pulldown select */
-#warning Missing Logic
-
-  /* Setup ECLK */
-#warning Missing Logic
+  tms570_eclk_configure();
 }